SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.97 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.44 |
T1007 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3576129496 | Jul 19 04:51:48 PM PDT 24 | Jul 19 04:51:50 PM PDT 24 | 32326811 ps | ||
T1008 | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3404706531 | Jul 19 04:51:36 PM PDT 24 | Jul 19 04:51:41 PM PDT 24 | 16782581 ps | ||
T1009 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2409429576 | Jul 19 04:52:08 PM PDT 24 | Jul 19 04:52:11 PM PDT 24 | 16561880 ps | ||
T1010 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1023827188 | Jul 19 04:51:44 PM PDT 24 | Jul 19 04:51:47 PM PDT 24 | 171803499 ps | ||
T1011 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3945096114 | Jul 19 04:52:25 PM PDT 24 | Jul 19 04:52:32 PM PDT 24 | 734014326 ps | ||
T1012 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2345456101 | Jul 19 04:51:33 PM PDT 24 | Jul 19 04:51:42 PM PDT 24 | 1418109474 ps | ||
T1013 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2154104073 | Jul 19 04:51:44 PM PDT 24 | Jul 19 04:51:49 PM PDT 24 | 768379367 ps | ||
T1014 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2167645683 | Jul 19 04:51:34 PM PDT 24 | Jul 19 04:51:40 PM PDT 24 | 12562147 ps | ||
T138 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4236535519 | Jul 19 04:51:45 PM PDT 24 | Jul 19 04:51:50 PM PDT 24 | 671092416 ps | ||
T1015 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3122577440 | Jul 19 04:52:21 PM PDT 24 | Jul 19 04:52:28 PM PDT 24 | 153564311 ps | ||
T1016 | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.793250006 | Jul 19 04:52:03 PM PDT 24 | Jul 19 04:52:08 PM PDT 24 | 67159139 ps | ||
T102 | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.277805384 | Jul 19 04:52:26 PM PDT 24 | Jul 19 04:53:26 PM PDT 24 | 14703479670 ps | ||
T1017 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.973007364 | Jul 19 04:52:06 PM PDT 24 | Jul 19 04:52:11 PM PDT 24 | 393486855 ps | ||
T1018 | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4233527009 | Jul 19 04:52:23 PM PDT 24 | Jul 19 04:52:26 PM PDT 24 | 50965040 ps | ||
T1019 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1479700182 | Jul 19 04:51:35 PM PDT 24 | Jul 19 04:51:43 PM PDT 24 | 65466328 ps | ||
T1020 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3551125655 | Jul 19 04:52:25 PM PDT 24 | Jul 19 04:52:32 PM PDT 24 | 43430776 ps | ||
T1021 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2352676567 | Jul 19 04:51:47 PM PDT 24 | Jul 19 04:51:53 PM PDT 24 | 354690718 ps | ||
T107 | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2642382325 | Jul 19 04:52:22 PM PDT 24 | Jul 19 04:52:55 PM PDT 24 | 13658874475 ps | ||
T1022 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1417379093 | Jul 19 04:51:32 PM PDT 24 | Jul 19 04:51:37 PM PDT 24 | 66117545 ps | ||
T1023 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3432512089 | Jul 19 04:52:00 PM PDT 24 | Jul 19 04:52:05 PM PDT 24 | 1442974035 ps | ||
T103 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3468086639 | Jul 19 04:51:44 PM PDT 24 | Jul 19 04:52:14 PM PDT 24 | 7418526744 ps | ||
T1024 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1220692372 | Jul 19 04:51:36 PM PDT 24 | Jul 19 04:52:09 PM PDT 24 | 7565855438 ps | ||
T1025 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.880445881 | Jul 19 04:52:17 PM PDT 24 | Jul 19 04:52:19 PM PDT 24 | 33896545 ps | ||
T1026 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3087139615 | Jul 19 04:52:22 PM PDT 24 | Jul 19 04:52:26 PM PDT 24 | 63443214 ps | ||
T1027 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1833305140 | Jul 19 04:52:06 PM PDT 24 | Jul 19 04:52:08 PM PDT 24 | 13848344 ps | ||
T1028 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2539254116 | Jul 19 04:52:07 PM PDT 24 | Jul 19 04:52:12 PM PDT 24 | 93220545 ps | ||
T104 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.412036071 | Jul 19 04:51:35 PM PDT 24 | Jul 19 04:51:41 PM PDT 24 | 101088111 ps | ||
T1029 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3760452623 | Jul 19 04:51:34 PM PDT 24 | Jul 19 04:51:40 PM PDT 24 | 64109243 ps | ||
T1030 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.544033197 | Jul 19 04:52:15 PM PDT 24 | Jul 19 04:52:19 PM PDT 24 | 119435387 ps | ||
T1031 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.33966172 | Jul 19 04:52:25 PM PDT 24 | Jul 19 04:52:32 PM PDT 24 | 1274266381 ps | ||
T133 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2584857596 | Jul 19 04:51:57 PM PDT 24 | Jul 19 04:52:02 PM PDT 24 | 278133365 ps | ||
T1032 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.878730412 | Jul 19 04:51:46 PM PDT 24 | Jul 19 04:51:51 PM PDT 24 | 126142497 ps | ||
T1033 | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1453165283 | Jul 19 04:51:44 PM PDT 24 | Jul 19 04:51:48 PM PDT 24 | 96561913 ps |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.1191150334 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 57495930977 ps |
CPU time | 581.56 seconds |
Started | Jul 19 06:09:31 PM PDT 24 |
Finished | Jul 19 06:19:13 PM PDT 24 |
Peak memory | 365552 kb |
Host | smart-3b97ddda-0e62-4c0a-a08c-47fcbdf0e141 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191150334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.1191150334 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3098116425 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 8006112588 ps |
CPU time | 109.04 seconds |
Started | Jul 19 06:05:54 PM PDT 24 |
Finished | Jul 19 06:07:47 PM PDT 24 |
Peak memory | 334820 kb |
Host | smart-5f3c2030-a426-4fa2-926d-c77d1d95bd77 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3098116425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3098116425 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3180054149 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 3472547735 ps |
CPU time | 24.97 seconds |
Started | Jul 19 06:04:37 PM PDT 24 |
Finished | Jul 19 06:05:03 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-0778b24e-51b0-4148-aaa1-d4043a4a8ea2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3180054149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3180054149 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.1527961659 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 122336423403 ps |
CPU time | 112.26 seconds |
Started | Jul 19 06:12:21 PM PDT 24 |
Finished | Jul 19 06:14:13 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-d1a61b4e-7b54-4153-94bb-78a402e1e667 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527961659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.1527961659 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.1388940142 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 152390505487 ps |
CPU time | 8246.72 seconds |
Started | Jul 19 06:05:23 PM PDT 24 |
Finished | Jul 19 08:22:52 PM PDT 24 |
Peak memory | 381872 kb |
Host | smart-7d880f1b-9eea-4199-9fef-9577f327d71e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388940142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.1388940142 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2053886403 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 212338073 ps |
CPU time | 2.5 seconds |
Started | Jul 19 04:52:22 PM PDT 24 |
Finished | Jul 19 04:52:26 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-9425dbfb-a45d-4ccb-9c05-bef5659b6032 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053886403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.2053886403 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.4186532417 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 294907198 ps |
CPU time | 3.39 seconds |
Started | Jul 19 06:03:54 PM PDT 24 |
Finished | Jul 19 06:03:58 PM PDT 24 |
Peak memory | 222096 kb |
Host | smart-d40a8f1a-49d5-4b61-9f11-119970f92bd1 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186532417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.4186532417 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1748424240 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 6032057997 ps |
CPU time | 91.47 seconds |
Started | Jul 19 06:10:20 PM PDT 24 |
Finished | Jul 19 06:11:52 PM PDT 24 |
Peak memory | 219180 kb |
Host | smart-05d3a937-9bec-4815-99e2-a6cdba033326 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748424240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.1748424240 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4176890675 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 55027335276 ps |
CPU time | 329.13 seconds |
Started | Jul 19 06:05:18 PM PDT 24 |
Finished | Jul 19 06:10:50 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-963ba5ae-0926-4c6b-ae43-cde239672e55 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176890675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.4176890675 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3403691636 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 7239471377 ps |
CPU time | 190.5 seconds |
Started | Jul 19 06:08:16 PM PDT 24 |
Finished | Jul 19 06:12:02 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-fbde4bb8-efb5-4453-bd91-d1c3080fbf26 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403691636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3403691636 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.1543240795 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 35531679 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:03:53 PM PDT 24 |
Finished | Jul 19 06:03:54 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-c89421d5-69eb-4281-9654-64d1b4a959d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543240795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1543240795 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.845635161 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 7309603114 ps |
CPU time | 47.3 seconds |
Started | Jul 19 04:52:07 PM PDT 24 |
Finished | Jul 19 04:52:57 PM PDT 24 |
Peak memory | 203468 kb |
Host | smart-81dbce60-4d2b-4e70-b957-06e240ac609a |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845635161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.845635161 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.1229419398 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 925153451782 ps |
CPU time | 6239.68 seconds |
Started | Jul 19 06:05:41 PM PDT 24 |
Finished | Jul 19 07:49:45 PM PDT 24 |
Peak memory | 380604 kb |
Host | smart-b533b9e7-26f2-4b0d-bad2-0d78d9a0d40c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229419398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.1229419398 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.457619902 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 694070936 ps |
CPU time | 3.33 seconds |
Started | Jul 19 06:06:55 PM PDT 24 |
Finished | Jul 19 06:07:00 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-dd7ebbd3-8801-4134-acbd-0323b36dfe78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457619902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.457619902 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2562204057 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 4515740551 ps |
CPU time | 33.57 seconds |
Started | Jul 19 06:07:15 PM PDT 24 |
Finished | Jul 19 06:07:49 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-a896fa95-f277-44b2-bb24-71412bd86d9c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2562204057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2562204057 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.568309155 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 761443380 ps |
CPU time | 1.55 seconds |
Started | Jul 19 04:52:14 PM PDT 24 |
Finished | Jul 19 04:52:16 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-39749172-e3f6-4b6d-bbc3-a7266d04ddd8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568309155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.sram_ctrl_tl_intg_err.568309155 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4269056047 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 942988143 ps |
CPU time | 2.42 seconds |
Started | Jul 19 04:51:56 PM PDT 24 |
Finished | Jul 19 04:52:01 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-3d0f3b75-f65f-420e-8911-516febb3d923 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269056047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.4269056047 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.277805384 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 14703479670 ps |
CPU time | 56.46 seconds |
Started | Jul 19 04:52:26 PM PDT 24 |
Finished | Jul 19 04:53:26 PM PDT 24 |
Peak memory | 203596 kb |
Host | smart-bc78d1eb-9e2c-4a92-aafa-4053fe32c18e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277805384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.277805384 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.3592910398 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 34833710758 ps |
CPU time | 83.07 seconds |
Started | Jul 19 06:05:59 PM PDT 24 |
Finished | Jul 19 06:07:24 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-efccb1ec-f48d-4dfc-9f24-c900c997f0f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592910398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.3592910398 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1277307495 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 662139796 ps |
CPU time | 2.57 seconds |
Started | Jul 19 04:52:07 PM PDT 24 |
Finished | Jul 19 04:52:12 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-33e0d472-d63b-4868-b602-e1dca9b6dc7a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277307495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.1277307495 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.394517246 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 32485795 ps |
CPU time | 0.77 seconds |
Started | Jul 19 04:51:34 PM PDT 24 |
Finished | Jul 19 04:51:40 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-5f79578e-80e3-43d2-b05b-4c5a434127b2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394517246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.394517246 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2581143912 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 47938070 ps |
CPU time | 1.3 seconds |
Started | Jul 19 04:51:32 PM PDT 24 |
Finished | Jul 19 04:51:38 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-8135c914-40c7-4381-8271-5e3a75466025 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581143912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.2581143912 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2104946714 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 18934082 ps |
CPU time | 0.69 seconds |
Started | Jul 19 04:51:33 PM PDT 24 |
Finished | Jul 19 04:51:38 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-a851c420-3807-4be5-9869-1fba88970601 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104946714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.2104946714 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2345456101 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 1418109474 ps |
CPU time | 3.92 seconds |
Started | Jul 19 04:51:33 PM PDT 24 |
Finished | Jul 19 04:51:42 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-d25c77b6-bdf6-4ae6-83f3-c9c0fd1ef99b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345456101 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2345456101 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3599876667 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 98683107 ps |
CPU time | 0.65 seconds |
Started | Jul 19 04:51:32 PM PDT 24 |
Finished | Jul 19 04:51:38 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-644cf629-32c3-4adc-bcbb-dbd090be121d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599876667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.3599876667 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1220692372 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 7565855438 ps |
CPU time | 28.25 seconds |
Started | Jul 19 04:51:36 PM PDT 24 |
Finished | Jul 19 04:52:09 PM PDT 24 |
Peak memory | 203312 kb |
Host | smart-59320580-6fcb-45ab-ae7c-eb86dd1ce72f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220692372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1220692372 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3404706531 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 16782581 ps |
CPU time | 0.8 seconds |
Started | Jul 19 04:51:36 PM PDT 24 |
Finished | Jul 19 04:51:41 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-96784b77-5b87-4619-860f-b7fe6ccbbb6c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404706531 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3404706531 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2616814273 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 263359512 ps |
CPU time | 5 seconds |
Started | Jul 19 04:51:33 PM PDT 24 |
Finished | Jul 19 04:51:43 PM PDT 24 |
Peak memory | 211456 kb |
Host | smart-656b6360-0463-495e-aff0-7931bef91a14 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616814273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.2616814273 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4140065197 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 175873805 ps |
CPU time | 1.57 seconds |
Started | Jul 19 04:51:33 PM PDT 24 |
Finished | Jul 19 04:51:39 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-07bd089f-37b9-4a24-bd29-1de9e6027034 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140065197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.4140065197 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1417379093 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 66117545 ps |
CPU time | 0.78 seconds |
Started | Jul 19 04:51:32 PM PDT 24 |
Finished | Jul 19 04:51:37 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-00846929-f2f6-407b-85e5-6b7f570ef274 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417379093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.1417379093 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.118080357 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 249791048 ps |
CPU time | 2.13 seconds |
Started | Jul 19 04:51:33 PM PDT 24 |
Finished | Jul 19 04:51:41 PM PDT 24 |
Peak memory | 203168 kb |
Host | smart-51c6d3bc-5782-4c92-a50b-4332b48a4144 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118080357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit_bash.118080357 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.412036071 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 101088111 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:51:35 PM PDT 24 |
Finished | Jul 19 04:51:41 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-21f04832-a87d-4e67-8f01-6d451820805b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412036071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_reset.412036071 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.89187937 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 1409067018 ps |
CPU time | 3.95 seconds |
Started | Jul 19 04:51:35 PM PDT 24 |
Finished | Jul 19 04:51:44 PM PDT 24 |
Peak memory | 211208 kb |
Host | smart-308d9681-4b77-4429-93f4-555d03509c29 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89187937 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.89187937 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2167645683 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 12562147 ps |
CPU time | 0.67 seconds |
Started | Jul 19 04:51:34 PM PDT 24 |
Finished | Jul 19 04:51:40 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-7f61332e-f4c3-4a18-9919-8f42d7aaecf7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167645683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.2167645683 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.565975777 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 29417575828 ps |
CPU time | 54.17 seconds |
Started | Jul 19 04:51:34 PM PDT 24 |
Finished | Jul 19 04:52:33 PM PDT 24 |
Peak memory | 203476 kb |
Host | smart-3cdfeed7-c8b2-4606-a84d-dc071687040e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565975777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.565975777 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3760452623 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 64109243 ps |
CPU time | 0.79 seconds |
Started | Jul 19 04:51:34 PM PDT 24 |
Finished | Jul 19 04:51:40 PM PDT 24 |
Peak memory | 203032 kb |
Host | smart-5bd7470a-27d0-490e-b052-23c0ff1b22a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760452623 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3760452623 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1479700182 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 65466328 ps |
CPU time | 2.92 seconds |
Started | Jul 19 04:51:35 PM PDT 24 |
Finished | Jul 19 04:51:43 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-8a89759b-a6b7-4a9b-9e83-4c29b2fcadc3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479700182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.1479700182 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1371537717 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 466708618 ps |
CPU time | 1.66 seconds |
Started | Jul 19 04:51:34 PM PDT 24 |
Finished | Jul 19 04:51:41 PM PDT 24 |
Peak memory | 211356 kb |
Host | smart-6ba00ac0-e2ce-4029-92fb-6756183e506b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371537717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1371537717 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3432512089 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 1442974035 ps |
CPU time | 3.8 seconds |
Started | Jul 19 04:52:00 PM PDT 24 |
Finished | Jul 19 04:52:05 PM PDT 24 |
Peak memory | 215744 kb |
Host | smart-3b79e563-806c-4cc4-9f5e-9236b93530c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432512089 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3432512089 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2409429576 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 16561880 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:52:08 PM PDT 24 |
Finished | Jul 19 04:52:11 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-335acccd-7996-4c75-8857-820587e97751 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409429576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.2409429576 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.405516295 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 64107316605 ps |
CPU time | 52.53 seconds |
Started | Jul 19 04:52:02 PM PDT 24 |
Finished | Jul 19 04:52:56 PM PDT 24 |
Peak memory | 211688 kb |
Host | smart-5aec61ec-6dd0-4e53-8ec0-eebcae4e2b4f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405516295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.405516295 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.558926110 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 111855428 ps |
CPU time | 0.78 seconds |
Started | Jul 19 04:52:06 PM PDT 24 |
Finished | Jul 19 04:52:09 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-c4020c93-138f-4e72-ba4b-faf5522264d0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558926110 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.558926110 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.793250006 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 67159139 ps |
CPU time | 3.54 seconds |
Started | Jul 19 04:52:03 PM PDT 24 |
Finished | Jul 19 04:52:08 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-f15047b4-994b-484c-9960-984de1477b9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793250006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.793250006 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3100883041 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 733691585 ps |
CPU time | 4.43 seconds |
Started | Jul 19 04:52:07 PM PDT 24 |
Finished | Jul 19 04:52:14 PM PDT 24 |
Peak memory | 212720 kb |
Host | smart-fb3d4d0b-f17a-48bb-bb58-46a7bc679ed7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100883041 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3100883041 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3594205485 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 44450842 ps |
CPU time | 0.73 seconds |
Started | Jul 19 04:52:07 PM PDT 24 |
Finished | Jul 19 04:52:11 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-71063b69-785c-45ac-b24b-51a7b5986f39 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594205485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.3594205485 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1547912926 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 44523946 ps |
CPU time | 0.7 seconds |
Started | Jul 19 04:52:09 PM PDT 24 |
Finished | Jul 19 04:52:11 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-ebde6b8c-2dcc-46a6-a8d8-f04468d2f415 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547912926 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1547912926 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1197266271 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 71522762 ps |
CPU time | 2.79 seconds |
Started | Jul 19 04:52:02 PM PDT 24 |
Finished | Jul 19 04:52:07 PM PDT 24 |
Peak memory | 211552 kb |
Host | smart-6a8518aa-8fde-4bc6-a570-04c9d7c6fb84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197266271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1197266271 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.557677852 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 346617149 ps |
CPU time | 1.57 seconds |
Started | Jul 19 04:51:56 PM PDT 24 |
Finished | Jul 19 04:52:00 PM PDT 24 |
Peak memory | 211428 kb |
Host | smart-81327738-ebdd-4207-8a6a-61190b852c9b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557677852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.sram_ctrl_tl_intg_err.557677852 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.973007364 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 393486855 ps |
CPU time | 3.31 seconds |
Started | Jul 19 04:52:06 PM PDT 24 |
Finished | Jul 19 04:52:11 PM PDT 24 |
Peak memory | 203016 kb |
Host | smart-d9f9d751-34ae-4f01-a132-f2891072415e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973007364 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.973007364 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1833305140 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 13848344 ps |
CPU time | 0.72 seconds |
Started | Jul 19 04:52:06 PM PDT 24 |
Finished | Jul 19 04:52:08 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-862e07d0-33ec-4a76-8422-3805781312e2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833305140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.1833305140 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2062201791 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 10278641267 ps |
CPU time | 27.28 seconds |
Started | Jul 19 04:52:06 PM PDT 24 |
Finished | Jul 19 04:52:36 PM PDT 24 |
Peak memory | 203368 kb |
Host | smart-628d048c-3768-4c9c-899d-4a4f9891f72f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062201791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2062201791 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3245540976 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 88577282 ps |
CPU time | 0.82 seconds |
Started | Jul 19 04:52:06 PM PDT 24 |
Finished | Jul 19 04:52:08 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-9bf5a20b-61be-431b-8fa3-0c7a9708eb8e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245540976 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3245540976 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2539254116 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 93220545 ps |
CPU time | 3.52 seconds |
Started | Jul 19 04:52:07 PM PDT 24 |
Finished | Jul 19 04:52:12 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-52a94ba0-1041-4795-9ad4-305db656571f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539254116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.2539254116 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.880445881 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 33896545 ps |
CPU time | 0.7 seconds |
Started | Jul 19 04:52:17 PM PDT 24 |
Finished | Jul 19 04:52:19 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-40f4d74c-83c6-4a29-a1d5-ae0b6456461e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880445881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.sram_ctrl_csr_rw.880445881 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.635032745 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 7863467320 ps |
CPU time | 28.32 seconds |
Started | Jul 19 04:52:08 PM PDT 24 |
Finished | Jul 19 04:52:38 PM PDT 24 |
Peak memory | 203264 kb |
Host | smart-0fcac167-ef40-4df4-81a2-0760a6b25656 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635032745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.635032745 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.214846107 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 22845007 ps |
CPU time | 0.79 seconds |
Started | Jul 19 04:52:15 PM PDT 24 |
Finished | Jul 19 04:52:17 PM PDT 24 |
Peak memory | 203084 kb |
Host | smart-1b0849a2-05b7-4d59-8a3f-2cc80f660055 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214846107 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.214846107 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2880983373 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 127028613 ps |
CPU time | 4.27 seconds |
Started | Jul 19 04:52:05 PM PDT 24 |
Finished | Jul 19 04:52:10 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-373a6734-d23f-4551-b0e0-4d9242947bd4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880983373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.2880983373 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3869217456 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 291794942 ps |
CPU time | 2.08 seconds |
Started | Jul 19 04:52:18 PM PDT 24 |
Finished | Jul 19 04:52:21 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-66864010-3772-4f44-8a7f-fdae358af72c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869217456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.3869217456 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1417301121 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 371959210 ps |
CPU time | 3.3 seconds |
Started | Jul 19 04:52:14 PM PDT 24 |
Finished | Jul 19 04:52:18 PM PDT 24 |
Peak memory | 211192 kb |
Host | smart-9465e278-6b49-436a-a123-0ae1a72ebf03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417301121 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1417301121 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2365894540 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 24444970 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:52:14 PM PDT 24 |
Finished | Jul 19 04:52:16 PM PDT 24 |
Peak memory | 203136 kb |
Host | smart-6db0017a-a98e-4878-9cf2-d720aa66d759 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365894540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.2365894540 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2296712172 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 9111875574 ps |
CPU time | 53.19 seconds |
Started | Jul 19 04:52:18 PM PDT 24 |
Finished | Jul 19 04:53:12 PM PDT 24 |
Peak memory | 203512 kb |
Host | smart-815cb33e-e2ab-49b7-bef3-88e6b4d6ae99 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296712172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2296712172 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.581022382 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 128229233 ps |
CPU time | 0.88 seconds |
Started | Jul 19 04:52:14 PM PDT 24 |
Finished | Jul 19 04:52:16 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-8d7dd6dd-6b33-422e-a6d2-db6f1ab709e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581022382 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.581022382 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3255879305 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 97879916 ps |
CPU time | 2.24 seconds |
Started | Jul 19 04:52:15 PM PDT 24 |
Finished | Jul 19 04:52:19 PM PDT 24 |
Peak memory | 211444 kb |
Host | smart-6d01471f-e50c-48aa-9ab8-a81bb77036ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255879305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3255879305 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.888047081 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 330785208 ps |
CPU time | 2.31 seconds |
Started | Jul 19 04:52:14 PM PDT 24 |
Finished | Jul 19 04:52:18 PM PDT 24 |
Peak memory | 211504 kb |
Host | smart-90815065-6d8f-404e-bfb5-7a8cba0bbc2f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888047081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.sram_ctrl_tl_intg_err.888047081 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2672895084 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 712316401 ps |
CPU time | 3.27 seconds |
Started | Jul 19 04:52:25 PM PDT 24 |
Finished | Jul 19 04:52:32 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-24228f84-e264-42e7-abdc-d78946a5651d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672895084 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2672895084 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.824646901 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 45114510 ps |
CPU time | 0.73 seconds |
Started | Jul 19 04:52:21 PM PDT 24 |
Finished | Jul 19 04:52:23 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-bc808500-6a81-4028-8dff-e68f7bffa474 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824646901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.sram_ctrl_csr_rw.824646901 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4248646057 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 14778279300 ps |
CPU time | 29.44 seconds |
Started | Jul 19 04:52:18 PM PDT 24 |
Finished | Jul 19 04:52:48 PM PDT 24 |
Peak memory | 203348 kb |
Host | smart-418df53a-02a3-400e-a233-2fe575b424d0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248646057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.4248646057 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1619040369 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 47234014 ps |
CPU time | 0.81 seconds |
Started | Jul 19 04:52:22 PM PDT 24 |
Finished | Jul 19 04:52:26 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-d0b14b8c-61d3-48b5-948f-b719a3c9af43 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619040369 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1619040369 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.544033197 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 119435387 ps |
CPU time | 2.7 seconds |
Started | Jul 19 04:52:15 PM PDT 24 |
Finished | Jul 19 04:52:19 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-aafe8460-b979-4af5-bf55-ffb61bcb61ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544033197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.544033197 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1728586356 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 441037308 ps |
CPU time | 3.71 seconds |
Started | Jul 19 04:52:24 PM PDT 24 |
Finished | Jul 19 04:52:31 PM PDT 24 |
Peak memory | 211476 kb |
Host | smart-c023f2aa-d916-4dad-b3a6-eba0585e7f55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728586356 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1728586356 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1788529421 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 16223528 ps |
CPU time | 0.69 seconds |
Started | Jul 19 04:52:23 PM PDT 24 |
Finished | Jul 19 04:52:27 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-e46049ca-730a-4746-b57b-f49810921968 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788529421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1788529421 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4233527009 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 50965040 ps |
CPU time | 0.81 seconds |
Started | Jul 19 04:52:23 PM PDT 24 |
Finished | Jul 19 04:52:26 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-ed92d0bd-3eee-4e68-acac-6d2741ae9d4c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233527009 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.4233527009 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3122577440 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 153564311 ps |
CPU time | 4.84 seconds |
Started | Jul 19 04:52:21 PM PDT 24 |
Finished | Jul 19 04:52:28 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-59b4fab6-aba0-4139-ac66-811c14201ed0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122577440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.3122577440 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1343035319 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 86442596 ps |
CPU time | 1.41 seconds |
Started | Jul 19 04:52:24 PM PDT 24 |
Finished | Jul 19 04:52:29 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-82491a6b-f5a3-4a4b-9b1b-dfe3f719334e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343035319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.1343035319 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.67772813 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 354533655 ps |
CPU time | 3.75 seconds |
Started | Jul 19 04:52:21 PM PDT 24 |
Finished | Jul 19 04:52:26 PM PDT 24 |
Peak memory | 211548 kb |
Host | smart-f0864d5f-7fe3-42ac-a717-325a685eee5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67772813 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.67772813 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3992127937 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 15345513 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:52:23 PM PDT 24 |
Finished | Jul 19 04:52:27 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-11a2ebd2-7637-47ff-a235-e66238049865 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992127937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.3992127937 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2970361555 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 14434321403 ps |
CPU time | 48.6 seconds |
Started | Jul 19 04:52:22 PM PDT 24 |
Finished | Jul 19 04:53:12 PM PDT 24 |
Peak memory | 203600 kb |
Host | smart-6130531a-af4a-4a68-b004-0534ddb47ce6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970361555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2970361555 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3406646782 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 111442746 ps |
CPU time | 0.73 seconds |
Started | Jul 19 04:52:23 PM PDT 24 |
Finished | Jul 19 04:52:26 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-968bca76-2bfc-4972-82c5-aa0b8948392c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406646782 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3406646782 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3087139615 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 63443214 ps |
CPU time | 2.5 seconds |
Started | Jul 19 04:52:22 PM PDT 24 |
Finished | Jul 19 04:52:26 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-44e522f0-8643-48cc-a52e-ce7648fc3188 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087139615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.3087139615 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1190122683 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 100201863 ps |
CPU time | 1.55 seconds |
Started | Jul 19 04:52:22 PM PDT 24 |
Finished | Jul 19 04:52:26 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-f6758c18-0701-4a14-b833-98b44e40d189 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190122683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.1190122683 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3945096114 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 734014326 ps |
CPU time | 3.63 seconds |
Started | Jul 19 04:52:25 PM PDT 24 |
Finished | Jul 19 04:52:32 PM PDT 24 |
Peak memory | 211312 kb |
Host | smart-99e63a26-f476-4f94-95b3-4e53b0240b83 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945096114 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.3945096114 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1611634654 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 20857359 ps |
CPU time | 0.67 seconds |
Started | Jul 19 04:52:23 PM PDT 24 |
Finished | Jul 19 04:52:27 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-d4324825-e2a8-4421-b205-48cfe1c1db51 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611634654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.1611634654 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1537458716 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 29413487089 ps |
CPU time | 59.51 seconds |
Started | Jul 19 04:52:24 PM PDT 24 |
Finished | Jul 19 04:53:27 PM PDT 24 |
Peak memory | 203492 kb |
Host | smart-0c436253-5a09-4dd1-bddd-54bb3ea99632 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537458716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.1537458716 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1337697719 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 23664663 ps |
CPU time | 0.69 seconds |
Started | Jul 19 04:52:22 PM PDT 24 |
Finished | Jul 19 04:52:24 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-e85c9e8a-d56a-4dc9-8028-aa7e229f349f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337697719 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1337697719 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3213256625 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 591323672 ps |
CPU time | 5 seconds |
Started | Jul 19 04:52:51 PM PDT 24 |
Finished | Jul 19 04:52:57 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-6c978177-957d-486d-82a1-8c3754990fe3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213256625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3213256625 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.33966172 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 1274266381 ps |
CPU time | 3.77 seconds |
Started | Jul 19 04:52:25 PM PDT 24 |
Finished | Jul 19 04:52:32 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-1c471124-453f-4d73-a988-3c14b6c5f45e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33966172 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.33966172 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.805645263 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 14803676 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:52:25 PM PDT 24 |
Finished | Jul 19 04:52:29 PM PDT 24 |
Peak memory | 202988 kb |
Host | smart-1063dae4-1d54-4900-970c-ab0510c562b5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805645263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_csr_rw.805645263 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2642382325 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 13658874475 ps |
CPU time | 30.4 seconds |
Started | Jul 19 04:52:22 PM PDT 24 |
Finished | Jul 19 04:52:55 PM PDT 24 |
Peak memory | 203324 kb |
Host | smart-bc0c436f-b343-4992-aa93-78be198bda84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642382325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2642382325 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3468269976 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 20600775 ps |
CPU time | 0.76 seconds |
Started | Jul 19 04:52:25 PM PDT 24 |
Finished | Jul 19 04:52:29 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-db042239-0f7b-4105-860d-e05b50c93267 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468269976 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3468269976 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3551125655 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 43430776 ps |
CPU time | 3.36 seconds |
Started | Jul 19 04:52:25 PM PDT 24 |
Finished | Jul 19 04:52:32 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-dd50b76d-3536-4ed2-9d26-e509d5d53dc9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551125655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.3551125655 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4061933488 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 1278816268 ps |
CPU time | 1.68 seconds |
Started | Jul 19 04:52:22 PM PDT 24 |
Finished | Jul 19 04:52:27 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-8fa875b2-1fab-4bb5-84df-c3d0ebd06f0c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061933488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.4061933488 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3576129496 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 32326811 ps |
CPU time | 0.67 seconds |
Started | Jul 19 04:51:48 PM PDT 24 |
Finished | Jul 19 04:51:50 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-2380d9c3-a59e-4954-a1fb-c43941bc0fe3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576129496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.3576129496 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3376823769 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 162914415 ps |
CPU time | 2.23 seconds |
Started | Jul 19 04:51:46 PM PDT 24 |
Finished | Jul 19 04:51:51 PM PDT 24 |
Peak memory | 203164 kb |
Host | smart-e968af4e-a67f-4ef6-99af-4db95be88003 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376823769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.3376823769 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3747600840 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 41497843 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:51:45 PM PDT 24 |
Finished | Jul 19 04:51:48 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-4a0b736a-c595-448a-8d21-82a293039897 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747600840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.3747600840 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1601673965 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 1187377118 ps |
CPU time | 4.26 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:51 PM PDT 24 |
Peak memory | 211464 kb |
Host | smart-5e59c304-1924-4800-b6fa-06b09c42a42a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601673965 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1601673965 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1577828236 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 49051345 ps |
CPU time | 0.67 seconds |
Started | Jul 19 04:51:45 PM PDT 24 |
Finished | Jul 19 04:51:48 PM PDT 24 |
Peak memory | 203032 kb |
Host | smart-91e96159-4deb-40f5-ada1-f5d85a926d10 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577828236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.1577828236 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3355784484 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 7334942661 ps |
CPU time | 52.24 seconds |
Started | Jul 19 04:51:30 PM PDT 24 |
Finished | Jul 19 04:52:25 PM PDT 24 |
Peak memory | 203592 kb |
Host | smart-2a6bc726-5576-4a41-97cb-1832c99a60de |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355784484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3355784484 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.266403138 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 41151847 ps |
CPU time | 0.79 seconds |
Started | Jul 19 04:51:45 PM PDT 24 |
Finished | Jul 19 04:51:48 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-de505771-bbea-4152-8947-043fec4502aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266403138 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.266403138 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2845538906 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 43900700 ps |
CPU time | 3.72 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:50 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-7ca12782-ac11-4a83-99a2-288cf42ccede |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845538906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.2845538906 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1957083196 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 899317154 ps |
CPU time | 2.15 seconds |
Started | Jul 19 04:51:43 PM PDT 24 |
Finished | Jul 19 04:51:47 PM PDT 24 |
Peak memory | 211392 kb |
Host | smart-9f51caa1-10ac-4f25-b4da-7ca78b82fe51 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957083196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.1957083196 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1023827188 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 171803499 ps |
CPU time | 0.76 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:47 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-c7a1d6e3-458c-4e4d-ae80-27909a8f498e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023827188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.1023827188 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3451885899 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 461574683 ps |
CPU time | 2.21 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:47 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-ffdb796e-6eba-4e38-ba08-dec90724f1ae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451885899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3451885899 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1600308027 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 62647247 ps |
CPU time | 0.69 seconds |
Started | Jul 19 04:51:47 PM PDT 24 |
Finished | Jul 19 04:51:50 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-b98d5728-8181-405f-86c7-98d3df689ba4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600308027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1600308027 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3179038610 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 709020673 ps |
CPU time | 3.66 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:49 PM PDT 24 |
Peak memory | 211208 kb |
Host | smart-94d2ded1-e7ae-4d26-a811-594acb1143fd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179038610 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3179038610 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2216812369 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 37233269 ps |
CPU time | 0.65 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:46 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-676a4559-e6c9-4ed5-9a2b-6db88aad9038 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216812369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.2216812369 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2340959282 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 15368891568 ps |
CPU time | 30.58 seconds |
Started | Jul 19 04:51:46 PM PDT 24 |
Finished | Jul 19 04:52:19 PM PDT 24 |
Peak memory | 203372 kb |
Host | smart-486dfe07-1dc2-405c-90eb-32de251fa90b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340959282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2340959282 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.523345228 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 52617327 ps |
CPU time | 0.73 seconds |
Started | Jul 19 04:51:48 PM PDT 24 |
Finished | Jul 19 04:51:51 PM PDT 24 |
Peak memory | 202988 kb |
Host | smart-7409553b-b4f4-4ffb-aed8-e44cbd8851b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523345228 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.523345228 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.878730412 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 126142497 ps |
CPU time | 2.31 seconds |
Started | Jul 19 04:51:46 PM PDT 24 |
Finished | Jul 19 04:51:51 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-f9d5e09a-06cd-4d80-a7f5-bb522728ca5a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878730412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.878730412 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2648181908 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1130324003 ps |
CPU time | 2.28 seconds |
Started | Jul 19 04:51:42 PM PDT 24 |
Finished | Jul 19 04:51:46 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-d03c99df-cec0-4e25-9809-88eb49a751ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648181908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.2648181908 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1220526672 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 15103408 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:51:45 PM PDT 24 |
Finished | Jul 19 04:51:48 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-8e860e90-889d-45cc-b486-ddc5554c2d6b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220526672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.1220526672 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4281983179 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 48668172 ps |
CPU time | 1.85 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:48 PM PDT 24 |
Peak memory | 203248 kb |
Host | smart-ca145d2d-7330-4590-a9ca-b7d9b0d9487b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281983179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.4281983179 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2416601468 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 18088014 ps |
CPU time | 0.7 seconds |
Started | Jul 19 04:51:45 PM PDT 24 |
Finished | Jul 19 04:51:48 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-e5e62768-75d1-46c7-bbaf-12dc0fa4f4b5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416601468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.2416601468 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2154104073 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 768379367 ps |
CPU time | 4.05 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:49 PM PDT 24 |
Peak memory | 211480 kb |
Host | smart-e5ffc098-f8e6-4c27-8e71-08657e7d568e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154104073 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2154104073 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1802337316 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 43420037 ps |
CPU time | 0.63 seconds |
Started | Jul 19 04:51:45 PM PDT 24 |
Finished | Jul 19 04:51:49 PM PDT 24 |
Peak memory | 203004 kb |
Host | smart-e6d43934-70fa-4a78-9530-30021b1e524f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802337316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.1802337316 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2488401054 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 14672976395 ps |
CPU time | 51.08 seconds |
Started | Jul 19 04:51:42 PM PDT 24 |
Finished | Jul 19 04:52:34 PM PDT 24 |
Peak memory | 203540 kb |
Host | smart-98754d17-5f56-40e2-93a4-870bf366f7f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488401054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2488401054 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2119529599 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 25768630 ps |
CPU time | 0.69 seconds |
Started | Jul 19 04:51:46 PM PDT 24 |
Finished | Jul 19 04:51:50 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-f6c49c12-849a-4a4a-b39f-575cb79976e8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119529599 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2119529599 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1453165283 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 96561913 ps |
CPU time | 2.2 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:48 PM PDT 24 |
Peak memory | 203344 kb |
Host | smart-fd9c939f-e0fa-4fcc-a62b-3ca7650d27d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453165283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.1453165283 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4236535519 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 671092416 ps |
CPU time | 2.26 seconds |
Started | Jul 19 04:51:45 PM PDT 24 |
Finished | Jul 19 04:51:50 PM PDT 24 |
Peak memory | 203268 kb |
Host | smart-1e318572-d599-43c7-86e0-2dbe20e6afbc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236535519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.4236535519 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2352676567 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 354690718 ps |
CPU time | 3.28 seconds |
Started | Jul 19 04:51:47 PM PDT 24 |
Finished | Jul 19 04:51:53 PM PDT 24 |
Peak memory | 211276 kb |
Host | smart-64d29e2c-b4f8-4806-a56e-91b85eaab0b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352676567 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2352676567 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3108133364 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 24108230 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:46 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-4010b3ed-0867-4cff-95b1-774c38c267ca |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108133364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.3108133364 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3770834757 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 29405146570 ps |
CPU time | 55.01 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:52:41 PM PDT 24 |
Peak memory | 203580 kb |
Host | smart-b451185c-a440-4a11-9665-a234296da720 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770834757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3770834757 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3981786499 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 24316023 ps |
CPU time | 0.7 seconds |
Started | Jul 19 04:51:46 PM PDT 24 |
Finished | Jul 19 04:51:49 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-93db09ea-a51b-4706-a56a-032e3d98f020 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981786499 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3981786499 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.180075149 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 66799644 ps |
CPU time | 2.5 seconds |
Started | Jul 19 04:51:45 PM PDT 24 |
Finished | Jul 19 04:51:50 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-28a78003-8454-4f4c-92a8-94b253abdd2d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180075149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.180075149 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.407330785 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 341575121 ps |
CPU time | 1.56 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:51:47 PM PDT 24 |
Peak memory | 203148 kb |
Host | smart-fd634152-51e4-4ce6-993b-cc6cf567fed0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407330785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sram_ctrl_tl_intg_err.407330785 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.301761928 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 375107479 ps |
CPU time | 3.46 seconds |
Started | Jul 19 04:51:52 PM PDT 24 |
Finished | Jul 19 04:51:55 PM PDT 24 |
Peak memory | 212220 kb |
Host | smart-eef163a9-cb47-4aec-95b0-2a48d8b62a12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301761928 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.301761928 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1876863892 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 13495641 ps |
CPU time | 0.66 seconds |
Started | Jul 19 04:51:53 PM PDT 24 |
Finished | Jul 19 04:51:55 PM PDT 24 |
Peak memory | 203000 kb |
Host | smart-2479883f-4cce-4127-ade1-f421644ee023 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876863892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.1876863892 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3468086639 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 7418526744 ps |
CPU time | 27.94 seconds |
Started | Jul 19 04:51:44 PM PDT 24 |
Finished | Jul 19 04:52:14 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-afda738a-1158-4162-a255-85bf9a5f1853 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468086639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3468086639 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2182659178 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 39356683 ps |
CPU time | 0.68 seconds |
Started | Jul 19 04:51:53 PM PDT 24 |
Finished | Jul 19 04:51:54 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-ce402ca1-a459-47e4-9cec-90ce24e87fa1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182659178 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.2182659178 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2174443498 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 42700770 ps |
CPU time | 2.03 seconds |
Started | Jul 19 04:51:53 PM PDT 24 |
Finished | Jul 19 04:51:56 PM PDT 24 |
Peak memory | 203196 kb |
Host | smart-6842a6a9-f13b-4f81-bce4-c5b61b303dce |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174443498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.2174443498 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1556153162 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 154819304 ps |
CPU time | 1.63 seconds |
Started | Jul 19 04:51:58 PM PDT 24 |
Finished | Jul 19 04:52:01 PM PDT 24 |
Peak memory | 211412 kb |
Host | smart-943caad5-a4f0-4021-bbf6-98a328429378 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556153162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1556153162 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4082844374 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 352238006 ps |
CPU time | 4.07 seconds |
Started | Jul 19 04:51:53 PM PDT 24 |
Finished | Jul 19 04:51:59 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-3cce08a2-ecb5-4819-93f6-75a7e295b4f7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082844374 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.4082844374 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1754492405 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 19950240 ps |
CPU time | 0.73 seconds |
Started | Jul 19 04:51:54 PM PDT 24 |
Finished | Jul 19 04:51:57 PM PDT 24 |
Peak memory | 203052 kb |
Host | smart-9664d2dc-fa80-4b28-8566-15c3fc1baae6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754492405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.1754492405 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3246572361 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 3710621748 ps |
CPU time | 28.65 seconds |
Started | Jul 19 04:51:53 PM PDT 24 |
Finished | Jul 19 04:52:23 PM PDT 24 |
Peak memory | 203352 kb |
Host | smart-eebfb269-7cf9-4c4d-979d-5f20ff900044 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246572361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3246572361 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3108448351 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 83059965 ps |
CPU time | 0.82 seconds |
Started | Jul 19 04:51:54 PM PDT 24 |
Finished | Jul 19 04:51:57 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-78ad5daf-7ff6-4116-a523-706ce06af357 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108448351 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3108448351 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2915947428 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 37097125 ps |
CPU time | 2.03 seconds |
Started | Jul 19 04:51:55 PM PDT 24 |
Finished | Jul 19 04:51:59 PM PDT 24 |
Peak memory | 211340 kb |
Host | smart-d50c81c3-608a-427f-b7d3-24d370c17f87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915947428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2915947428 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2584857596 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 278133365 ps |
CPU time | 2.58 seconds |
Started | Jul 19 04:51:57 PM PDT 24 |
Finished | Jul 19 04:52:02 PM PDT 24 |
Peak memory | 211396 kb |
Host | smart-dfe230e5-a327-43a6-a065-4defe5bff7a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584857596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.2584857596 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1677867423 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 363710503 ps |
CPU time | 3.56 seconds |
Started | Jul 19 04:51:55 PM PDT 24 |
Finished | Jul 19 04:52:00 PM PDT 24 |
Peak memory | 212216 kb |
Host | smart-0ebf5fd3-3bf2-4135-8133-2eadc3731cea |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677867423 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1677867423 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1582119243 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 59761875 ps |
CPU time | 0.64 seconds |
Started | Jul 19 04:51:58 PM PDT 24 |
Finished | Jul 19 04:52:00 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-7a3047dc-4ec6-40a7-9b85-681580ceae40 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582119243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.1582119243 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.442352635 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 3873690244 ps |
CPU time | 28.61 seconds |
Started | Jul 19 04:51:52 PM PDT 24 |
Finished | Jul 19 04:52:21 PM PDT 24 |
Peak memory | 203308 kb |
Host | smart-19b61211-a7e3-4daf-82d6-4c3a1ed8540d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442352635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.442352635 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3210593411 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 68227128 ps |
CPU time | 0.68 seconds |
Started | Jul 19 04:51:56 PM PDT 24 |
Finished | Jul 19 04:51:58 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-3b61e0ba-5d2a-4111-a052-d3f4bbcc440e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210593411 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3210593411 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1157953119 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 38291844 ps |
CPU time | 4.04 seconds |
Started | Jul 19 04:51:54 PM PDT 24 |
Finished | Jul 19 04:51:59 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-57fdeea3-9bdc-4e47-b077-171b62278f6e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157953119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.1157953119 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.900099245 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 102034998 ps |
CPU time | 1.7 seconds |
Started | Jul 19 04:51:56 PM PDT 24 |
Finished | Jul 19 04:52:00 PM PDT 24 |
Peak memory | 211452 kb |
Host | smart-1434141f-9cae-45d6-8eba-11ca905a836b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900099245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.sram_ctrl_tl_intg_err.900099245 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1119628230 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 1577976054 ps |
CPU time | 3.61 seconds |
Started | Jul 19 04:52:03 PM PDT 24 |
Finished | Jul 19 04:52:08 PM PDT 24 |
Peak memory | 211240 kb |
Host | smart-873cd75b-7eb9-475f-bbe1-eabdf0143706 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119628230 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1119628230 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1275105383 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 12967157 ps |
CPU time | 0.67 seconds |
Started | Jul 19 04:51:56 PM PDT 24 |
Finished | Jul 19 04:51:59 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-257a1aed-a43c-4c0c-b7ff-379f00f3908f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275105383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.1275105383 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3691721753 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 3868432181 ps |
CPU time | 27.56 seconds |
Started | Jul 19 04:51:53 PM PDT 24 |
Finished | Jul 19 04:52:22 PM PDT 24 |
Peak memory | 203548 kb |
Host | smart-2d06944a-06b9-4ab6-ac1b-38267c8d0b68 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691721753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3691721753 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1059580363 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 73149216 ps |
CPU time | 0.81 seconds |
Started | Jul 19 04:52:01 PM PDT 24 |
Finished | Jul 19 04:52:03 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-304f340b-33d9-4237-b41b-36c07db040f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059580363 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1059580363 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1019115201 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 476077860 ps |
CPU time | 2.49 seconds |
Started | Jul 19 04:51:58 PM PDT 24 |
Finished | Jul 19 04:52:02 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-25e9c892-0a9d-411f-a1fe-ce148579e1f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019115201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.1019115201 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.74446214 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 556988396 ps |
CPU time | 2.11 seconds |
Started | Jul 19 04:51:54 PM PDT 24 |
Finished | Jul 19 04:51:58 PM PDT 24 |
Peak memory | 211404 kb |
Host | smart-cc1de93a-8f0e-4571-9f9e-942601796dd4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74446214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 9.sram_ctrl_tl_intg_err.74446214 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1141380948 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 34538776721 ps |
CPU time | 642.46 seconds |
Started | Jul 19 06:03:44 PM PDT 24 |
Finished | Jul 19 06:14:27 PM PDT 24 |
Peak memory | 379516 kb |
Host | smart-7da84fb8-6481-4ad1-a6b5-6a514adfd5cb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141380948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.1141380948 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.613170612 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 138078502625 ps |
CPU time | 2598.38 seconds |
Started | Jul 19 06:03:44 PM PDT 24 |
Finished | Jul 19 06:47:04 PM PDT 24 |
Peak memory | 203664 kb |
Host | smart-b8786a1b-7a23-4caf-8c12-fe97012e626c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613170612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.613170612 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.3527104551 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 1517535909 ps |
CPU time | 34.98 seconds |
Started | Jul 19 06:03:54 PM PDT 24 |
Finished | Jul 19 06:04:29 PM PDT 24 |
Peak memory | 277416 kb |
Host | smart-64c8b59a-86a8-4fce-bd5b-242cefdfaf1b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527104551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.3527104551 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.677083311 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 23925827692 ps |
CPU time | 81.42 seconds |
Started | Jul 19 06:03:43 PM PDT 24 |
Finished | Jul 19 06:05:05 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-cce92606-8115-4a9f-99e3-6a050d108b27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677083311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esca lation.677083311 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.582423714 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 716301787 ps |
CPU time | 6.14 seconds |
Started | Jul 19 06:03:45 PM PDT 24 |
Finished | Jul 19 06:03:51 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-f5d2da15-ce2a-46fd-b164-1f5bc57af6e1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582423714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.sram_ctrl_max_throughput.582423714 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1808132507 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 1582711218 ps |
CPU time | 129.1 seconds |
Started | Jul 19 06:03:56 PM PDT 24 |
Finished | Jul 19 06:06:06 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-6f134b56-9c84-4e29-8901-d04c3059d7af |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808132507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.1808132507 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.485199651 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 5365509338 ps |
CPU time | 304.2 seconds |
Started | Jul 19 06:03:54 PM PDT 24 |
Finished | Jul 19 06:08:59 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-5bb9b23e-9f72-42f1-97fb-de9237be3cff |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485199651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ mem_walk.485199651 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.3037087071 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 17769563073 ps |
CPU time | 1285.82 seconds |
Started | Jul 19 06:03:44 PM PDT 24 |
Finished | Jul 19 06:25:10 PM PDT 24 |
Peak memory | 380812 kb |
Host | smart-235c8f78-c523-40d5-8ec0-ebeeca548e36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037087071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.3037087071 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.1105058040 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 667451375 ps |
CPU time | 24.73 seconds |
Started | Jul 19 06:03:44 PM PDT 24 |
Finished | Jul 19 06:04:09 PM PDT 24 |
Peak memory | 265184 kb |
Host | smart-6ce55b68-6109-42e2-9bb7-e4841f44e1f4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105058040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.1105058040 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1334119018 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 6383313450 ps |
CPU time | 399.93 seconds |
Started | Jul 19 06:03:45 PM PDT 24 |
Finished | Jul 19 06:10:25 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-f0f0f2c2-6f3f-48ce-bfe6-27e37d6555ef |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334119018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1334119018 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.1222908625 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 683722541 ps |
CPU time | 3.38 seconds |
Started | Jul 19 06:03:54 PM PDT 24 |
Finished | Jul 19 06:03:58 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-9e834bb4-505e-4a30-bd19-67e124ed168c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222908625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1222908625 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.2850085029 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 10273271329 ps |
CPU time | 719.38 seconds |
Started | Jul 19 06:03:52 PM PDT 24 |
Finished | Jul 19 06:15:52 PM PDT 24 |
Peak memory | 376712 kb |
Host | smart-c1f08d12-3590-432f-9ef0-c6005c10caae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850085029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2850085029 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.2263820046 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 2647579952 ps |
CPU time | 5.81 seconds |
Started | Jul 19 06:03:42 PM PDT 24 |
Finished | Jul 19 06:03:48 PM PDT 24 |
Peak memory | 209064 kb |
Host | smart-96adf9f6-0f9d-469e-bfdc-2f712b373ced |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263820046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2263820046 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.3853212459 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 61600023181 ps |
CPU time | 3899.4 seconds |
Started | Jul 19 06:03:55 PM PDT 24 |
Finished | Jul 19 07:08:55 PM PDT 24 |
Peak memory | 378820 kb |
Host | smart-a8e01ead-d322-4cd8-bde2-c726057142c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853212459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.sram_ctrl_stress_all.3853212459 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1694650972 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 4637636462 ps |
CPU time | 157.98 seconds |
Started | Jul 19 06:03:53 PM PDT 24 |
Finished | Jul 19 06:06:31 PM PDT 24 |
Peak memory | 362312 kb |
Host | smart-c5f3c9b5-5c8c-445f-8e29-7b5ec2eb15a4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1694650972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1694650972 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2489759590 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 5593426917 ps |
CPU time | 351.87 seconds |
Started | Jul 19 06:03:42 PM PDT 24 |
Finished | Jul 19 06:09:35 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-82e7b222-cdc8-4e61-9447-58b5bc3b36a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489759590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.2489759590 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1513725593 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 3081056973 ps |
CPU time | 23.03 seconds |
Started | Jul 19 06:03:45 PM PDT 24 |
Finished | Jul 19 06:04:09 PM PDT 24 |
Peak memory | 268376 kb |
Host | smart-989f5941-af73-4740-bba8-03088f1c1de0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513725593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1513725593 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.3853618337 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 90238281453 ps |
CPU time | 1233.56 seconds |
Started | Jul 19 06:04:00 PM PDT 24 |
Finished | Jul 19 06:24:34 PM PDT 24 |
Peak memory | 375480 kb |
Host | smart-19f151c7-290b-4a00-b218-5aa975f4ebfd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853618337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.3853618337 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.2174270953 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 23019950 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:04:05 PM PDT 24 |
Finished | Jul 19 06:04:06 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-aec19911-d573-4af2-acea-81d90793308f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174270953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2174270953 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.751932894 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 85552238454 ps |
CPU time | 1372.58 seconds |
Started | Jul 19 06:03:55 PM PDT 24 |
Finished | Jul 19 06:26:49 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-2b1988df-5c4d-4acf-9829-88fb044e7e86 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751932894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.751932894 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.2589931166 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 7733740656 ps |
CPU time | 236.34 seconds |
Started | Jul 19 06:04:03 PM PDT 24 |
Finished | Jul 19 06:08:00 PM PDT 24 |
Peak memory | 318320 kb |
Host | smart-76b0f861-4b72-4ff2-8802-04659648668b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589931166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.2589931166 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.2347389880 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 6317598199 ps |
CPU time | 19.38 seconds |
Started | Jul 19 06:04:04 PM PDT 24 |
Finished | Jul 19 06:04:24 PM PDT 24 |
Peak memory | 215228 kb |
Host | smart-0b806e7e-c00b-4b01-884f-7f226635ea6f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347389880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.2347389880 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.1306364876 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 703140795 ps |
CPU time | 6.29 seconds |
Started | Jul 19 06:03:53 PM PDT 24 |
Finished | Jul 19 06:04:00 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-d946abe4-e27d-4b37-98e0-a9b8ae9a674f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306364876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.1306364876 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2861651018 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 18257723754 ps |
CPU time | 145.66 seconds |
Started | Jul 19 06:04:00 PM PDT 24 |
Finished | Jul 19 06:06:26 PM PDT 24 |
Peak memory | 219280 kb |
Host | smart-b2d5c657-7011-42b0-8499-20c0cd79bc5f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861651018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.2861651018 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.3132801684 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 86200085184 ps |
CPU time | 352.15 seconds |
Started | Jul 19 06:04:03 PM PDT 24 |
Finished | Jul 19 06:09:56 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-01c2a410-3e8e-4da8-a086-7e5a5b065986 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132801684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.3132801684 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.1978487138 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 27649261838 ps |
CPU time | 1716.58 seconds |
Started | Jul 19 06:03:55 PM PDT 24 |
Finished | Jul 19 06:32:32 PM PDT 24 |
Peak memory | 380864 kb |
Host | smart-5b665b20-c31d-4516-a8c7-d957512dce84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978487138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.1978487138 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.3650517549 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 16613425379 ps |
CPU time | 59.33 seconds |
Started | Jul 19 06:03:53 PM PDT 24 |
Finished | Jul 19 06:04:53 PM PDT 24 |
Peak memory | 289644 kb |
Host | smart-d454ac66-acc7-418a-8bed-93eda9777ac5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650517549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.3650517549 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3524118360 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 9638506575 ps |
CPU time | 213.56 seconds |
Started | Jul 19 06:03:53 PM PDT 24 |
Finished | Jul 19 06:07:27 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-da213300-edbf-4703-8dbf-f2105d1726bb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524118360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.3524118360 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.1137443187 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 1351756021 ps |
CPU time | 3.69 seconds |
Started | Jul 19 06:04:00 PM PDT 24 |
Finished | Jul 19 06:04:05 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-8d50b773-240b-44b7-8544-88ca0c7de1db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137443187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1137443187 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.2528075166 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 14837415558 ps |
CPU time | 1120.96 seconds |
Started | Jul 19 06:04:02 PM PDT 24 |
Finished | Jul 19 06:22:44 PM PDT 24 |
Peak memory | 378800 kb |
Host | smart-e0711ad8-ed61-4593-9632-0699ee12f8f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528075166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2528075166 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.2437891358 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 147536490 ps |
CPU time | 2.04 seconds |
Started | Jul 19 06:04:05 PM PDT 24 |
Finished | Jul 19 06:04:07 PM PDT 24 |
Peak memory | 222088 kb |
Host | smart-9db0ecae-cd9a-4051-9458-70794f9e4e6b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437891358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2437891358 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.1523329755 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 1543691862 ps |
CPU time | 13.61 seconds |
Started | Jul 19 06:03:55 PM PDT 24 |
Finished | Jul 19 06:04:10 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-6f9f203d-12e5-425a-8454-ce0e96907bd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523329755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1523329755 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.1243020775 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 161257934484 ps |
CPU time | 1884.78 seconds |
Started | Jul 19 06:04:00 PM PDT 24 |
Finished | Jul 19 06:35:26 PM PDT 24 |
Peak memory | 379776 kb |
Host | smart-6a8d1b00-be6b-4018-b05b-6a11451ae747 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243020775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.1243020775 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.134491681 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 9389857827 ps |
CPU time | 66.46 seconds |
Started | Jul 19 06:04:00 PM PDT 24 |
Finished | Jul 19 06:05:07 PM PDT 24 |
Peak memory | 211360 kb |
Host | smart-a3f563b5-b819-4bdb-a6a2-1ae615ceadac |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=134491681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.134491681 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1205373820 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 3071520731 ps |
CPU time | 207.09 seconds |
Started | Jul 19 06:03:56 PM PDT 24 |
Finished | Jul 19 06:07:25 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-4ef6e153-3c9a-44af-9f93-64aa1e6d6d67 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205373820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1205373820 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3041285502 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 10716163845 ps |
CPU time | 70.79 seconds |
Started | Jul 19 06:04:02 PM PDT 24 |
Finished | Jul 19 06:05:14 PM PDT 24 |
Peak memory | 327684 kb |
Host | smart-fee3b1a5-d991-455e-871c-405f02892078 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041285502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3041285502 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2000636161 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 63895633120 ps |
CPU time | 1042.44 seconds |
Started | Jul 19 06:05:24 PM PDT 24 |
Finished | Jul 19 06:22:48 PM PDT 24 |
Peak memory | 373740 kb |
Host | smart-e1eba3f1-c3e3-43cc-abc4-bdd561476c96 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000636161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.2000636161 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.3709546657 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 26568436 ps |
CPU time | 0.69 seconds |
Started | Jul 19 06:05:24 PM PDT 24 |
Finished | Jul 19 06:05:26 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-0f49a5d2-8097-4127-8a60-e2bc9a6da3cc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709546657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3709546657 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.3251822244 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 355125725683 ps |
CPU time | 1500.49 seconds |
Started | Jul 19 06:05:18 PM PDT 24 |
Finished | Jul 19 06:30:22 PM PDT 24 |
Peak memory | 203488 kb |
Host | smart-96ebb64e-464f-4f55-9003-79a43905da84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251822244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .3251822244 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.2922124386 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 19120301663 ps |
CPU time | 831.1 seconds |
Started | Jul 19 06:05:25 PM PDT 24 |
Finished | Jul 19 06:19:18 PM PDT 24 |
Peak memory | 374632 kb |
Host | smart-5bae8f93-97a7-4291-b6d6-b16886bc18a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922124386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.2922124386 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.1875544556 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 9043684113 ps |
CPU time | 53.97 seconds |
Started | Jul 19 06:05:24 PM PDT 24 |
Finished | Jul 19 06:06:20 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-02b10bda-25d5-4dd9-a6c0-fe8683a0787c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875544556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.1875544556 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.802608930 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 1499687757 ps |
CPU time | 47.51 seconds |
Started | Jul 19 06:05:19 PM PDT 24 |
Finished | Jul 19 06:06:09 PM PDT 24 |
Peak memory | 309748 kb |
Host | smart-bb0fb27f-e1b1-42d3-88dd-4c385ac1ad36 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802608930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.sram_ctrl_max_throughput.802608930 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3984646751 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 20879241252 ps |
CPU time | 177.48 seconds |
Started | Jul 19 06:05:24 PM PDT 24 |
Finished | Jul 19 06:08:23 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-bce2e08f-abd7-48ac-9a07-4a2e9024dbb9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984646751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.3984646751 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.3184093568 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 55312782550 ps |
CPU time | 328.46 seconds |
Started | Jul 19 06:05:25 PM PDT 24 |
Finished | Jul 19 06:10:55 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-696a905d-2584-4257-9201-3d12652b4a87 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184093568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.3184093568 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.745752562 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 30761960526 ps |
CPU time | 534.19 seconds |
Started | Jul 19 06:05:15 PM PDT 24 |
Finished | Jul 19 06:14:14 PM PDT 24 |
Peak memory | 376716 kb |
Host | smart-0c61ffbd-68fe-4d29-81e6-c311b2af7d59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745752562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip le_keys.745752562 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.3825771074 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 3701714740 ps |
CPU time | 14.19 seconds |
Started | Jul 19 06:05:16 PM PDT 24 |
Finished | Jul 19 06:05:34 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-5ebdde5b-3ff0-4328-82f1-a739857a5918 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825771074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3825771074 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.2525583771 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 359406793 ps |
CPU time | 3.38 seconds |
Started | Jul 19 06:05:42 PM PDT 24 |
Finished | Jul 19 06:05:49 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-c2dbe5e6-0221-4e18-ad07-3138513c68f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525583771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2525583771 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.1304573077 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 3807574593 ps |
CPU time | 306.07 seconds |
Started | Jul 19 06:05:23 PM PDT 24 |
Finished | Jul 19 06:10:31 PM PDT 24 |
Peak memory | 372644 kb |
Host | smart-9ea5732e-4d00-4d07-b827-ec50461c6af0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304573077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1304573077 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.3461018703 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 830208897 ps |
CPU time | 4.65 seconds |
Started | Jul 19 06:05:15 PM PDT 24 |
Finished | Jul 19 06:05:24 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-b6fcd0c8-8d59-4292-a0d9-076a89d3e3fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461018703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3461018703 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3146306376 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 1679413341 ps |
CPU time | 13.37 seconds |
Started | Jul 19 06:05:24 PM PDT 24 |
Finished | Jul 19 06:05:38 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-e062deaa-f454-426d-b272-7f4918d75dd1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3146306376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3146306376 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3089091145 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 3754509651 ps |
CPU time | 237.1 seconds |
Started | Jul 19 06:05:15 PM PDT 24 |
Finished | Jul 19 06:09:16 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-de95c3f4-bc86-4d1e-b10f-0752879140be |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089091145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.3089091145 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2614107097 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 13359156989 ps |
CPU time | 10.94 seconds |
Started | Jul 19 06:05:16 PM PDT 24 |
Finished | Jul 19 06:05:30 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-313a4440-93db-400f-9e1d-bef01669dc7c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614107097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2614107097 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.392496808 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 12854288865 ps |
CPU time | 1372.42 seconds |
Started | Jul 19 06:05:32 PM PDT 24 |
Finished | Jul 19 06:28:25 PM PDT 24 |
Peak memory | 378800 kb |
Host | smart-e0c587cd-5e1c-431c-9146-e8e3fc405510 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392496808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 11.sram_ctrl_access_during_key_req.392496808 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.1606682199 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 32923475 ps |
CPU time | 0.63 seconds |
Started | Jul 19 06:05:45 PM PDT 24 |
Finished | Jul 19 06:05:49 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-d4813195-9593-4d01-8c8a-b1aba9efb183 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606682199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1606682199 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.1187101242 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 29321180961 ps |
CPU time | 639.85 seconds |
Started | Jul 19 06:05:30 PM PDT 24 |
Finished | Jul 19 06:16:11 PM PDT 24 |
Peak memory | 203672 kb |
Host | smart-f4f4def5-cdc3-4a13-ab2a-21f505eeb987 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187101242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .1187101242 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.2075022656 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 30197414028 ps |
CPU time | 644.26 seconds |
Started | Jul 19 06:05:33 PM PDT 24 |
Finished | Jul 19 06:16:18 PM PDT 24 |
Peak memory | 373628 kb |
Host | smart-afe78bd3-3f11-45ce-aff7-9f154150118e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075022656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.2075022656 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.3349739272 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 42222036506 ps |
CPU time | 73.77 seconds |
Started | Jul 19 06:05:35 PM PDT 24 |
Finished | Jul 19 06:06:50 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-1d96c8a6-28ee-4a76-b451-e4f478dbe9a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349739272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.3349739272 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.3106909709 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 1190108618 ps |
CPU time | 75.01 seconds |
Started | Jul 19 06:05:35 PM PDT 24 |
Finished | Jul 19 06:06:51 PM PDT 24 |
Peak memory | 321448 kb |
Host | smart-cd53e65f-55e6-4fc3-9817-5728050efc8c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106909709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.3106909709 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2585997042 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 6046714107 ps |
CPU time | 175.57 seconds |
Started | Jul 19 06:05:39 PM PDT 24 |
Finished | Jul 19 06:08:37 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-de8cc011-0393-4ad0-99ba-38066608a2cf |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585997042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.2585997042 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.2098630732 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 10721747628 ps |
CPU time | 299.54 seconds |
Started | Jul 19 06:05:39 PM PDT 24 |
Finished | Jul 19 06:10:40 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-a3794ceb-d160-4a80-bc95-3e7640b1832d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098630732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.2098630732 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.2413794377 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 7137130322 ps |
CPU time | 809.92 seconds |
Started | Jul 19 06:05:30 PM PDT 24 |
Finished | Jul 19 06:19:01 PM PDT 24 |
Peak memory | 378752 kb |
Host | smart-92970c25-c184-43e9-8cff-6c18a6342910 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413794377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.2413794377 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.2856467666 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 588482156 ps |
CPU time | 19.31 seconds |
Started | Jul 19 06:05:31 PM PDT 24 |
Finished | Jul 19 06:05:51 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-bb62490b-c182-47a0-b803-c8d932ef1444 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856467666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.2856467666 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2494390804 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 27288706450 ps |
CPU time | 448.87 seconds |
Started | Jul 19 06:05:31 PM PDT 24 |
Finished | Jul 19 06:13:00 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-5e0a113c-436d-4a5a-8a4c-14e48e630438 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494390804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.2494390804 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.1807131485 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 676836404 ps |
CPU time | 3.19 seconds |
Started | Jul 19 06:05:32 PM PDT 24 |
Finished | Jul 19 06:05:36 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-04fcd461-afc7-4a5e-9fe2-532ac5f14c06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807131485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1807131485 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.2823248468 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 20767412921 ps |
CPU time | 1569.45 seconds |
Started | Jul 19 06:05:32 PM PDT 24 |
Finished | Jul 19 06:31:43 PM PDT 24 |
Peak memory | 382832 kb |
Host | smart-9f88cd56-1c2e-4f80-90e3-3be217f0dc2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823248468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2823248468 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.2458171673 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 1094038714 ps |
CPU time | 48.88 seconds |
Started | Jul 19 06:05:35 PM PDT 24 |
Finished | Jul 19 06:06:25 PM PDT 24 |
Peak memory | 295860 kb |
Host | smart-2e0f00a2-8be3-4bb8-be64-f67919cc5e3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458171673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2458171673 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3969269385 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 1986435961 ps |
CPU time | 108.47 seconds |
Started | Jul 19 06:05:41 PM PDT 24 |
Finished | Jul 19 06:07:33 PM PDT 24 |
Peak memory | 214996 kb |
Host | smart-4e91c6d9-468b-40d1-b32a-e7c41d8a7532 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3969269385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3969269385 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.4036670558 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 3992065684 ps |
CPU time | 265.67 seconds |
Started | Jul 19 06:05:32 PM PDT 24 |
Finished | Jul 19 06:09:59 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-21a6acf7-4485-4b98-b626-c815bf3b8835 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036670558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.4036670558 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2797218637 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 2702697803 ps |
CPU time | 6.33 seconds |
Started | Jul 19 06:05:31 PM PDT 24 |
Finished | Jul 19 06:05:38 PM PDT 24 |
Peak memory | 211232 kb |
Host | smart-56b34311-0759-4df3-9ad7-e222c59e7f73 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797218637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.2797218637 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3235071797 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 8668679864 ps |
CPU time | 446.95 seconds |
Started | Jul 19 06:05:47 PM PDT 24 |
Finished | Jul 19 06:13:16 PM PDT 24 |
Peak memory | 360008 kb |
Host | smart-e9b394e8-f71b-43cf-9dc7-7f1c0d3d6698 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235071797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.3235071797 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.235295229 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 29831639 ps |
CPU time | 0.7 seconds |
Started | Jul 19 06:05:54 PM PDT 24 |
Finished | Jul 19 06:05:59 PM PDT 24 |
Peak memory | 202468 kb |
Host | smart-05d79813-fcc7-4852-9a9e-0f795c69aad5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235295229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.235295229 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.475836067 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 113841792507 ps |
CPU time | 2331.32 seconds |
Started | Jul 19 06:05:44 PM PDT 24 |
Finished | Jul 19 06:44:39 PM PDT 24 |
Peak memory | 203720 kb |
Host | smart-194f706c-4acf-45e0-bbeb-23ba0e1ad535 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475836067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection. 475836067 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.882383050 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 26884516451 ps |
CPU time | 352.35 seconds |
Started | Jul 19 06:05:54 PM PDT 24 |
Finished | Jul 19 06:11:50 PM PDT 24 |
Peak memory | 369540 kb |
Host | smart-50a9db9e-5d5f-4995-ae81-5b179aa5fe88 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882383050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executabl e.882383050 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.4174591187 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 2548366732 ps |
CPU time | 9.31 seconds |
Started | Jul 19 06:05:40 PM PDT 24 |
Finished | Jul 19 06:05:51 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-8ff7aaa7-6ca5-4eb2-b8dc-01cc5732e0b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174591187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.4174591187 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.3885174220 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 1468662515 ps |
CPU time | 7.66 seconds |
Started | Jul 19 06:05:44 PM PDT 24 |
Finished | Jul 19 06:05:55 PM PDT 24 |
Peak memory | 219340 kb |
Host | smart-3339f128-45dd-4434-8f0b-320c5669a23f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885174220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.3885174220 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.834885252 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 2501183959 ps |
CPU time | 141.3 seconds |
Started | Jul 19 06:05:46 PM PDT 24 |
Finished | Jul 19 06:08:10 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-c8c3dbad-2648-42de-a69d-f5fead6fbe75 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834885252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sram_ctrl_mem_partial_access.834885252 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.1367566099 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 82638246398 ps |
CPU time | 376.59 seconds |
Started | Jul 19 06:05:47 PM PDT 24 |
Finished | Jul 19 06:12:06 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-f4e9bf1f-fbf0-4807-9eca-5783858c9164 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367566099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.1367566099 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.3266093558 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 91732203835 ps |
CPU time | 1407.56 seconds |
Started | Jul 19 06:05:40 PM PDT 24 |
Finished | Jul 19 06:29:10 PM PDT 24 |
Peak memory | 375708 kb |
Host | smart-cf81e3bb-768f-40a2-9133-acd576d2845c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266093558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.3266093558 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.491575350 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 883863329 ps |
CPU time | 18.91 seconds |
Started | Jul 19 06:05:41 PM PDT 24 |
Finished | Jul 19 06:06:03 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-346d21b5-0db0-4a00-b786-90e268d73a60 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491575350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.s ram_ctrl_partial_access.491575350 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4278677505 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 16880453701 ps |
CPU time | 523.06 seconds |
Started | Jul 19 06:05:38 PM PDT 24 |
Finished | Jul 19 06:14:23 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-f8f60108-9cf6-4577-9ef6-f810325ea7f0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278677505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.4278677505 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.1794318948 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1606812215 ps |
CPU time | 3.26 seconds |
Started | Jul 19 06:05:48 PM PDT 24 |
Finished | Jul 19 06:05:53 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-02ddde9d-ede6-4d2b-a5d1-6750bf7cf417 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794318948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1794318948 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.2355862551 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 4256260237 ps |
CPU time | 86.75 seconds |
Started | Jul 19 06:05:48 PM PDT 24 |
Finished | Jul 19 06:07:17 PM PDT 24 |
Peak memory | 230968 kb |
Host | smart-b4e4e783-466e-43e9-a5a6-f9faba46c248 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355862551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2355862551 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.2950395257 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 1007635484 ps |
CPU time | 11 seconds |
Started | Jul 19 06:05:45 PM PDT 24 |
Finished | Jul 19 06:05:59 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-16bebe0f-9d59-4012-ace3-151a7fe58981 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950395257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2950395257 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.448090479 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 296170447710 ps |
CPU time | 6855.17 seconds |
Started | Jul 19 06:05:54 PM PDT 24 |
Finished | Jul 19 08:00:15 PM PDT 24 |
Peak memory | 382404 kb |
Host | smart-c0d9b023-e77b-4cbc-95f2-43e5e4a568ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448090479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_stress_all.448090479 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2782736892 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 42890939134 ps |
CPU time | 343.61 seconds |
Started | Jul 19 06:05:43 PM PDT 24 |
Finished | Jul 19 06:11:30 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-0569d340-f5e4-4f84-8b9e-17afac3fe351 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782736892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.2782736892 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.972892227 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 2744340735 ps |
CPU time | 11.18 seconds |
Started | Jul 19 06:05:38 PM PDT 24 |
Finished | Jul 19 06:05:50 PM PDT 24 |
Peak memory | 235648 kb |
Host | smart-74e20e92-11b6-4803-828d-85218b97ad35 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972892227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.972892227 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1727459000 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 18428444259 ps |
CPU time | 845.6 seconds |
Started | Jul 19 06:05:58 PM PDT 24 |
Finished | Jul 19 06:20:07 PM PDT 24 |
Peak memory | 369616 kb |
Host | smart-a06a175e-d7ba-424d-9f81-31afdf7bd33f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727459000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.1727459000 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.2656575081 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 24377199 ps |
CPU time | 0.7 seconds |
Started | Jul 19 06:05:58 PM PDT 24 |
Finished | Jul 19 06:06:02 PM PDT 24 |
Peak memory | 202508 kb |
Host | smart-7592a762-b7ef-4c59-9e1c-a37341a3af26 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656575081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2656575081 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.3345244947 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 105797007636 ps |
CPU time | 2539.41 seconds |
Started | Jul 19 06:05:46 PM PDT 24 |
Finished | Jul 19 06:48:09 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-79aeac8c-9e26-490c-be0c-dd6da936ebf7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345244947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .3345244947 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.1418857320 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 34014425073 ps |
CPU time | 820.19 seconds |
Started | Jul 19 06:05:58 PM PDT 24 |
Finished | Jul 19 06:19:41 PM PDT 24 |
Peak memory | 359352 kb |
Host | smart-d3717be7-ddc3-41ca-aea5-67bbe8ea9510 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418857320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.1418857320 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.1720396032 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 14492926223 ps |
CPU time | 59.94 seconds |
Started | Jul 19 06:05:58 PM PDT 24 |
Finished | Jul 19 06:07:01 PM PDT 24 |
Peak memory | 303092 kb |
Host | smart-fbdb3dab-53d1-4b1b-957a-b650106f9db1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720396032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.1720396032 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2036333256 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 7227057747 ps |
CPU time | 128.61 seconds |
Started | Jul 19 06:06:00 PM PDT 24 |
Finished | Jul 19 06:08:11 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-6bdfe00e-24b4-4483-921c-a0498ad83614 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036333256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.2036333256 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.2565644749 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 4116962503 ps |
CPU time | 123.96 seconds |
Started | Jul 19 06:06:00 PM PDT 24 |
Finished | Jul 19 06:08:06 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-3e9b3812-989e-4265-b486-c93b002dfac6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565644749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.2565644749 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.1463027514 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 127196686171 ps |
CPU time | 1930.09 seconds |
Started | Jul 19 06:05:46 PM PDT 24 |
Finished | Jul 19 06:37:59 PM PDT 24 |
Peak memory | 378736 kb |
Host | smart-b137ed4f-050c-4806-8e05-36d81c5a1cd8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463027514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.1463027514 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.3034398370 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 907602010 ps |
CPU time | 18.33 seconds |
Started | Jul 19 06:05:46 PM PDT 24 |
Finished | Jul 19 06:06:07 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-3e2af3e3-56b3-44c1-af83-e55f93f2b56a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034398370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.3034398370 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3314940450 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 3844248566 ps |
CPU time | 212.94 seconds |
Started | Jul 19 06:05:58 PM PDT 24 |
Finished | Jul 19 06:09:34 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-f223adc9-05d2-46e1-9cc3-851e2ce40041 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314940450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.3314940450 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.642794387 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 673801584 ps |
CPU time | 3.29 seconds |
Started | Jul 19 06:06:00 PM PDT 24 |
Finished | Jul 19 06:06:06 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-78fb2c53-619f-4476-9d89-8333f510d899 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642794387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.642794387 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.3395971049 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 14980291963 ps |
CPU time | 905.41 seconds |
Started | Jul 19 06:05:58 PM PDT 24 |
Finished | Jul 19 06:21:07 PM PDT 24 |
Peak memory | 374704 kb |
Host | smart-cc9ddfe3-9e1e-4127-b36b-8e7aac19708e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395971049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3395971049 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.3841936944 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 3026511681 ps |
CPU time | 15.14 seconds |
Started | Jul 19 06:05:46 PM PDT 24 |
Finished | Jul 19 06:06:04 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-1bd08c8a-0525-4f7a-af59-3a3dd6f63b85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841936944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3841936944 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.963115198 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 227847328960 ps |
CPU time | 6230.29 seconds |
Started | Jul 19 06:06:00 PM PDT 24 |
Finished | Jul 19 07:49:53 PM PDT 24 |
Peak memory | 378816 kb |
Host | smart-eb1b69dd-4745-463d-a2fa-b8f8d3e34ceb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963115198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_stress_all.963115198 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3650682462 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 645808260 ps |
CPU time | 18.74 seconds |
Started | Jul 19 06:05:58 PM PDT 24 |
Finished | Jul 19 06:06:20 PM PDT 24 |
Peak memory | 217792 kb |
Host | smart-dec1d3f3-4363-4ddf-9d3b-dc5ae3cf9dc1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3650682462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3650682462 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.4277599752 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 5173294354 ps |
CPU time | 340.94 seconds |
Started | Jul 19 06:05:46 PM PDT 24 |
Finished | Jul 19 06:11:30 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-76a814b4-8af2-494c-89ad-9345cc7ba251 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277599752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.4277599752 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1157032905 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 732628161 ps |
CPU time | 13.46 seconds |
Started | Jul 19 06:05:59 PM PDT 24 |
Finished | Jul 19 06:06:15 PM PDT 24 |
Peak memory | 242116 kb |
Host | smart-17eda29c-ba30-431f-b678-94758e504551 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157032905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1157032905 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3120654661 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 56924938862 ps |
CPU time | 1463.69 seconds |
Started | Jul 19 06:06:09 PM PDT 24 |
Finished | Jul 19 06:30:35 PM PDT 24 |
Peak memory | 379812 kb |
Host | smart-df793242-981b-44e9-8a00-930ec70e060c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120654661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.3120654661 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.2362805309 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 22394913 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:06:07 PM PDT 24 |
Finished | Jul 19 06:06:10 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-b09c8c51-68ad-4c4c-8d1d-1a22cdfaf5a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362805309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.2362805309 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.1392574033 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 125856271607 ps |
CPU time | 1270.99 seconds |
Started | Jul 19 06:05:59 PM PDT 24 |
Finished | Jul 19 06:27:13 PM PDT 24 |
Peak memory | 203320 kb |
Host | smart-dc34f817-f444-4877-bd85-bd88fc72d236 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392574033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .1392574033 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.1663377129 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 8429349479 ps |
CPU time | 633.77 seconds |
Started | Jul 19 06:06:07 PM PDT 24 |
Finished | Jul 19 06:16:42 PM PDT 24 |
Peak memory | 375596 kb |
Host | smart-002b4a47-a98e-4490-a825-bf6435b2ac34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663377129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.1663377129 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.2102066374 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 5679388355 ps |
CPU time | 29.41 seconds |
Started | Jul 19 06:06:08 PM PDT 24 |
Finished | Jul 19 06:06:40 PM PDT 24 |
Peak memory | 215924 kb |
Host | smart-aa95f250-5e68-4fc8-8880-a5db7c7f46d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102066374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.2102066374 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.1397522574 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 700527576 ps |
CPU time | 16.05 seconds |
Started | Jul 19 06:06:08 PM PDT 24 |
Finished | Jul 19 06:06:26 PM PDT 24 |
Peak memory | 251860 kb |
Host | smart-5e4553d3-4c1e-4319-925b-000405b42a03 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397522574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.1397522574 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3485617082 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 1400427385 ps |
CPU time | 79.42 seconds |
Started | Jul 19 06:06:06 PM PDT 24 |
Finished | Jul 19 06:07:26 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-a187412f-0359-4e54-8fbe-7b21d815195b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485617082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3485617082 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.312344251 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 13139994934 ps |
CPU time | 164.67 seconds |
Started | Jul 19 06:06:08 PM PDT 24 |
Finished | Jul 19 06:08:55 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-24d02149-348f-4d09-bd95-64f5ab06745b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312344251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _mem_walk.312344251 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.3340608582 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 54245176713 ps |
CPU time | 976.56 seconds |
Started | Jul 19 06:05:57 PM PDT 24 |
Finished | Jul 19 06:22:17 PM PDT 24 |
Peak memory | 375652 kb |
Host | smart-97e4fb3b-311c-40f6-b9c8-441b34527f1d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340608582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3340608582 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.2915996689 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 845964232 ps |
CPU time | 7.62 seconds |
Started | Jul 19 06:06:07 PM PDT 24 |
Finished | Jul 19 06:06:17 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-884372b8-daaa-4643-8546-7b6f570c538e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915996689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14. sram_ctrl_partial_access.2915996689 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2560925687 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 24294855274 ps |
CPU time | 371.91 seconds |
Started | Jul 19 06:06:10 PM PDT 24 |
Finished | Jul 19 06:12:24 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-d577ebfd-bf1b-42c0-9e39-dcd74263001c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560925687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.2560925687 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.2530642967 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 1770896848 ps |
CPU time | 4.01 seconds |
Started | Jul 19 06:06:08 PM PDT 24 |
Finished | Jul 19 06:06:15 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-ce96f063-b045-4876-99b3-7940b77e9fe4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530642967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2530642967 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.1332053734 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 3646732788 ps |
CPU time | 1016.23 seconds |
Started | Jul 19 06:06:06 PM PDT 24 |
Finished | Jul 19 06:23:04 PM PDT 24 |
Peak memory | 378800 kb |
Host | smart-54e134ce-8184-4655-884f-1f67c7605db5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332053734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1332053734 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.557442678 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 785886507 ps |
CPU time | 8.99 seconds |
Started | Jul 19 06:06:00 PM PDT 24 |
Finished | Jul 19 06:06:11 PM PDT 24 |
Peak memory | 214072 kb |
Host | smart-80891ee8-c63c-44cf-b822-dc0053f02bcf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557442678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.557442678 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.208863391 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 81742498984 ps |
CPU time | 6421.86 seconds |
Started | Jul 19 06:06:08 PM PDT 24 |
Finished | Jul 19 07:53:13 PM PDT 24 |
Peak memory | 389144 kb |
Host | smart-fa0db6a1-9f66-4a2a-aeb6-4fd8682a9dab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208863391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_stress_all.208863391 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1806139749 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 3792493192 ps |
CPU time | 47.79 seconds |
Started | Jul 19 06:06:07 PM PDT 24 |
Finished | Jul 19 06:06:57 PM PDT 24 |
Peak memory | 211208 kb |
Host | smart-aac7bb7d-12e3-4d8f-a8c4-eb95a5462be1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1806139749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1806139749 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1550469727 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 6938152582 ps |
CPU time | 273.74 seconds |
Started | Jul 19 06:05:59 PM PDT 24 |
Finished | Jul 19 06:10:36 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-5144daea-3fd4-4572-9105-0b0a76f403a3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550469727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.1550469727 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2252478458 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 693253987 ps |
CPU time | 12.45 seconds |
Started | Jul 19 06:06:06 PM PDT 24 |
Finished | Jul 19 06:06:20 PM PDT 24 |
Peak memory | 235564 kb |
Host | smart-227009a9-7452-43ea-9314-3563b1ffd310 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252478458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.2252478458 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2631154497 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 15734945236 ps |
CPU time | 1657.73 seconds |
Started | Jul 19 06:06:17 PM PDT 24 |
Finished | Jul 19 06:33:56 PM PDT 24 |
Peak memory | 379820 kb |
Host | smart-942b00e8-3f15-431a-ac23-07ba12af27be |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631154497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.2631154497 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.746647202 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 34980358 ps |
CPU time | 0.63 seconds |
Started | Jul 19 06:06:25 PM PDT 24 |
Finished | Jul 19 06:06:27 PM PDT 24 |
Peak memory | 202536 kb |
Host | smart-171137a2-17bb-4bc9-90b4-ee995756d9d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746647202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.746647202 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.44550684 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 259508202240 ps |
CPU time | 1089.66 seconds |
Started | Jul 19 06:06:15 PM PDT 24 |
Finished | Jul 19 06:24:27 PM PDT 24 |
Peak memory | 203804 kb |
Host | smart-4007f2fb-7075-4fa8-8742-bb04c4fb29fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44550684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.44550684 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.878507458 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 10142560076 ps |
CPU time | 393.21 seconds |
Started | Jul 19 06:06:14 PM PDT 24 |
Finished | Jul 19 06:12:50 PM PDT 24 |
Peak memory | 367480 kb |
Host | smart-08b56ccb-3efc-4f39-8a4a-eeee5d210f9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878507458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executabl e.878507458 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.3810987255 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 9558002710 ps |
CPU time | 62.7 seconds |
Started | Jul 19 06:06:19 PM PDT 24 |
Finished | Jul 19 06:07:22 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-fb549071-8f02-4641-bac1-657f877f751d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810987255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.3810987255 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.175497307 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 1728448234 ps |
CPU time | 112.25 seconds |
Started | Jul 19 06:06:14 PM PDT 24 |
Finished | Jul 19 06:08:09 PM PDT 24 |
Peak memory | 363364 kb |
Host | smart-632b9d6a-5a74-4b2d-a769-d7b8a689070c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175497307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.sram_ctrl_max_throughput.175497307 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2316128517 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 5244960919 ps |
CPU time | 82 seconds |
Started | Jul 19 06:06:21 PM PDT 24 |
Finished | Jul 19 06:07:43 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-e459dbd1-539f-45e2-a987-b81a5c8d04d1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316128517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.2316128517 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.1868815303 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 57659851220 ps |
CPU time | 177.98 seconds |
Started | Jul 19 06:06:25 PM PDT 24 |
Finished | Jul 19 06:09:24 PM PDT 24 |
Peak memory | 212184 kb |
Host | smart-8f615a71-e598-4ea6-9b6b-05a25089d119 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868815303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.1868815303 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.3881149297 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 56097120426 ps |
CPU time | 1200.73 seconds |
Started | Jul 19 06:06:13 PM PDT 24 |
Finished | Jul 19 06:26:15 PM PDT 24 |
Peak memory | 378760 kb |
Host | smart-3fc7faf6-8651-412f-86ba-edd2c9ec987c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881149297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.3881149297 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.2974952496 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 6125548853 ps |
CPU time | 213.77 seconds |
Started | Jul 19 06:06:15 PM PDT 24 |
Finished | Jul 19 06:09:51 PM PDT 24 |
Peak memory | 367564 kb |
Host | smart-89b3a987-a843-4944-bdcc-7574a2b41449 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974952496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.2974952496 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.100138897 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 17961189420 ps |
CPU time | 375.86 seconds |
Started | Jul 19 06:06:14 PM PDT 24 |
Finished | Jul 19 06:12:32 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-12892c54-4538-4a56-ba25-c465119bbf19 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100138897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.sram_ctrl_partial_access_b2b.100138897 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.4068220697 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1473098383 ps |
CPU time | 3.6 seconds |
Started | Jul 19 06:06:15 PM PDT 24 |
Finished | Jul 19 06:06:21 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-f3f41830-d028-4ba1-bede-29c917f67e9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068220697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.4068220697 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.1575168338 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 6390735447 ps |
CPU time | 447.73 seconds |
Started | Jul 19 06:06:14 PM PDT 24 |
Finished | Jul 19 06:13:44 PM PDT 24 |
Peak memory | 375680 kb |
Host | smart-ca992984-9ff8-4738-9960-5bd87f47aeeb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575168338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1575168338 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.203575551 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 1341717748 ps |
CPU time | 6.37 seconds |
Started | Jul 19 06:06:05 PM PDT 24 |
Finished | Jul 19 06:06:13 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-603abf1c-d08b-4424-9816-b4bd631fead2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203575551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.203575551 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.2556889896 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 703864560430 ps |
CPU time | 7441.58 seconds |
Started | Jul 19 06:06:25 PM PDT 24 |
Finished | Jul 19 08:10:29 PM PDT 24 |
Peak memory | 402372 kb |
Host | smart-533fb8b0-5bd1-402d-bec6-ba0e1db9fb14 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556889896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.2556889896 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2174178041 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 3015376023 ps |
CPU time | 58.35 seconds |
Started | Jul 19 06:06:23 PM PDT 24 |
Finished | Jul 19 06:07:23 PM PDT 24 |
Peak memory | 273392 kb |
Host | smart-4134cfca-6196-43e8-8e9c-e2d89caf3b41 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2174178041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2174178041 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3269824193 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 16079186225 ps |
CPU time | 304.67 seconds |
Started | Jul 19 06:06:16 PM PDT 24 |
Finished | Jul 19 06:11:22 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-07808aec-cce3-4e5b-8a03-2e98414cb141 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269824193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.3269824193 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3475736311 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 1618680356 ps |
CPU time | 164.28 seconds |
Started | Jul 19 06:06:18 PM PDT 24 |
Finished | Jul 19 06:09:03 PM PDT 24 |
Peak memory | 370588 kb |
Host | smart-525004f7-c288-4833-b48f-49d9da54943d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475736311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.3475736311 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1879189934 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 14892486949 ps |
CPU time | 1046.43 seconds |
Started | Jul 19 06:06:31 PM PDT 24 |
Finished | Jul 19 06:24:01 PM PDT 24 |
Peak memory | 379456 kb |
Host | smart-bbd919a6-a345-4780-ad59-265cadcd9586 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879189934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.1879189934 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.2187897222 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 25661725 ps |
CPU time | 0.66 seconds |
Started | Jul 19 06:06:42 PM PDT 24 |
Finished | Jul 19 06:06:44 PM PDT 24 |
Peak memory | 202340 kb |
Host | smart-de32e5c1-49fc-4fa1-807a-fe8e64839de5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187897222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2187897222 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.963112389 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 87480926918 ps |
CPU time | 2070.04 seconds |
Started | Jul 19 06:06:32 PM PDT 24 |
Finished | Jul 19 06:41:05 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-577c1bd1-9757-4acd-818c-4d4b0f278d97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963112389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection. 963112389 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.3098690837 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 125045527984 ps |
CPU time | 913.73 seconds |
Started | Jul 19 06:06:31 PM PDT 24 |
Finished | Jul 19 06:21:48 PM PDT 24 |
Peak memory | 375624 kb |
Host | smart-68438e45-5ca2-4081-9618-ee27d3aa2145 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098690837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.3098690837 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.2615797325 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 48779749868 ps |
CPU time | 82.94 seconds |
Started | Jul 19 06:06:30 PM PDT 24 |
Finished | Jul 19 06:07:56 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-d2663883-37cf-47b3-bf69-0b7e9abe769f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615797325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.2615797325 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.248351076 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 3176637416 ps |
CPU time | 133.77 seconds |
Started | Jul 19 06:06:32 PM PDT 24 |
Finished | Jul 19 06:08:49 PM PDT 24 |
Peak memory | 372700 kb |
Host | smart-c8fd8003-95d0-4ba8-ba7e-db5018ab6f30 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248351076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.sram_ctrl_max_throughput.248351076 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.840890162 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 2927569719 ps |
CPU time | 89.33 seconds |
Started | Jul 19 06:06:32 PM PDT 24 |
Finished | Jul 19 06:08:05 PM PDT 24 |
Peak memory | 211284 kb |
Host | smart-bff0a6fe-e6a5-48c6-bb63-29ccd6017fd8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840890162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_mem_partial_access.840890162 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.2795628332 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 20733705880 ps |
CPU time | 170.68 seconds |
Started | Jul 19 06:06:30 PM PDT 24 |
Finished | Jul 19 06:09:24 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-ca399a38-47e5-4553-8265-d6d017f265bc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795628332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.2795628332 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.1962838469 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 83150489332 ps |
CPU time | 1199.29 seconds |
Started | Jul 19 06:06:31 PM PDT 24 |
Finished | Jul 19 06:26:34 PM PDT 24 |
Peak memory | 373108 kb |
Host | smart-8caf2969-58b8-46c6-b60a-8ce45bad6cd1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962838469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.1962838469 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.3083340630 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 360424535 ps |
CPU time | 3.35 seconds |
Started | Jul 19 06:06:30 PM PDT 24 |
Finished | Jul 19 06:06:37 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-54a63e35-33ce-41fc-86ca-337ea58e23d9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083340630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.3083340630 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2871066070 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 12350631705 ps |
CPU time | 258.74 seconds |
Started | Jul 19 06:06:31 PM PDT 24 |
Finished | Jul 19 06:10:53 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-5ecacdf7-23b1-47b0-8e8f-c9b6c7251edf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871066070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.2871066070 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.1075077779 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 360163069 ps |
CPU time | 3.17 seconds |
Started | Jul 19 06:06:33 PM PDT 24 |
Finished | Jul 19 06:06:39 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-1e92c107-fa4c-4a27-b275-fe2935fa6c47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075077779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1075077779 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.721739355 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 3741347412 ps |
CPU time | 1157.5 seconds |
Started | Jul 19 06:06:29 PM PDT 24 |
Finished | Jul 19 06:25:50 PM PDT 24 |
Peak memory | 375528 kb |
Host | smart-db8c785f-11ab-48f5-aa24-e7d4fec9e3f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721739355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.721739355 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.2039986999 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 565613999 ps |
CPU time | 12.94 seconds |
Started | Jul 19 06:06:25 PM PDT 24 |
Finished | Jul 19 06:06:39 PM PDT 24 |
Peak memory | 241632 kb |
Host | smart-615e1d64-6b11-4165-8482-92fa1961cdb5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039986999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2039986999 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.3383493749 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 129736774793 ps |
CPU time | 5017.34 seconds |
Started | Jul 19 06:06:41 PM PDT 24 |
Finished | Jul 19 07:30:21 PM PDT 24 |
Peak memory | 380800 kb |
Host | smart-d863fa2c-e902-4564-afc7-9a05c431a0bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383493749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.3383493749 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3367169966 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 3213287854 ps |
CPU time | 38.51 seconds |
Started | Jul 19 06:06:40 PM PDT 24 |
Finished | Jul 19 06:07:21 PM PDT 24 |
Peak memory | 211172 kb |
Host | smart-5a4729a0-e8e9-4b60-9dc5-86bc1f3cc9bd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3367169966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3367169966 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1772436887 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 21881370899 ps |
CPU time | 329.1 seconds |
Started | Jul 19 06:06:30 PM PDT 24 |
Finished | Jul 19 06:12:03 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-282e8ea4-e405-4ab6-85f5-d4d63d0c9742 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772436887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.1772436887 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2819703316 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 3951940051 ps |
CPU time | 7.63 seconds |
Started | Jul 19 06:06:30 PM PDT 24 |
Finished | Jul 19 06:06:41 PM PDT 24 |
Peak memory | 218244 kb |
Host | smart-09093f88-e32e-4566-bb4a-d6fee4380f80 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819703316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2819703316 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3614418892 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 67095630322 ps |
CPU time | 1362.43 seconds |
Started | Jul 19 06:06:42 PM PDT 24 |
Finished | Jul 19 06:29:26 PM PDT 24 |
Peak memory | 366544 kb |
Host | smart-d93a45a1-5956-47e3-b89e-8942c2f40b4c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614418892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.3614418892 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.1689826344 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 31208595 ps |
CPU time | 0.67 seconds |
Started | Jul 19 06:06:49 PM PDT 24 |
Finished | Jul 19 06:06:50 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-04ea1005-f01f-4419-9cda-f7377755ed0f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689826344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1689826344 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.2009325211 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 59984590671 ps |
CPU time | 1382.12 seconds |
Started | Jul 19 06:06:40 PM PDT 24 |
Finished | Jul 19 06:29:44 PM PDT 24 |
Peak memory | 203488 kb |
Host | smart-7759bfda-5d58-466e-abe4-dde1ec27293b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009325211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .2009325211 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.4087591625 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 13721452344 ps |
CPU time | 2280.85 seconds |
Started | Jul 19 06:06:51 PM PDT 24 |
Finished | Jul 19 06:44:53 PM PDT 24 |
Peak memory | 379824 kb |
Host | smart-727f03c9-9956-40e6-b286-b0fc303414b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087591625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.4087591625 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.3380591993 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 25850067230 ps |
CPU time | 28.17 seconds |
Started | Jul 19 06:06:42 PM PDT 24 |
Finished | Jul 19 06:07:11 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-2617b280-ba43-46d5-a13a-e2accb9d4f38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380591993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.3380591993 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.131348782 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 2857701584 ps |
CPU time | 13.38 seconds |
Started | Jul 19 06:06:40 PM PDT 24 |
Finished | Jul 19 06:06:55 PM PDT 24 |
Peak memory | 238092 kb |
Host | smart-32feadcc-2dcf-4270-98d7-61ee4d282f89 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131348782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.sram_ctrl_max_throughput.131348782 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3371010303 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 4725164189 ps |
CPU time | 150.18 seconds |
Started | Jul 19 06:06:50 PM PDT 24 |
Finished | Jul 19 06:09:22 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-71044e19-01f7-464c-b4a4-2b50f61266a4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371010303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.3371010303 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.3012125782 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 27735988551 ps |
CPU time | 164.98 seconds |
Started | Jul 19 06:06:50 PM PDT 24 |
Finished | Jul 19 06:09:36 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-387ad3a3-0c41-4f29-8c60-c553637ae6a1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012125782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.3012125782 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.2292491232 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 10479658005 ps |
CPU time | 1907.27 seconds |
Started | Jul 19 06:06:42 PM PDT 24 |
Finished | Jul 19 06:38:30 PM PDT 24 |
Peak memory | 379836 kb |
Host | smart-5db5ceed-a32b-4d80-b360-1821ce05eccd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292491232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.2292491232 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.3199362940 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 795213794 ps |
CPU time | 4.49 seconds |
Started | Jul 19 06:06:39 PM PDT 24 |
Finished | Jul 19 06:06:46 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-6d073e14-d4e1-46a7-9e1f-147b004ca0c1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199362940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.3199362940 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1154362647 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 43719152215 ps |
CPU time | 545.95 seconds |
Started | Jul 19 06:06:41 PM PDT 24 |
Finished | Jul 19 06:15:48 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-2425c0d0-8df7-422d-8afa-ecdb5254e11d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154362647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.1154362647 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.2911271147 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 352967146 ps |
CPU time | 3.32 seconds |
Started | Jul 19 06:06:50 PM PDT 24 |
Finished | Jul 19 06:06:54 PM PDT 24 |
Peak memory | 203032 kb |
Host | smart-a6490a7b-53eb-41f4-85ca-042b8a85b1fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911271147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2911271147 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.1046369300 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 47934220814 ps |
CPU time | 518.34 seconds |
Started | Jul 19 06:06:51 PM PDT 24 |
Finished | Jul 19 06:15:30 PM PDT 24 |
Peak memory | 378688 kb |
Host | smart-852b4f37-4de1-4768-a295-a0caac7e0d8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046369300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1046369300 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.3941571547 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 1047085339 ps |
CPU time | 47.09 seconds |
Started | Jul 19 06:06:41 PM PDT 24 |
Finished | Jul 19 06:07:29 PM PDT 24 |
Peak memory | 289092 kb |
Host | smart-10aa6a47-91f2-403c-88dd-a59a89b1698f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941571547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3941571547 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.2268907048 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 48142901319 ps |
CPU time | 716.61 seconds |
Started | Jul 19 06:06:48 PM PDT 24 |
Finished | Jul 19 06:18:46 PM PDT 24 |
Peak memory | 371648 kb |
Host | smart-2aae30f0-7559-4b8e-adf5-eecb03c8932d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268907048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.2268907048 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1923747342 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 641256579 ps |
CPU time | 24.09 seconds |
Started | Jul 19 06:06:49 PM PDT 24 |
Finished | Jul 19 06:07:14 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-e169a5cc-2b32-4ce4-b3c5-b6892a41e325 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1923747342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1923747342 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.4060080954 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 32228082213 ps |
CPU time | 297.96 seconds |
Started | Jul 19 06:06:41 PM PDT 24 |
Finished | Jul 19 06:11:41 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-40a03190-eedd-4ebc-a38f-6fd6341720c1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060080954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.4060080954 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1468025440 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 743514832 ps |
CPU time | 48.38 seconds |
Started | Jul 19 06:06:43 PM PDT 24 |
Finished | Jul 19 06:07:32 PM PDT 24 |
Peak memory | 294060 kb |
Host | smart-e0bf0ec8-be02-4cd1-af4c-71f3ea103c09 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468025440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1468025440 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1428846133 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 9841551805 ps |
CPU time | 186.54 seconds |
Started | Jul 19 06:06:56 PM PDT 24 |
Finished | Jul 19 06:10:04 PM PDT 24 |
Peak memory | 341968 kb |
Host | smart-50b6172f-3351-4dfb-84ba-535b76e8ae7e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428846133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.1428846133 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.1274702551 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 20336276 ps |
CPU time | 0.66 seconds |
Started | Jul 19 06:07:10 PM PDT 24 |
Finished | Jul 19 06:07:11 PM PDT 24 |
Peak memory | 202476 kb |
Host | smart-d93f8f61-4da3-4ccf-9a2f-bc9a7e531451 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274702551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.1274702551 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.3284561896 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 694752901913 ps |
CPU time | 835.96 seconds |
Started | Jul 19 06:06:51 PM PDT 24 |
Finished | Jul 19 06:20:48 PM PDT 24 |
Peak memory | 203552 kb |
Host | smart-596d5491-2727-4dd4-b821-754dadb4751d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284561896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .3284561896 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.3570912215 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 58612475253 ps |
CPU time | 927.64 seconds |
Started | Jul 19 06:06:56 PM PDT 24 |
Finished | Jul 19 06:22:25 PM PDT 24 |
Peak memory | 374692 kb |
Host | smart-0a44f12d-910f-478d-a0d4-2343b323e032 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570912215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.3570912215 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.258475177 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 25757173275 ps |
CPU time | 40.02 seconds |
Started | Jul 19 06:06:58 PM PDT 24 |
Finished | Jul 19 06:07:39 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-48189c90-52f5-45af-96da-6f0e5e513947 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258475177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc alation.258475177 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.1424184800 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 739414315 ps |
CPU time | 26.37 seconds |
Started | Jul 19 06:06:58 PM PDT 24 |
Finished | Jul 19 06:07:25 PM PDT 24 |
Peak memory | 268284 kb |
Host | smart-701346f3-379c-4c9f-ad45-6294af3f967e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424184800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.1424184800 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.804779013 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 1028426488 ps |
CPU time | 72.3 seconds |
Started | Jul 19 06:06:56 PM PDT 24 |
Finished | Jul 19 06:08:10 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-95a26860-c4c5-4440-9ee6-46428fcb1e63 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804779013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_mem_partial_access.804779013 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.1381242203 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 5477881275 ps |
CPU time | 298.99 seconds |
Started | Jul 19 06:06:55 PM PDT 24 |
Finished | Jul 19 06:11:56 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-c8ad1ab6-c6d9-4ddd-be79-6b6c9f5ca6d3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381242203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.1381242203 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.135588862 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 42924165098 ps |
CPU time | 336.03 seconds |
Started | Jul 19 06:06:49 PM PDT 24 |
Finished | Jul 19 06:12:27 PM PDT 24 |
Peak memory | 381088 kb |
Host | smart-f20563a1-ae30-4dba-9555-72c1c3a4cc14 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135588862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip le_keys.135588862 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.207370935 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 626312540 ps |
CPU time | 25.9 seconds |
Started | Jul 19 06:06:49 PM PDT 24 |
Finished | Jul 19 06:07:16 PM PDT 24 |
Peak memory | 266272 kb |
Host | smart-f0152bb6-3c09-40b4-b909-2df775afd713 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207370935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.s ram_ctrl_partial_access.207370935 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3686546119 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 17077513569 ps |
CPU time | 319.94 seconds |
Started | Jul 19 06:06:47 PM PDT 24 |
Finished | Jul 19 06:12:08 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-34140b6c-a387-4c92-9e9a-2614861b3fe6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686546119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.3686546119 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.2729672932 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 7410296139 ps |
CPU time | 190.57 seconds |
Started | Jul 19 06:06:59 PM PDT 24 |
Finished | Jul 19 06:10:11 PM PDT 24 |
Peak memory | 350180 kb |
Host | smart-97129570-e9ff-418a-86b1-b519b3ff3a2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729672932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2729672932 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.1239005389 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 2748895477 ps |
CPU time | 14.09 seconds |
Started | Jul 19 06:06:49 PM PDT 24 |
Finished | Jul 19 06:07:04 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-bb1e77bf-7bb7-4cc4-a32b-813c12c1d301 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239005389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1239005389 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.3768182968 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 68190118500 ps |
CPU time | 2192.35 seconds |
Started | Jul 19 06:06:59 PM PDT 24 |
Finished | Jul 19 06:43:33 PM PDT 24 |
Peak memory | 379764 kb |
Host | smart-3f202f98-d054-49fd-9c14-f9512e19c843 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768182968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.3768182968 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3724971354 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 1686405553 ps |
CPU time | 69.86 seconds |
Started | Jul 19 06:07:00 PM PDT 24 |
Finished | Jul 19 06:08:10 PM PDT 24 |
Peak memory | 286632 kb |
Host | smart-732f09e8-e20d-4381-9713-3bf96a884c5f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3724971354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3724971354 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3344201151 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 23029379798 ps |
CPU time | 395.82 seconds |
Started | Jul 19 06:06:49 PM PDT 24 |
Finished | Jul 19 06:13:25 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-35eeef4f-951c-420d-897c-1d3d29ca2e77 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344201151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.3344201151 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.328044839 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 1169351605 ps |
CPU time | 22.01 seconds |
Started | Jul 19 06:06:58 PM PDT 24 |
Finished | Jul 19 06:07:22 PM PDT 24 |
Peak memory | 268292 kb |
Host | smart-f37af4ad-d0b7-416e-9928-3814f87e19b2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328044839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.328044839 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2903268267 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 17718321129 ps |
CPU time | 664.05 seconds |
Started | Jul 19 06:07:15 PM PDT 24 |
Finished | Jul 19 06:18:20 PM PDT 24 |
Peak memory | 377548 kb |
Host | smart-5e2bf585-e244-42a9-bf00-f55dc9d6997b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903268267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.2903268267 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.2738828306 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 42127062 ps |
CPU time | 0.67 seconds |
Started | Jul 19 06:07:16 PM PDT 24 |
Finished | Jul 19 06:07:18 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-3b939207-e027-4735-b660-1f7ed6616a0d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738828306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.2738828306 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.2352330866 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 19663019601 ps |
CPU time | 1850.08 seconds |
Started | Jul 19 06:07:15 PM PDT 24 |
Finished | Jul 19 06:38:06 PM PDT 24 |
Peak memory | 378672 kb |
Host | smart-e41c855c-4d22-4079-a337-d76415e73db8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352330866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.2352330866 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.164013424 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 33338105146 ps |
CPU time | 58.14 seconds |
Started | Jul 19 06:07:06 PM PDT 24 |
Finished | Jul 19 06:08:05 PM PDT 24 |
Peak memory | 215808 kb |
Host | smart-babff998-8ac6-4a2f-872d-8a5de61db7a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164013424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esc alation.164013424 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.3945888350 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 4923042202 ps |
CPU time | 14.35 seconds |
Started | Jul 19 06:07:04 PM PDT 24 |
Finished | Jul 19 06:07:20 PM PDT 24 |
Peak memory | 241900 kb |
Host | smart-694271f9-3253-4fe5-bce8-b85f61b52d00 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945888350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.3945888350 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.2999992845 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 33675706087 ps |
CPU time | 82.28 seconds |
Started | Jul 19 06:07:16 PM PDT 24 |
Finished | Jul 19 06:08:39 PM PDT 24 |
Peak memory | 211380 kb |
Host | smart-b2e6c592-18a4-4bd3-ba9f-c2b47764518e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999992845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.2999992845 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.3999754607 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 27630093251 ps |
CPU time | 169.05 seconds |
Started | Jul 19 06:07:15 PM PDT 24 |
Finished | Jul 19 06:10:06 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-0953424d-5509-4870-9868-4e76963f9296 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999754607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.3999754607 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.876723701 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 6943497504 ps |
CPU time | 782.59 seconds |
Started | Jul 19 06:07:06 PM PDT 24 |
Finished | Jul 19 06:20:09 PM PDT 24 |
Peak memory | 380692 kb |
Host | smart-4b54bae9-8a84-445c-a8a0-89af02b85380 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876723701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip le_keys.876723701 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.254797550 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 3131607474 ps |
CPU time | 171.43 seconds |
Started | Jul 19 06:07:07 PM PDT 24 |
Finished | Jul 19 06:09:59 PM PDT 24 |
Peak memory | 366380 kb |
Host | smart-7f6d558b-e231-4366-803a-43e0de42cd66 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254797550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s ram_ctrl_partial_access.254797550 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2255570723 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 6799267488 ps |
CPU time | 211.24 seconds |
Started | Jul 19 06:07:05 PM PDT 24 |
Finished | Jul 19 06:10:37 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-0f960da5-1602-4c4a-9652-05d8700bdfc3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255570723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.2255570723 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.3258763209 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 1345921915 ps |
CPU time | 3.11 seconds |
Started | Jul 19 06:07:16 PM PDT 24 |
Finished | Jul 19 06:07:20 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-1777a948-92ce-41da-bc5b-5c00f3b814ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258763209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3258763209 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.3820403774 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 21942998880 ps |
CPU time | 813.3 seconds |
Started | Jul 19 06:07:17 PM PDT 24 |
Finished | Jul 19 06:20:51 PM PDT 24 |
Peak memory | 379036 kb |
Host | smart-46ff0780-92af-4cc6-8efe-f0bb6ebde64c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820403774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3820403774 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.987951529 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 4151667434 ps |
CPU time | 21.81 seconds |
Started | Jul 19 06:07:04 PM PDT 24 |
Finished | Jul 19 06:07:27 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-ba17abf5-e3ed-46a9-9950-fef5ce55876b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987951529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.987951529 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.826123648 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 790174678447 ps |
CPU time | 4140.61 seconds |
Started | Jul 19 06:07:16 PM PDT 24 |
Finished | Jul 19 07:16:18 PM PDT 24 |
Peak memory | 380996 kb |
Host | smart-95f0970a-96d4-4c5e-be74-a96f72e1a4fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826123648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_stress_all.826123648 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3007377441 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 2873880673 ps |
CPU time | 195.93 seconds |
Started | Jul 19 06:07:04 PM PDT 24 |
Finished | Jul 19 06:10:21 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-eede27b8-85f9-4142-98d1-f83d71ba1f81 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007377441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.3007377441 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3397712421 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 1385502452 ps |
CPU time | 7.44 seconds |
Started | Jul 19 06:07:07 PM PDT 24 |
Finished | Jul 19 06:07:15 PM PDT 24 |
Peak memory | 217432 kb |
Host | smart-e1e65c13-4d8d-4a89-a987-790365ba0560 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397712421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3397712421 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.181680964 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 52468072785 ps |
CPU time | 1387.79 seconds |
Started | Jul 19 06:04:07 PM PDT 24 |
Finished | Jul 19 06:27:16 PM PDT 24 |
Peak memory | 380784 kb |
Host | smart-d7d6c244-ff17-4555-b737-3f429fe64f25 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181680964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_access_during_key_req.181680964 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.3034845327 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 55354626 ps |
CPU time | 0.63 seconds |
Started | Jul 19 06:04:06 PM PDT 24 |
Finished | Jul 19 06:04:08 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-0a33aa4c-a35c-4e1d-9e54-848ae877bb33 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034845327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3034845327 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.2687777693 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 45930189056 ps |
CPU time | 828.72 seconds |
Started | Jul 19 06:04:12 PM PDT 24 |
Finished | Jul 19 06:18:02 PM PDT 24 |
Peak memory | 378768 kb |
Host | smart-1572a8b6-322f-4abc-9ab6-167e9a79df48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687777693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.2687777693 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.922631649 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 17469174845 ps |
CPU time | 55.54 seconds |
Started | Jul 19 06:04:02 PM PDT 24 |
Finished | Jul 19 06:04:58 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-e7e657e3-e970-4525-84c0-b4cc2c6aac87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922631649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esca lation.922631649 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.2736011117 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 735015008 ps |
CPU time | 40.09 seconds |
Started | Jul 19 06:04:01 PM PDT 24 |
Finished | Jul 19 06:04:42 PM PDT 24 |
Peak memory | 288760 kb |
Host | smart-34a9f89f-b70b-4a73-841a-7b3a66fbe4bf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736011117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.2736011117 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.324588593 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 2548451624 ps |
CPU time | 157.77 seconds |
Started | Jul 19 06:04:07 PM PDT 24 |
Finished | Jul 19 06:06:46 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-d1468c53-9712-45c1-a713-a92ac12cbe91 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324588593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. sram_ctrl_mem_partial_access.324588593 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.2802052764 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 36393463470 ps |
CPU time | 176.83 seconds |
Started | Jul 19 06:04:10 PM PDT 24 |
Finished | Jul 19 06:07:07 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-684999f3-596b-4a85-9ea9-75f7d0308bf8 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802052764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.2802052764 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.3665542647 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 122117903988 ps |
CPU time | 1969.78 seconds |
Started | Jul 19 06:04:02 PM PDT 24 |
Finished | Jul 19 06:36:52 PM PDT 24 |
Peak memory | 378252 kb |
Host | smart-d762526d-8628-477e-8ed7-0d271a9410f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665542647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.3665542647 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.229538429 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 3842453193 ps |
CPU time | 30.29 seconds |
Started | Jul 19 06:04:05 PM PDT 24 |
Finished | Jul 19 06:04:36 PM PDT 24 |
Peak memory | 277480 kb |
Host | smart-4643ca52-601b-429b-a5db-900d04421c21 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229538429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sr am_ctrl_partial_access.229538429 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3431720085 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 56003572534 ps |
CPU time | 334.88 seconds |
Started | Jul 19 06:04:02 PM PDT 24 |
Finished | Jul 19 06:09:37 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-dba84cae-6785-4572-a371-f88fc3a01f3b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431720085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.3431720085 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.847610067 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 363612490 ps |
CPU time | 3.3 seconds |
Started | Jul 19 06:04:11 PM PDT 24 |
Finished | Jul 19 06:04:15 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-16a0d315-e44b-4f45-b07e-cadf868dadf5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847610067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.847610067 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.1445272109 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 14039130904 ps |
CPU time | 1117.01 seconds |
Started | Jul 19 06:04:07 PM PDT 24 |
Finished | Jul 19 06:22:45 PM PDT 24 |
Peak memory | 373772 kb |
Host | smart-2e7fda5c-a658-40d2-9825-7dc21e9b447f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445272109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1445272109 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.419428467 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 124110760 ps |
CPU time | 1.9 seconds |
Started | Jul 19 06:04:08 PM PDT 24 |
Finished | Jul 19 06:04:11 PM PDT 24 |
Peak memory | 222000 kb |
Host | smart-6b52e389-cb05-4df9-adfa-d5220d090963 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419428467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_sec_cm.419428467 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.1629391151 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 828158146 ps |
CPU time | 5.31 seconds |
Started | Jul 19 06:04:02 PM PDT 24 |
Finished | Jul 19 06:04:08 PM PDT 24 |
Peak memory | 210304 kb |
Host | smart-db9d6f1a-6366-41ef-8667-8ecf328c865d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629391151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1629391151 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.3942220935 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 275518524018 ps |
CPU time | 8667.56 seconds |
Started | Jul 19 06:04:08 PM PDT 24 |
Finished | Jul 19 08:28:37 PM PDT 24 |
Peak memory | 380864 kb |
Host | smart-e8a7d3b1-8404-44d4-bfa1-c1b14e228174 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942220935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.3942220935 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2862825555 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 1117882819 ps |
CPU time | 36.51 seconds |
Started | Jul 19 06:04:08 PM PDT 24 |
Finished | Jul 19 06:04:46 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-abbc2370-a922-47a3-ba91-f6fe118b9e5c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2862825555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2862825555 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.4019128758 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 3155693349 ps |
CPU time | 164.09 seconds |
Started | Jul 19 06:04:04 PM PDT 24 |
Finished | Jul 19 06:06:49 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-cea2ba83-ca84-40f6-8e96-67ab97b88146 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019128758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.4019128758 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2786725287 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 3398224901 ps |
CPU time | 73.88 seconds |
Started | Jul 19 06:04:06 PM PDT 24 |
Finished | Jul 19 06:05:21 PM PDT 24 |
Peak memory | 321436 kb |
Host | smart-a552e996-daa7-4e1f-9204-e53b28209cb2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786725287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.2786725287 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.350893395 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 66834971013 ps |
CPU time | 754.9 seconds |
Started | Jul 19 06:07:21 PM PDT 24 |
Finished | Jul 19 06:19:57 PM PDT 24 |
Peak memory | 368612 kb |
Host | smart-c72a462d-2ae3-4050-bc37-42f7f21a3a7c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350893395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 20.sram_ctrl_access_during_key_req.350893395 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.3655462727 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 23726655 ps |
CPU time | 0.7 seconds |
Started | Jul 19 06:07:29 PM PDT 24 |
Finished | Jul 19 06:07:30 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-772b21f7-2ff1-4a8d-a4cf-a5d7a33839ba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655462727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.3655462727 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.656940281 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 113042340644 ps |
CPU time | 1267.26 seconds |
Started | Jul 19 06:07:22 PM PDT 24 |
Finished | Jul 19 06:28:30 PM PDT 24 |
Peak memory | 203404 kb |
Host | smart-4bf2969c-5636-4972-8a88-665998408e73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656940281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection. 656940281 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.2032441447 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 57235936880 ps |
CPU time | 883.84 seconds |
Started | Jul 19 06:07:24 PM PDT 24 |
Finished | Jul 19 06:22:08 PM PDT 24 |
Peak memory | 376656 kb |
Host | smart-d51c9b94-ee1b-4b59-ab2e-9048030fb7ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032441447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.2032441447 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.3720885821 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 16290838088 ps |
CPU time | 50.8 seconds |
Started | Jul 19 06:07:23 PM PDT 24 |
Finished | Jul 19 06:08:14 PM PDT 24 |
Peak memory | 216044 kb |
Host | smart-8a757e0d-c005-4191-a987-250f2ab0bf74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720885821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.3720885821 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.1086443806 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 1497930630 ps |
CPU time | 64.62 seconds |
Started | Jul 19 06:07:25 PM PDT 24 |
Finished | Jul 19 06:08:30 PM PDT 24 |
Peak memory | 310052 kb |
Host | smart-3b64832a-0885-460e-9dbd-95640a6c8991 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086443806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.1086443806 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.27935852 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 10737929095 ps |
CPU time | 89.06 seconds |
Started | Jul 19 06:07:29 PM PDT 24 |
Finished | Jul 19 06:08:59 PM PDT 24 |
Peak memory | 219252 kb |
Host | smart-117bd67a-cd8c-4382-a868-48384c1e4fe5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27935852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_mem_partial_access.27935852 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.1593368002 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 14106500696 ps |
CPU time | 322.95 seconds |
Started | Jul 19 06:07:21 PM PDT 24 |
Finished | Jul 19 06:12:45 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-4bcd92d1-25fb-4398-8edd-8fa4cf0316ac |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593368002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.1593368002 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.683737151 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 40375575967 ps |
CPU time | 1884.92 seconds |
Started | Jul 19 06:07:23 PM PDT 24 |
Finished | Jul 19 06:38:49 PM PDT 24 |
Peak memory | 377768 kb |
Host | smart-be3099b3-ee2c-4236-a005-4fd3db93314a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683737151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip le_keys.683737151 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.3089593530 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 807779247 ps |
CPU time | 51.36 seconds |
Started | Jul 19 06:07:22 PM PDT 24 |
Finished | Jul 19 06:08:14 PM PDT 24 |
Peak memory | 294852 kb |
Host | smart-8622d5c4-c600-4d7d-a868-5dca8a9a2757 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089593530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.3089593530 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2598728750 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 5456640366 ps |
CPU time | 272.99 seconds |
Started | Jul 19 06:07:22 PM PDT 24 |
Finished | Jul 19 06:11:56 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-73b72b85-bb05-4333-9124-ce7495bde7b8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598728750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.2598728750 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.1680244535 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 359953836 ps |
CPU time | 3.44 seconds |
Started | Jul 19 06:07:22 PM PDT 24 |
Finished | Jul 19 06:07:26 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-b024e6a0-f273-4f11-a5dd-148fda82f138 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680244535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1680244535 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.180359354 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 3803946749 ps |
CPU time | 1185.78 seconds |
Started | Jul 19 06:07:21 PM PDT 24 |
Finished | Jul 19 06:27:08 PM PDT 24 |
Peak memory | 377728 kb |
Host | smart-f68f6bc2-6972-4b47-9ff9-0fd43ee71a4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180359354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.180359354 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.530569242 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 97334635483 ps |
CPU time | 4319.74 seconds |
Started | Jul 19 06:07:28 PM PDT 24 |
Finished | Jul 19 07:19:29 PM PDT 24 |
Peak memory | 381836 kb |
Host | smart-9577b4ce-77af-41b2-beb9-e3291aed3cd6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530569242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_stress_all.530569242 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4103483906 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 1008506231 ps |
CPU time | 9.72 seconds |
Started | Jul 19 06:07:32 PM PDT 24 |
Finished | Jul 19 06:07:42 PM PDT 24 |
Peak memory | 214260 kb |
Host | smart-57026e11-9b1c-4183-9722-e6c9e5c45103 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4103483906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.4103483906 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2492555030 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 14549457134 ps |
CPU time | 235.32 seconds |
Started | Jul 19 06:07:24 PM PDT 24 |
Finished | Jul 19 06:11:25 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-4e40c64a-d4fe-4127-8bed-4dc346371293 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492555030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.2492555030 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3426344683 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 733434770 ps |
CPU time | 40.19 seconds |
Started | Jul 19 06:07:22 PM PDT 24 |
Finished | Jul 19 06:08:03 PM PDT 24 |
Peak memory | 284644 kb |
Host | smart-75d6a944-9a1a-40a1-8161-fc7502ada9f2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426344683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3426344683 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2272412764 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 47428938976 ps |
CPU time | 1092.67 seconds |
Started | Jul 19 06:07:40 PM PDT 24 |
Finished | Jul 19 06:25:53 PM PDT 24 |
Peak memory | 380860 kb |
Host | smart-73711d63-8a84-472e-a146-143bf5a6ef7b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272412764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.2272412764 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.1039900597 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 34848217 ps |
CPU time | 0.7 seconds |
Started | Jul 19 06:07:42 PM PDT 24 |
Finished | Jul 19 06:07:44 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-ed437e0e-e4c9-4745-a061-d8f6e9ecbecf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039900597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1039900597 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.129049197 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 44559652708 ps |
CPU time | 1213.61 seconds |
Started | Jul 19 06:07:28 PM PDT 24 |
Finished | Jul 19 06:27:43 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-1d27a094-895e-4eed-9e24-52a77191ef70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129049197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection. 129049197 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.2047337703 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 15915893778 ps |
CPU time | 1132.16 seconds |
Started | Jul 19 06:07:41 PM PDT 24 |
Finished | Jul 19 06:26:34 PM PDT 24 |
Peak memory | 378740 kb |
Host | smart-68202df2-ac05-4f42-836d-2aadeeedc86c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047337703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.2047337703 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.2622787544 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 12165366423 ps |
CPU time | 45.93 seconds |
Started | Jul 19 06:07:39 PM PDT 24 |
Finished | Jul 19 06:08:25 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-62ca6b4c-1f40-429a-8178-ac0110740a48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622787544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.2622787544 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.1047199049 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 785105112 ps |
CPU time | 165.28 seconds |
Started | Jul 19 06:07:36 PM PDT 24 |
Finished | Jul 19 06:10:22 PM PDT 24 |
Peak memory | 368680 kb |
Host | smart-1e47989c-5770-4a05-b7c5-82fb5a5c2f63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047199049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.1047199049 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3617409859 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 16704010389 ps |
CPU time | 88.54 seconds |
Started | Jul 19 06:07:41 PM PDT 24 |
Finished | Jul 19 06:09:10 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-f5b8152b-6d17-4827-8ed3-3934e0680a65 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617409859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.3617409859 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.4171722271 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 57516467675 ps |
CPU time | 332.47 seconds |
Started | Jul 19 06:07:41 PM PDT 24 |
Finished | Jul 19 06:13:14 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-586120ab-08c6-495a-b9c8-7adc346119c7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171722271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.4171722271 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.2086756136 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 2280775376 ps |
CPU time | 132.4 seconds |
Started | Jul 19 06:07:32 PM PDT 24 |
Finished | Jul 19 06:09:45 PM PDT 24 |
Peak memory | 334772 kb |
Host | smart-0d8518df-9a1c-4a39-968e-8959031f3611 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086756136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.2086756136 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.1440066137 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 842692289 ps |
CPU time | 79.48 seconds |
Started | Jul 19 06:07:31 PM PDT 24 |
Finished | Jul 19 06:08:52 PM PDT 24 |
Peak memory | 332604 kb |
Host | smart-dce619c6-90a1-4562-b7d0-0f534193be75 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440066137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.1440066137 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2620415196 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 34705028710 ps |
CPU time | 226.14 seconds |
Started | Jul 19 06:07:37 PM PDT 24 |
Finished | Jul 19 06:11:23 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-e1aa879e-c247-4c90-9604-9c863d32c84e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620415196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.2620415196 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.4002845693 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 343851357 ps |
CPU time | 3.34 seconds |
Started | Jul 19 06:07:36 PM PDT 24 |
Finished | Jul 19 06:07:40 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-b8b9280a-9e9c-448d-9bb4-6d18068e4db1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002845693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.4002845693 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.3619523852 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 32504846671 ps |
CPU time | 608.8 seconds |
Started | Jul 19 06:07:37 PM PDT 24 |
Finished | Jul 19 06:17:46 PM PDT 24 |
Peak memory | 360560 kb |
Host | smart-7a671ff4-a793-4817-95f2-74e386505b1c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619523852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3619523852 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.1925658388 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 2394947689 ps |
CPU time | 15.25 seconds |
Started | Jul 19 06:07:29 PM PDT 24 |
Finished | Jul 19 06:07:45 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-059c4cee-50da-4c6b-9ef1-2aef196629fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925658388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1925658388 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.3496506258 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 917952488174 ps |
CPU time | 6680.15 seconds |
Started | Jul 19 06:07:41 PM PDT 24 |
Finished | Jul 19 07:59:03 PM PDT 24 |
Peak memory | 374748 kb |
Host | smart-0be0adef-4ef4-4260-a20d-e007622d1564 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496506258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.3496506258 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2092272212 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 6535771905 ps |
CPU time | 59.24 seconds |
Started | Jul 19 06:07:38 PM PDT 24 |
Finished | Jul 19 06:08:38 PM PDT 24 |
Peak memory | 215048 kb |
Host | smart-b12c53d8-8b21-494e-9543-395d32ed455a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2092272212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2092272212 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.930997080 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 7470957387 ps |
CPU time | 267.78 seconds |
Started | Jul 19 06:07:29 PM PDT 24 |
Finished | Jul 19 06:11:58 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-7ba7a40a-2af3-4141-8ace-fd7cabb8ada3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930997080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_stress_pipeline.930997080 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1889516024 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 760988276 ps |
CPU time | 36.78 seconds |
Started | Jul 19 06:07:41 PM PDT 24 |
Finished | Jul 19 06:08:18 PM PDT 24 |
Peak memory | 279540 kb |
Host | smart-695e7945-4a7b-4e9a-bf9a-c3af61188d8c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889516024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.1889516024 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3120838985 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 9203001518 ps |
CPU time | 1173.74 seconds |
Started | Jul 19 06:07:53 PM PDT 24 |
Finished | Jul 19 06:27:31 PM PDT 24 |
Peak memory | 379764 kb |
Host | smart-a184740c-ed09-4443-b1d6-2986422462bb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120838985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.3120838985 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.670719838 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 35330510 ps |
CPU time | 0.65 seconds |
Started | Jul 19 06:07:52 PM PDT 24 |
Finished | Jul 19 06:07:56 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-fe8fd09b-b069-4d1f-88cc-a6b60a985053 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670719838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.670719838 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.946134802 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 172262753229 ps |
CPU time | 3109.5 seconds |
Started | Jul 19 06:07:46 PM PDT 24 |
Finished | Jul 19 06:59:36 PM PDT 24 |
Peak memory | 203584 kb |
Host | smart-35ed4bc9-b6e0-43d5-84dd-b3db26501308 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946134802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection. 946134802 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.2708932593 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 4747812311 ps |
CPU time | 39.45 seconds |
Started | Jul 19 06:07:53 PM PDT 24 |
Finished | Jul 19 06:08:36 PM PDT 24 |
Peak memory | 293428 kb |
Host | smart-05acea9e-0322-4fae-a92c-f59ba7d9c156 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708932593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.2708932593 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.1748055865 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 1792048322 ps |
CPU time | 11.34 seconds |
Started | Jul 19 06:07:53 PM PDT 24 |
Finished | Jul 19 06:08:08 PM PDT 24 |
Peak memory | 214596 kb |
Host | smart-9c242479-cf92-4d3f-a09c-69116614f6c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748055865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.1748055865 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.2147466063 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 726172876 ps |
CPU time | 30.01 seconds |
Started | Jul 19 06:07:44 PM PDT 24 |
Finished | Jul 19 06:08:15 PM PDT 24 |
Peak memory | 281608 kb |
Host | smart-a5a77a26-f96a-4902-a6ab-fdc08b182053 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147466063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2147466063 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1038190055 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 6290344504 ps |
CPU time | 123.93 seconds |
Started | Jul 19 06:07:52 PM PDT 24 |
Finished | Jul 19 06:09:59 PM PDT 24 |
Peak memory | 219156 kb |
Host | smart-ac9a047e-a7d2-4b1b-b47e-5ae34dfbb192 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038190055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.1038190055 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.4243286435 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 129187440717 ps |
CPU time | 361.14 seconds |
Started | Jul 19 06:07:53 PM PDT 24 |
Finished | Jul 19 06:13:57 PM PDT 24 |
Peak memory | 203960 kb |
Host | smart-f0f3def6-2986-486e-a53a-0072949e5685 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243286435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.4243286435 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.1861982537 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 8135361661 ps |
CPU time | 1185.02 seconds |
Started | Jul 19 06:07:43 PM PDT 24 |
Finished | Jul 19 06:27:29 PM PDT 24 |
Peak memory | 356260 kb |
Host | smart-06f49028-a9e0-4e00-b611-e780fad724ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861982537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.1861982537 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.4075377746 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 830402270 ps |
CPU time | 62.79 seconds |
Started | Jul 19 06:07:45 PM PDT 24 |
Finished | Jul 19 06:08:49 PM PDT 24 |
Peak memory | 305868 kb |
Host | smart-685a6e3f-e4cd-42eb-8a4d-8bb509029f4b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075377746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.4075377746 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1752419752 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 17781698061 ps |
CPU time | 549.16 seconds |
Started | Jul 19 06:07:46 PM PDT 24 |
Finished | Jul 19 06:16:56 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-b4bad1e3-0916-4f09-b3e4-0ec5d1a8fd67 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752419752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.1752419752 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.354205291 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 706405946 ps |
CPU time | 3.35 seconds |
Started | Jul 19 06:07:52 PM PDT 24 |
Finished | Jul 19 06:07:58 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-c841bea0-ae01-43d8-91b6-0d5c1e16f838 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354205291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.354205291 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.3620877645 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 1014737816 ps |
CPU time | 92.17 seconds |
Started | Jul 19 06:07:55 PM PDT 24 |
Finished | Jul 19 06:09:31 PM PDT 24 |
Peak memory | 351052 kb |
Host | smart-7f80e845-a33d-42a2-b267-ad8b64759a49 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620877645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3620877645 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.3869799518 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 3267914534 ps |
CPU time | 77.42 seconds |
Started | Jul 19 06:07:36 PM PDT 24 |
Finished | Jul 19 06:08:54 PM PDT 24 |
Peak memory | 333820 kb |
Host | smart-dc28559d-b9e7-427c-885c-4e8933c8ae5e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869799518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3869799518 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.707469362 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 74248860495 ps |
CPU time | 4204.58 seconds |
Started | Jul 19 06:07:52 PM PDT 24 |
Finished | Jul 19 07:18:00 PM PDT 24 |
Peak memory | 381508 kb |
Host | smart-2b4129e3-49e2-4ff4-928c-373090d3a673 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707469362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_stress_all.707469362 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1070455658 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1759686596 ps |
CPU time | 18.85 seconds |
Started | Jul 19 06:07:53 PM PDT 24 |
Finished | Jul 19 06:08:15 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-7417d80c-60c5-47e5-9ce6-b9957865f9c5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1070455658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1070455658 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.694911495 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 4151733572 ps |
CPU time | 271.45 seconds |
Started | Jul 19 06:07:46 PM PDT 24 |
Finished | Jul 19 06:12:19 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-b10bbdf7-38b7-4ca3-b0dc-f91b114380d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694911495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_stress_pipeline.694911495 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.4034190445 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 702034859 ps |
CPU time | 6.01 seconds |
Started | Jul 19 06:07:45 PM PDT 24 |
Finished | Jul 19 06:07:51 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-3161f361-d2cf-4172-a39a-4408aecccd3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034190445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.4034190445 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1256367917 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 191516361341 ps |
CPU time | 597.01 seconds |
Started | Jul 19 06:08:02 PM PDT 24 |
Finished | Jul 19 06:18:10 PM PDT 24 |
Peak memory | 378456 kb |
Host | smart-d84c9512-55d6-4d20-8f36-514e42071b3c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256367917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.1256367917 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.1536562467 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 19876735 ps |
CPU time | 0.69 seconds |
Started | Jul 19 06:07:58 PM PDT 24 |
Finished | Jul 19 06:08:04 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-3f33984c-0410-4132-8e0b-1b16574c36e8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536562467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.1536562467 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.3592911599 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 256201947828 ps |
CPU time | 2665.25 seconds |
Started | Jul 19 06:07:55 PM PDT 24 |
Finished | Jul 19 06:52:23 PM PDT 24 |
Peak memory | 203104 kb |
Host | smart-301d1461-cdfa-4738-aa74-2b5dc165b38f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592911599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .3592911599 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.2927317316 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 11583465352 ps |
CPU time | 1487.32 seconds |
Started | Jul 19 06:08:01 PM PDT 24 |
Finished | Jul 19 06:32:58 PM PDT 24 |
Peak memory | 378824 kb |
Host | smart-8c13212b-0971-4df7-ab30-ca4e002a7b7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927317316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.2927317316 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.2000847242 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 10230689144 ps |
CPU time | 62.41 seconds |
Started | Jul 19 06:08:01 PM PDT 24 |
Finished | Jul 19 06:09:13 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-e4b78c44-52a2-4121-b029-cf03a687e59e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000847242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.2000847242 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.72229601 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 1160654154 ps |
CPU time | 127.91 seconds |
Started | Jul 19 06:08:00 PM PDT 24 |
Finished | Jul 19 06:10:16 PM PDT 24 |
Peak memory | 368620 kb |
Host | smart-547a7f47-226f-45b2-bc4c-6436cf6b95c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72229601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 23.sram_ctrl_max_throughput.72229601 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.301101940 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 2011977598 ps |
CPU time | 66.04 seconds |
Started | Jul 19 06:08:00 PM PDT 24 |
Finished | Jul 19 06:09:15 PM PDT 24 |
Peak memory | 219140 kb |
Host | smart-e64f2803-a0bb-424e-87b7-3b47d90435e5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301101940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .sram_ctrl_mem_partial_access.301101940 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.360643546 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 21129998029 ps |
CPU time | 176.02 seconds |
Started | Jul 19 06:08:00 PM PDT 24 |
Finished | Jul 19 06:11:04 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-088521e5-cda3-42a9-87d5-df1213fae21d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360643546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _mem_walk.360643546 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.304825129 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 43506480507 ps |
CPU time | 1108.78 seconds |
Started | Jul 19 06:07:54 PM PDT 24 |
Finished | Jul 19 06:26:26 PM PDT 24 |
Peak memory | 370856 kb |
Host | smart-6874a917-bd20-489c-8fed-ba38b8eb0785 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304825129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip le_keys.304825129 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.3926829066 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 6425763148 ps |
CPU time | 50.69 seconds |
Started | Jul 19 06:07:52 PM PDT 24 |
Finished | Jul 19 06:08:46 PM PDT 24 |
Peak memory | 291176 kb |
Host | smart-06ef3b17-8f09-40db-95c9-569d2556c238 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926829066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.3926829066 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.297028391 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 44374790040 ps |
CPU time | 289.34 seconds |
Started | Jul 19 06:07:51 PM PDT 24 |
Finished | Jul 19 06:12:43 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-cf4cb4f7-ca5d-46f8-a8f3-409e8504a883 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297028391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.sram_ctrl_partial_access_b2b.297028391 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.2518625209 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 1406017732 ps |
CPU time | 3.27 seconds |
Started | Jul 19 06:07:59 PM PDT 24 |
Finished | Jul 19 06:08:09 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-f144fcd1-251a-487b-bcc9-1055ca327bfa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518625209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2518625209 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.2598445931 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 19469429176 ps |
CPU time | 21.57 seconds |
Started | Jul 19 06:08:04 PM PDT 24 |
Finished | Jul 19 06:08:39 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-db40bf85-91e5-4c41-b85e-c9bcb126096a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598445931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2598445931 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.104282251 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 3402541559 ps |
CPU time | 23.48 seconds |
Started | Jul 19 06:07:53 PM PDT 24 |
Finished | Jul 19 06:08:19 PM PDT 24 |
Peak memory | 203052 kb |
Host | smart-02d75ede-e220-42b4-9dfb-cc8b41836627 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104282251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.104282251 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.3962586797 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 82121544117 ps |
CPU time | 3878.91 seconds |
Started | Jul 19 06:08:00 PM PDT 24 |
Finished | Jul 19 07:12:48 PM PDT 24 |
Peak memory | 381864 kb |
Host | smart-01ca7602-424e-4e3d-91cf-b0a80dd8cac3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962586797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.3962586797 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1872500528 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 1628644410 ps |
CPU time | 60.08 seconds |
Started | Jul 19 06:08:02 PM PDT 24 |
Finished | Jul 19 06:09:13 PM PDT 24 |
Peak memory | 280572 kb |
Host | smart-569d4c2d-af3c-4143-9017-ba019bde0d74 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1872500528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1872500528 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3076793763 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 7668453588 ps |
CPU time | 234.6 seconds |
Started | Jul 19 06:07:53 PM PDT 24 |
Finished | Jul 19 06:11:51 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-9b9c0989-a4f0-4abb-9488-2bb762bf495e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076793763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3076793763 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3519958112 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 733554035 ps |
CPU time | 15.94 seconds |
Started | Jul 19 06:08:00 PM PDT 24 |
Finished | Jul 19 06:08:24 PM PDT 24 |
Peak memory | 251892 kb |
Host | smart-57e4838e-13aa-44f5-b8a1-7ae0a1cddef5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519958112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3519958112 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2466742986 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 9837642399 ps |
CPU time | 329.98 seconds |
Started | Jul 19 06:08:09 PM PDT 24 |
Finished | Jul 19 06:13:59 PM PDT 24 |
Peak memory | 334776 kb |
Host | smart-2d29e98d-f119-4e79-9adf-c516f8b0677b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466742986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.2466742986 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.4211918147 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 21013800 ps |
CPU time | 0.67 seconds |
Started | Jul 19 06:08:17 PM PDT 24 |
Finished | Jul 19 06:08:53 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-e6d65980-b9d4-4fcf-a36d-12822c7f5d55 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211918147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.4211918147 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.29056058 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 153848286526 ps |
CPU time | 1464.31 seconds |
Started | Jul 19 06:08:09 PM PDT 24 |
Finished | Jul 19 06:32:54 PM PDT 24 |
Peak memory | 203488 kb |
Host | smart-1f50df45-58cb-49a2-bf45-78006fe20406 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29056058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.29056058 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.3174972757 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 43420813394 ps |
CPU time | 845.92 seconds |
Started | Jul 19 06:08:08 PM PDT 24 |
Finished | Jul 19 06:22:33 PM PDT 24 |
Peak memory | 372584 kb |
Host | smart-97535e0b-407b-4428-8840-129249f1c01e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174972757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.3174972757 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.1407272525 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 3889716053 ps |
CPU time | 26.32 seconds |
Started | Jul 19 06:08:07 PM PDT 24 |
Finished | Jul 19 06:08:53 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-ee885648-571e-4407-bad4-265bc558202f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407272525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.1407272525 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.376145848 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 4818127625 ps |
CPU time | 50.51 seconds |
Started | Jul 19 06:08:07 PM PDT 24 |
Finished | Jul 19 06:09:17 PM PDT 24 |
Peak memory | 296732 kb |
Host | smart-22c462fe-b35b-4f59-8f5d-79eb1ef9616e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376145848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.sram_ctrl_max_throughput.376145848 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.1466153767 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 10369109119 ps |
CPU time | 87.73 seconds |
Started | Jul 19 06:08:17 PM PDT 24 |
Finished | Jul 19 06:10:20 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-11bfdc30-2c59-46a0-b048-fe740df7de89 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466153767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.1466153767 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2187443115 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 23171293941 ps |
CPU time | 266.17 seconds |
Started | Jul 19 06:08:08 PM PDT 24 |
Finished | Jul 19 06:12:55 PM PDT 24 |
Peak memory | 212160 kb |
Host | smart-de0caeff-a7d5-42d3-9745-9c588d2d5032 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187443115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2187443115 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.967595731 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 3220728673 ps |
CPU time | 551.49 seconds |
Started | Jul 19 06:07:59 PM PDT 24 |
Finished | Jul 19 06:17:16 PM PDT 24 |
Peak memory | 371748 kb |
Host | smart-9cd5863c-7b61-404e-a4a0-842910bcafef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967595731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multip le_keys.967595731 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.390713267 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 1055945852 ps |
CPU time | 13.12 seconds |
Started | Jul 19 06:08:09 PM PDT 24 |
Finished | Jul 19 06:08:42 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-55e706b2-7957-4825-a1f1-1d447c0297f0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390713267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s ram_ctrl_partial_access.390713267 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3756834372 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 17457256391 ps |
CPU time | 223.12 seconds |
Started | Jul 19 06:08:08 PM PDT 24 |
Finished | Jul 19 06:12:10 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-a7d4d74b-7888-4468-8476-460e42c1e587 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756834372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.3756834372 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.3047955272 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 353698109 ps |
CPU time | 3.03 seconds |
Started | Jul 19 06:08:10 PM PDT 24 |
Finished | Jul 19 06:08:34 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-06c3dabf-1fa0-4d3b-ba8c-3b6d8d80423e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047955272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3047955272 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.2691797610 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 5214940442 ps |
CPU time | 648.5 seconds |
Started | Jul 19 06:08:08 PM PDT 24 |
Finished | Jul 19 06:19:18 PM PDT 24 |
Peak memory | 375532 kb |
Host | smart-15b585cc-cdfc-47ee-98e9-bca9493a1df0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691797610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2691797610 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.2046299130 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 6396419793 ps |
CPU time | 20.77 seconds |
Started | Jul 19 06:07:59 PM PDT 24 |
Finished | Jul 19 06:08:26 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-9490e2e0-09b6-4364-b209-ed6065d1b790 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046299130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2046299130 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.701812834 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 558642289230 ps |
CPU time | 7409.98 seconds |
Started | Jul 19 06:08:18 PM PDT 24 |
Finished | Jul 19 08:12:25 PM PDT 24 |
Peak memory | 381872 kb |
Host | smart-cdceb52d-7aa3-459c-9006-40e16b14adab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701812834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_stress_all.701812834 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2804568098 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 3888403515 ps |
CPU time | 11.21 seconds |
Started | Jul 19 06:08:16 PM PDT 24 |
Finished | Jul 19 06:09:02 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-5a77114d-8039-4d03-9ddd-1669896d4262 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2804568098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2804568098 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2679295597 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 8979251253 ps |
CPU time | 277.19 seconds |
Started | Jul 19 06:08:08 PM PDT 24 |
Finished | Jul 19 06:13:06 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-41355c4f-421c-4ed3-9223-f9c03874f019 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679295597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.2679295597 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1163520761 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 3044235351 ps |
CPU time | 48.18 seconds |
Started | Jul 19 06:08:08 PM PDT 24 |
Finished | Jul 19 06:09:16 PM PDT 24 |
Peak memory | 288776 kb |
Host | smart-5945535f-6846-4892-aa0b-b52e4769a8e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163520761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1163520761 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2707797929 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 46160324935 ps |
CPU time | 785.37 seconds |
Started | Jul 19 06:08:24 PM PDT 24 |
Finished | Jul 19 06:22:09 PM PDT 24 |
Peak memory | 379796 kb |
Host | smart-eafb524f-0b61-47b2-968b-2f1bf83abe37 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707797929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2707797929 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.749276269 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 119706458 ps |
CPU time | 0.7 seconds |
Started | Jul 19 06:08:23 PM PDT 24 |
Finished | Jul 19 06:09:03 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-ff781f3d-054b-4e7b-8f00-d584a2bc3290 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749276269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.749276269 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.1728854880 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 111629546435 ps |
CPU time | 2170.77 seconds |
Started | Jul 19 06:08:17 PM PDT 24 |
Finished | Jul 19 06:45:03 PM PDT 24 |
Peak memory | 203864 kb |
Host | smart-55f6268a-2412-4e3f-b367-f11d95719d8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728854880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .1728854880 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.1932567871 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 62877790978 ps |
CPU time | 776.52 seconds |
Started | Jul 19 06:08:24 PM PDT 24 |
Finished | Jul 19 06:21:59 PM PDT 24 |
Peak memory | 375668 kb |
Host | smart-f81973c0-7eeb-4ccc-ba1c-638ae181b0b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932567871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.1932567871 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.2637869137 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 8894321235 ps |
CPU time | 58.61 seconds |
Started | Jul 19 06:08:25 PM PDT 24 |
Finished | Jul 19 06:10:02 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-1d139896-94c8-4d42-b76c-8c7778a962df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637869137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.2637869137 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.2086265408 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 3180797974 ps |
CPU time | 156.07 seconds |
Started | Jul 19 06:08:24 PM PDT 24 |
Finished | Jul 19 06:11:39 PM PDT 24 |
Peak memory | 371588 kb |
Host | smart-36076e97-6e4a-4e85-a116-0bfd99580c02 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086265408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.2086265408 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3806398993 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 2513501674 ps |
CPU time | 141.1 seconds |
Started | Jul 19 06:08:25 PM PDT 24 |
Finished | Jul 19 06:11:25 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-e0696c2c-628c-4629-b58f-77e61bc25cae |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806398993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.3806398993 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.3231868875 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 7280672701 ps |
CPU time | 152.65 seconds |
Started | Jul 19 06:08:25 PM PDT 24 |
Finished | Jul 19 06:11:36 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-eaa69518-8348-494d-8570-23376e8b8108 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231868875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.3231868875 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.1126095950 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 25522516857 ps |
CPU time | 1052.13 seconds |
Started | Jul 19 06:08:16 PM PDT 24 |
Finished | Jul 19 06:26:23 PM PDT 24 |
Peak memory | 374692 kb |
Host | smart-9b7a861e-77c8-4c2a-8f3d-087e756889cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126095950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.1126095950 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.3545352955 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 676563082 ps |
CPU time | 6.08 seconds |
Started | Jul 19 06:08:17 PM PDT 24 |
Finished | Jul 19 06:08:58 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-b7e503cf-22da-42ba-bc27-76004d77bc89 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545352955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3545352955 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.2443211990 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 1473030719 ps |
CPU time | 3.58 seconds |
Started | Jul 19 06:08:24 PM PDT 24 |
Finished | Jul 19 06:09:06 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-c5ca7164-5a42-49ed-a116-9b6b9765d187 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443211990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2443211990 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.938369822 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 6081697506 ps |
CPU time | 329.79 seconds |
Started | Jul 19 06:08:23 PM PDT 24 |
Finished | Jul 19 06:14:32 PM PDT 24 |
Peak memory | 373712 kb |
Host | smart-90cfde29-04e4-4a64-92ca-f0857e9bb089 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938369822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.938369822 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.3784883810 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 403163435 ps |
CPU time | 4.17 seconds |
Started | Jul 19 06:08:17 PM PDT 24 |
Finished | Jul 19 06:08:57 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-88bb9aaf-4b65-4126-9e59-26f0e0251304 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784883810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3784883810 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.448345875 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 57161028552 ps |
CPU time | 1174.55 seconds |
Started | Jul 19 06:08:25 PM PDT 24 |
Finished | Jul 19 06:28:38 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-3619d5da-3748-4486-845c-433dcce1fe4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448345875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_stress_all.448345875 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4100895587 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 279534740 ps |
CPU time | 9 seconds |
Started | Jul 19 06:08:25 PM PDT 24 |
Finished | Jul 19 06:09:13 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-227838c0-a620-43e0-8975-5e02e063c956 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4100895587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.4100895587 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2701215616 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 25179164916 ps |
CPU time | 409.61 seconds |
Started | Jul 19 06:08:18 PM PDT 24 |
Finished | Jul 19 06:15:43 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-c9f9da64-a498-4fbd-97ae-e5f5936700c5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701215616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.2701215616 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.390793193 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 3549180157 ps |
CPU time | 167.9 seconds |
Started | Jul 19 06:08:25 PM PDT 24 |
Finished | Jul 19 06:11:52 PM PDT 24 |
Peak memory | 370888 kb |
Host | smart-9d9ecd92-de84-4865-90df-3d33eced5bdb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390793193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.390793193 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2234769596 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 16114614453 ps |
CPU time | 1393.62 seconds |
Started | Jul 19 06:08:39 PM PDT 24 |
Finished | Jul 19 06:32:32 PM PDT 24 |
Peak memory | 379776 kb |
Host | smart-3ff0fa4f-eb93-40f4-8039-3652166d69d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234769596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.2234769596 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.1649209653 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 14566573 ps |
CPU time | 0.67 seconds |
Started | Jul 19 06:08:47 PM PDT 24 |
Finished | Jul 19 06:09:23 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-fd0a364b-9249-4b45-99e1-15c0e40c11a4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649209653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.1649209653 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.3168644308 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 78349925712 ps |
CPU time | 1957.42 seconds |
Started | Jul 19 06:08:25 PM PDT 24 |
Finished | Jul 19 06:41:41 PM PDT 24 |
Peak memory | 203456 kb |
Host | smart-6c5b4f6d-2864-4f9d-acc1-0ef55991aba4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168644308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .3168644308 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.865814580 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 85921787072 ps |
CPU time | 1106.88 seconds |
Started | Jul 19 06:08:38 PM PDT 24 |
Finished | Jul 19 06:27:45 PM PDT 24 |
Peak memory | 368532 kb |
Host | smart-f172ee6b-f1a6-490e-a697-a641af6e3da1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865814580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.865814580 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.3774622104 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 6318064577 ps |
CPU time | 41.53 seconds |
Started | Jul 19 06:08:35 PM PDT 24 |
Finished | Jul 19 06:09:56 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-f4bc9a07-1269-41fd-bbb0-a06736a191e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774622104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es calation.3774622104 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.90717613 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 703731820 ps |
CPU time | 6.19 seconds |
Started | Jul 19 06:08:34 PM PDT 24 |
Finished | Jul 19 06:09:20 PM PDT 24 |
Peak memory | 210972 kb |
Host | smart-f16f3a05-34f5-40bd-b2bc-21f9f8ac8313 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90717613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 26.sram_ctrl_max_throughput.90717613 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.39567606 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 10695092803 ps |
CPU time | 91.04 seconds |
Started | Jul 19 06:08:46 PM PDT 24 |
Finished | Jul 19 06:10:53 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-97c5f326-d635-468b-9be8-027d0598bb77 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39567606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_mem_partial_access.39567606 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.3151483626 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 3986027830 ps |
CPU time | 261.11 seconds |
Started | Jul 19 06:08:38 PM PDT 24 |
Finished | Jul 19 06:13:38 PM PDT 24 |
Peak memory | 211196 kb |
Host | smart-a7a81b38-369f-44d2-8df4-b7d8c45dd5f6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151483626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3151483626 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.3360783575 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 40311610374 ps |
CPU time | 850.87 seconds |
Started | Jul 19 06:08:25 PM PDT 24 |
Finished | Jul 19 06:23:15 PM PDT 24 |
Peak memory | 377112 kb |
Host | smart-987542a1-61c7-4420-aa3f-f3f45a848a19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360783575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.3360783575 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.3458108752 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 720761595 ps |
CPU time | 3.9 seconds |
Started | Jul 19 06:08:35 PM PDT 24 |
Finished | Jul 19 06:09:19 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-6df1e6f5-1095-4286-af72-671933c39ab9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458108752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.3458108752 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1755306818 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 27618689876 ps |
CPU time | 346.91 seconds |
Started | Jul 19 06:08:32 PM PDT 24 |
Finished | Jul 19 06:14:59 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-b2d4c7a7-0bcd-4508-848f-28fe4e445ca2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755306818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.1755306818 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.1738595836 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 354825764 ps |
CPU time | 3.55 seconds |
Started | Jul 19 06:08:42 PM PDT 24 |
Finished | Jul 19 06:09:24 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-984932fb-3fda-49f9-a4bb-4d3ec7d35b8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738595836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1738595836 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.688197729 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 7731452865 ps |
CPU time | 404.96 seconds |
Started | Jul 19 06:08:38 PM PDT 24 |
Finished | Jul 19 06:16:02 PM PDT 24 |
Peak memory | 344192 kb |
Host | smart-3df8d805-f9f8-422d-b80c-99aec367fbea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688197729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.688197729 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.1119493591 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 7273984522 ps |
CPU time | 20.2 seconds |
Started | Jul 19 06:08:23 PM PDT 24 |
Finished | Jul 19 06:09:22 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-189820d2-d147-47f0-8360-f3a577c906f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119493591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1119493591 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.873317251 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 81762620309 ps |
CPU time | 5070.14 seconds |
Started | Jul 19 06:08:47 PM PDT 24 |
Finished | Jul 19 07:33:53 PM PDT 24 |
Peak memory | 382932 kb |
Host | smart-2103d88f-71ab-43fa-9643-9f4341381ed6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873317251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_stress_all.873317251 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1144600734 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 2761297641 ps |
CPU time | 14.3 seconds |
Started | Jul 19 06:08:48 PM PDT 24 |
Finished | Jul 19 06:09:37 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-2b096642-cc00-4abc-9809-1323082bbf4d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1144600734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1144600734 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.116381033 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 3278383885 ps |
CPU time | 247.65 seconds |
Started | Jul 19 06:08:24 PM PDT 24 |
Finished | Jul 19 06:13:10 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-0ebc45d4-02f4-4344-be8f-18b9aaef2595 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116381033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_stress_pipeline.116381033 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2034024715 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 793434797 ps |
CPU time | 131.45 seconds |
Started | Jul 19 06:08:33 PM PDT 24 |
Finished | Jul 19 06:11:24 PM PDT 24 |
Peak memory | 372552 kb |
Host | smart-e04aeefa-9ac9-4c40-a981-368d3e5cc805 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034024715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2034024715 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3427818910 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 18896157893 ps |
CPU time | 1406.58 seconds |
Started | Jul 19 06:08:57 PM PDT 24 |
Finished | Jul 19 06:32:52 PM PDT 24 |
Peak memory | 378756 kb |
Host | smart-d5095b0c-8f8f-4e53-b278-6e1ae5cf2bad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427818910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.3427818910 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.3780149980 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 46606142 ps |
CPU time | 0.65 seconds |
Started | Jul 19 06:09:03 PM PDT 24 |
Finished | Jul 19 06:09:27 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-aa0a2d9a-98a5-466d-ac1b-938c079af032 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780149980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3780149980 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.105043532 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 94563667209 ps |
CPU time | 1732.74 seconds |
Started | Jul 19 06:08:47 PM PDT 24 |
Finished | Jul 19 06:38:15 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-cafb1c32-f5f6-4b1b-8406-00b91d5a38ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105043532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection. 105043532 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.1018446765 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 2215334042 ps |
CPU time | 57.13 seconds |
Started | Jul 19 06:08:55 PM PDT 24 |
Finished | Jul 19 06:10:22 PM PDT 24 |
Peak memory | 265172 kb |
Host | smart-173bb760-3380-4aca-852d-5156e3da423e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018446765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.1018446765 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.3290720033 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 14040392194 ps |
CPU time | 68.93 seconds |
Started | Jul 19 06:08:47 PM PDT 24 |
Finished | Jul 19 06:10:31 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-8da7efa5-375b-4253-982b-0e4f908caf3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290720033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.3290720033 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.3512932240 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 2878790447 ps |
CPU time | 13.81 seconds |
Started | Jul 19 06:08:46 PM PDT 24 |
Finished | Jul 19 06:09:36 PM PDT 24 |
Peak memory | 243752 kb |
Host | smart-0e0f5ecd-0136-4ecb-ae03-8a2fad78ed47 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512932240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.3512932240 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.4269934789 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 19906278419 ps |
CPU time | 129.39 seconds |
Started | Jul 19 06:08:54 PM PDT 24 |
Finished | Jul 19 06:11:34 PM PDT 24 |
Peak memory | 211584 kb |
Host | smart-2e61be13-f4d7-4bea-9ada-70f26778419d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269934789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.4269934789 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.1271824069 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 206485818119 ps |
CPU time | 219.67 seconds |
Started | Jul 19 06:08:59 PM PDT 24 |
Finished | Jul 19 06:13:06 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-0477e15d-94f4-42fe-8c65-873dd080cb07 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271824069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.1271824069 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.815472063 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 13661471398 ps |
CPU time | 758.98 seconds |
Started | Jul 19 06:08:46 PM PDT 24 |
Finished | Jul 19 06:22:01 PM PDT 24 |
Peak memory | 378768 kb |
Host | smart-4c18e57a-391d-41a8-a928-16a90bb94388 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815472063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip le_keys.815472063 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.686391327 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 1445092572 ps |
CPU time | 4.7 seconds |
Started | Jul 19 06:08:50 PM PDT 24 |
Finished | Jul 19 06:09:28 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-a1e2a569-c9f7-4501-b8de-ec61a76cf11b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686391327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s ram_ctrl_partial_access.686391327 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1374527913 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 51181612700 ps |
CPU time | 652.61 seconds |
Started | Jul 19 06:08:48 PM PDT 24 |
Finished | Jul 19 06:20:15 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-4e34784c-8ff7-4d68-8f16-e487e41da5d6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374527913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.1374527913 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.2633003144 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 358596706 ps |
CPU time | 3.33 seconds |
Started | Jul 19 06:09:01 PM PDT 24 |
Finished | Jul 19 06:09:30 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-95ae8fe3-3c05-4aae-9151-3f6ca4cc4f5b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633003144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2633003144 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.2012107607 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 12394113913 ps |
CPU time | 933.94 seconds |
Started | Jul 19 06:08:54 PM PDT 24 |
Finished | Jul 19 06:24:59 PM PDT 24 |
Peak memory | 379752 kb |
Host | smart-880cf6cc-988f-4a08-8f67-d86834ff9552 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012107607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2012107607 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.1985003001 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 493109925 ps |
CPU time | 5.61 seconds |
Started | Jul 19 06:08:48 PM PDT 24 |
Finished | Jul 19 06:09:28 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-08ebb0b6-bdcf-43e9-a8fa-442e90fbddf2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985003001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1985003001 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.3771105281 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 309837404595 ps |
CPU time | 9470.84 seconds |
Started | Jul 19 06:09:05 PM PDT 24 |
Finished | Jul 19 08:47:19 PM PDT 24 |
Peak memory | 381788 kb |
Host | smart-83703493-0f2e-473c-819b-f7a8639ca4dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771105281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.3771105281 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.542246905 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 638771935 ps |
CPU time | 20.31 seconds |
Started | Jul 19 06:09:01 PM PDT 24 |
Finished | Jul 19 06:09:47 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-ea2e711f-8de6-42d0-8018-f1db56079104 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=542246905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.542246905 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3288135340 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 6375982801 ps |
CPU time | 345.38 seconds |
Started | Jul 19 06:08:47 PM PDT 24 |
Finished | Jul 19 06:15:08 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-83217c96-f84f-4a2c-9cf0-54701084e2d6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288135340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.3288135340 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1062386068 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 944050899 ps |
CPU time | 77.27 seconds |
Started | Jul 19 06:08:46 PM PDT 24 |
Finished | Jul 19 06:10:40 PM PDT 24 |
Peak memory | 327732 kb |
Host | smart-d29570bc-21c4-4ff7-bab4-f1030c9a4815 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062386068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1062386068 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.944391775 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 7769653118 ps |
CPU time | 678.24 seconds |
Started | Jul 19 06:09:09 PM PDT 24 |
Finished | Jul 19 06:20:46 PM PDT 24 |
Peak memory | 373604 kb |
Host | smart-211ac1d2-8e6c-443e-b983-41498d27a833 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944391775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 28.sram_ctrl_access_during_key_req.944391775 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.1931021220 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 40406577 ps |
CPU time | 0.65 seconds |
Started | Jul 19 06:09:19 PM PDT 24 |
Finished | Jul 19 06:09:29 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-8bb0a514-7a12-4f61-893d-fbeaed93a476 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931021220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1931021220 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.2768313829 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 84395385080 ps |
CPU time | 670.75 seconds |
Started | Jul 19 06:09:01 PM PDT 24 |
Finished | Jul 19 06:20:37 PM PDT 24 |
Peak memory | 203600 kb |
Host | smart-25276911-89bd-4319-a0dd-d4aa742f9da0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768313829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .2768313829 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.117986672 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 34602288372 ps |
CPU time | 316.34 seconds |
Started | Jul 19 06:09:12 PM PDT 24 |
Finished | Jul 19 06:14:44 PM PDT 24 |
Peak memory | 377444 kb |
Host | smart-f2ecce0e-296e-44aa-a469-fecae13ef9f1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117986672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executabl e.117986672 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.4258027572 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 2276481556 ps |
CPU time | 15.21 seconds |
Started | Jul 19 06:09:09 PM PDT 24 |
Finished | Jul 19 06:09:43 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-7e79dc8a-228d-42cb-bf97-c8bd5a68cdc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258027572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.4258027572 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.4287785399 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 3058455381 ps |
CPU time | 51.27 seconds |
Started | Jul 19 06:09:02 PM PDT 24 |
Finished | Jul 19 06:10:18 PM PDT 24 |
Peak memory | 314344 kb |
Host | smart-1a5d1f24-5ab7-400c-94e3-bf0671eccddd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287785399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.4287785399 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2240092575 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 10501115999 ps |
CPU time | 172.28 seconds |
Started | Jul 19 06:09:17 PM PDT 24 |
Finished | Jul 19 06:12:20 PM PDT 24 |
Peak memory | 219264 kb |
Host | smart-742abe46-ffa1-4381-b01c-5f37ae671dd2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240092575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.2240092575 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.1195014924 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 7882049266 ps |
CPU time | 259.13 seconds |
Started | Jul 19 06:09:17 PM PDT 24 |
Finished | Jul 19 06:13:47 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-cceaf422-a4f7-484e-9f5e-7401a1c8577d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195014924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.1195014924 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.2199069114 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 12910572974 ps |
CPU time | 216.62 seconds |
Started | Jul 19 06:09:04 PM PDT 24 |
Finished | Jul 19 06:13:03 PM PDT 24 |
Peak memory | 378436 kb |
Host | smart-45f13af1-c2ed-4188-ab7b-01a173ef6895 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199069114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.2199069114 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.3538840378 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 17843771711 ps |
CPU time | 19.6 seconds |
Started | Jul 19 06:09:05 PM PDT 24 |
Finished | Jul 19 06:09:46 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-15fa7a75-4e57-4c37-8130-9b36bad01c4e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538840378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.3538840378 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1499199018 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 10708084822 ps |
CPU time | 292.42 seconds |
Started | Jul 19 06:09:04 PM PDT 24 |
Finished | Jul 19 06:14:19 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-8d736fe9-34e0-413b-8726-6ccd38f878f6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499199018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.1499199018 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.1124104307 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 3726437402 ps |
CPU time | 3.79 seconds |
Started | Jul 19 06:09:10 PM PDT 24 |
Finished | Jul 19 06:09:31 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-f61d0170-0a43-4ce4-a63f-f6be6cb2cce3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124104307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1124104307 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.1447702590 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 122214481600 ps |
CPU time | 1365.43 seconds |
Started | Jul 19 06:09:09 PM PDT 24 |
Finished | Jul 19 06:32:13 PM PDT 24 |
Peak memory | 380812 kb |
Host | smart-c5046173-9968-42f4-9564-6d8d9c85adc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447702590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1447702590 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.4269170401 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 581011487 ps |
CPU time | 3.8 seconds |
Started | Jul 19 06:09:03 PM PDT 24 |
Finished | Jul 19 06:09:30 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-6b4c28c9-9df8-406f-a7f6-7f7598f788b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269170401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.4269170401 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.3411946158 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 570697215921 ps |
CPU time | 7109.01 seconds |
Started | Jul 19 06:09:18 PM PDT 24 |
Finished | Jul 19 08:07:58 PM PDT 24 |
Peak memory | 340396 kb |
Host | smart-27cd3b5b-7cf7-41a2-b84b-1f930bad06d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411946158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.3411946158 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1343767688 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 711751666 ps |
CPU time | 18.62 seconds |
Started | Jul 19 06:09:21 PM PDT 24 |
Finished | Jul 19 06:09:47 PM PDT 24 |
Peak memory | 217660 kb |
Host | smart-20077541-1e48-4804-95eb-e26527ff8d90 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1343767688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1343767688 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3161071741 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 7086805163 ps |
CPU time | 222.28 seconds |
Started | Jul 19 06:09:02 PM PDT 24 |
Finished | Jul 19 06:13:09 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-2338dd78-d9a9-4c73-a48d-5eb96fa8f8c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161071741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.3161071741 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3311512966 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 743796263 ps |
CPU time | 9.94 seconds |
Started | Jul 19 06:09:12 PM PDT 24 |
Finished | Jul 19 06:09:38 PM PDT 24 |
Peak memory | 227404 kb |
Host | smart-6d1a78d4-25ea-4d37-b5e2-81389893ee18 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311512966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.3311512966 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2433495847 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 60409623924 ps |
CPU time | 1477.72 seconds |
Started | Jul 19 06:09:32 PM PDT 24 |
Finished | Jul 19 06:34:10 PM PDT 24 |
Peak memory | 379816 kb |
Host | smart-0a8a9aae-3f3b-40a5-b7f7-55b9f324656c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433495847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.2433495847 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.1428206602 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 14892089 ps |
CPU time | 0.65 seconds |
Started | Jul 19 06:09:32 PM PDT 24 |
Finished | Jul 19 06:09:33 PM PDT 24 |
Peak memory | 202288 kb |
Host | smart-7c190837-f833-4a72-b26a-b49ab46ef383 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428206602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1428206602 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.2681552897 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 422302471774 ps |
CPU time | 2380.1 seconds |
Started | Jul 19 06:09:19 PM PDT 24 |
Finished | Jul 19 06:49:09 PM PDT 24 |
Peak memory | 203000 kb |
Host | smart-62e1a21b-5806-4e1f-9676-d611df64229d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681552897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .2681552897 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.777229115 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 30018416772 ps |
CPU time | 35.93 seconds |
Started | Jul 19 06:09:26 PM PDT 24 |
Finished | Jul 19 06:10:05 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-9b5cf9e1-56ef-465d-8929-a81f0d8b8320 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777229115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_esc alation.777229115 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.3262067250 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 800427620 ps |
CPU time | 163.24 seconds |
Started | Jul 19 06:09:25 PM PDT 24 |
Finished | Jul 19 06:12:12 PM PDT 24 |
Peak memory | 370564 kb |
Host | smart-87b67880-e558-4932-86cc-a8ed5728d5ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262067250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.3262067250 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.4178117526 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 2544821054 ps |
CPU time | 79.21 seconds |
Started | Jul 19 06:09:31 PM PDT 24 |
Finished | Jul 19 06:10:51 PM PDT 24 |
Peak memory | 219276 kb |
Host | smart-ff5ebe93-90bc-4bc6-b19f-7b14944f1792 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178117526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.4178117526 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.3077998875 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 10625103195 ps |
CPU time | 189.2 seconds |
Started | Jul 19 06:09:32 PM PDT 24 |
Finished | Jul 19 06:12:42 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-75658462-d325-4b70-a1d7-298bb99d86a4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077998875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.3077998875 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.349311773 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 335253797771 ps |
CPU time | 1394.6 seconds |
Started | Jul 19 06:09:19 PM PDT 24 |
Finished | Jul 19 06:32:43 PM PDT 24 |
Peak memory | 381868 kb |
Host | smart-cb0d7acf-0848-4738-a3e0-fe7f0c34fd5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349311773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip le_keys.349311773 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.3425277880 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 1789926026 ps |
CPU time | 21.25 seconds |
Started | Jul 19 06:09:26 PM PDT 24 |
Finished | Jul 19 06:09:50 PM PDT 24 |
Peak memory | 254312 kb |
Host | smart-e8ee2d28-c8ba-41fa-853d-85fa551a04ab |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425277880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.3425277880 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1319115490 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 126244948263 ps |
CPU time | 473.44 seconds |
Started | Jul 19 06:09:26 PM PDT 24 |
Finished | Jul 19 06:17:23 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-5b64e857-7c20-4eb4-a562-5d735d93c4a5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319115490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1319115490 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.688152085 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 1803370681 ps |
CPU time | 3.37 seconds |
Started | Jul 19 06:09:32 PM PDT 24 |
Finished | Jul 19 06:09:36 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-987168a6-d519-419d-9ba5-cf82b806f378 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688152085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.688152085 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.3201914351 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 5371543481 ps |
CPU time | 579.12 seconds |
Started | Jul 19 06:09:30 PM PDT 24 |
Finished | Jul 19 06:19:10 PM PDT 24 |
Peak memory | 377276 kb |
Host | smart-8ddf11c9-6e73-4d5c-be21-ef768b7b4ccc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201914351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3201914351 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.2717178777 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 2047493489 ps |
CPU time | 80.3 seconds |
Started | Jul 19 06:09:21 PM PDT 24 |
Finished | Jul 19 06:10:49 PM PDT 24 |
Peak memory | 346992 kb |
Host | smart-3a489388-4462-4feb-8e04-32c88ffbf2d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717178777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2717178777 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.3613019800 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 115093649534 ps |
CPU time | 4160.89 seconds |
Started | Jul 19 06:09:32 PM PDT 24 |
Finished | Jul 19 07:18:55 PM PDT 24 |
Peak memory | 380824 kb |
Host | smart-5a1a947c-3884-4cfa-9e56-b49e1d878285 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613019800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.3613019800 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3944317540 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 801842902 ps |
CPU time | 21.14 seconds |
Started | Jul 19 06:09:31 PM PDT 24 |
Finished | Jul 19 06:09:53 PM PDT 24 |
Peak memory | 212888 kb |
Host | smart-2845309a-a902-4e7c-a2a4-84d53847c3b7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3944317540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.3944317540 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.452222060 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 17922385227 ps |
CPU time | 240 seconds |
Started | Jul 19 06:09:24 PM PDT 24 |
Finished | Jul 19 06:13:29 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-276bcd41-b5a7-44f6-ab4c-c88cb82f6529 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452222060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29 .sram_ctrl_stress_pipeline.452222060 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3722467597 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 3140500850 ps |
CPU time | 86.89 seconds |
Started | Jul 19 06:09:25 PM PDT 24 |
Finished | Jul 19 06:10:56 PM PDT 24 |
Peak memory | 329720 kb |
Host | smart-04fce905-bd44-49dc-8a9a-f98698b48958 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722467597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3722467597 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1843820253 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 25902950546 ps |
CPU time | 265.09 seconds |
Started | Jul 19 06:04:14 PM PDT 24 |
Finished | Jul 19 06:08:40 PM PDT 24 |
Peak memory | 379708 kb |
Host | smart-312be8e9-97b8-4fb2-bfbc-86dddf1491e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843820253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.1843820253 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.2766260959 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 32941515 ps |
CPU time | 0.67 seconds |
Started | Jul 19 06:04:16 PM PDT 24 |
Finished | Jul 19 06:04:17 PM PDT 24 |
Peak memory | 202488 kb |
Host | smart-a3491694-aa38-49af-89e0-f398200ccfea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766260959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2766260959 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.3414939087 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 211659288595 ps |
CPU time | 2577.73 seconds |
Started | Jul 19 06:04:12 PM PDT 24 |
Finished | Jul 19 06:47:12 PM PDT 24 |
Peak memory | 203384 kb |
Host | smart-4f5791cf-f836-4dac-9786-3453b27c278d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414939087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 3414939087 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.1204469800 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 31271213164 ps |
CPU time | 1220.82 seconds |
Started | Jul 19 06:04:14 PM PDT 24 |
Finished | Jul 19 06:24:36 PM PDT 24 |
Peak memory | 378800 kb |
Host | smart-4d5a186e-d40c-498a-8681-f3dd882f3f08 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204469800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.1204469800 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.2809505617 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 7102847785 ps |
CPU time | 41.05 seconds |
Started | Jul 19 06:04:14 PM PDT 24 |
Finished | Jul 19 06:04:56 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-a2f1872a-6b08-4cc9-86f8-ee82499ac237 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809505617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.2809505617 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.3237641234 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 1457281887 ps |
CPU time | 39.64 seconds |
Started | Jul 19 06:04:17 PM PDT 24 |
Finished | Jul 19 06:04:57 PM PDT 24 |
Peak memory | 279484 kb |
Host | smart-91861a9e-8873-4c51-a3c3-765fb0b21134 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237641234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.3237641234 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3210350787 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 9382058657 ps |
CPU time | 79.87 seconds |
Started | Jul 19 06:04:16 PM PDT 24 |
Finished | Jul 19 06:05:36 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-db471c19-8b0a-4656-ad67-97c8af4a6c0e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210350787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_mem_partial_access.3210350787 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.2871980428 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 29476881029 ps |
CPU time | 340.82 seconds |
Started | Jul 19 06:04:17 PM PDT 24 |
Finished | Jul 19 06:09:59 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-75ace04d-2f72-4ac7-89b2-92b4204ae437 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871980428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.2871980428 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.475403174 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 19849223445 ps |
CPU time | 920.08 seconds |
Started | Jul 19 06:04:09 PM PDT 24 |
Finished | Jul 19 06:19:30 PM PDT 24 |
Peak memory | 376780 kb |
Host | smart-4b6eafe1-759c-4238-b246-f2cc764c92cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475403174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl e_keys.475403174 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.330340333 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 844549656 ps |
CPU time | 14.97 seconds |
Started | Jul 19 06:04:14 PM PDT 24 |
Finished | Jul 19 06:04:30 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-09877e20-95a0-4366-a067-4f8c7a6620e5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330340333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr am_ctrl_partial_access.330340333 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3761441240 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 71039535835 ps |
CPU time | 212.31 seconds |
Started | Jul 19 06:04:15 PM PDT 24 |
Finished | Jul 19 06:07:48 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-573f2452-0009-4a90-b138-76f526368f2a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761441240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.3761441240 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.4178461525 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 344532786 ps |
CPU time | 3.53 seconds |
Started | Jul 19 06:04:15 PM PDT 24 |
Finished | Jul 19 06:04:19 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-9f54aefb-59f3-4f60-8e44-fe555c6deec2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178461525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.4178461525 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.1678958988 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 6012324279 ps |
CPU time | 794.19 seconds |
Started | Jul 19 06:04:17 PM PDT 24 |
Finished | Jul 19 06:17:31 PM PDT 24 |
Peak memory | 380816 kb |
Host | smart-1b6294f3-fff5-4c1b-a717-bacd3442b4ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678958988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1678958988 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.48264853 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 269466898 ps |
CPU time | 3.41 seconds |
Started | Jul 19 06:04:16 PM PDT 24 |
Finished | Jul 19 06:04:20 PM PDT 24 |
Peak memory | 221936 kb |
Host | smart-aa1dba25-2790-4d19-9e5e-8e4819eaf22b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48264853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_sec_cm.48264853 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.2839901250 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 4629593680 ps |
CPU time | 16.17 seconds |
Started | Jul 19 06:04:12 PM PDT 24 |
Finished | Jul 19 06:04:29 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-a275650c-8bee-4453-b56b-3e24c78106fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839901250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2839901250 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.3257203191 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 191307959269 ps |
CPU time | 4483.95 seconds |
Started | Jul 19 06:04:13 PM PDT 24 |
Finished | Jul 19 07:18:58 PM PDT 24 |
Peak memory | 227048 kb |
Host | smart-78e5206e-5f6b-4347-bdc4-3eef70213214 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257203191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.3257203191 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1459410446 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 5459354520 ps |
CPU time | 286.39 seconds |
Started | Jul 19 06:04:16 PM PDT 24 |
Finished | Jul 19 06:09:03 PM PDT 24 |
Peak memory | 350720 kb |
Host | smart-096ac9be-9c40-4267-acd5-c565870ca411 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1459410446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1459410446 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.872675793 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 6031469931 ps |
CPU time | 402.84 seconds |
Started | Jul 19 06:04:08 PM PDT 24 |
Finished | Jul 19 06:10:52 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-863c1209-6987-4c7a-b8fb-660fc0365e3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872675793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.872675793 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1834796470 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 2963667870 ps |
CPU time | 58.32 seconds |
Started | Jul 19 06:04:14 PM PDT 24 |
Finished | Jul 19 06:05:13 PM PDT 24 |
Peak memory | 307496 kb |
Host | smart-8a6ebb79-715b-4673-b4ea-c739b282508d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834796470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1834796470 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.671962164 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 41967933520 ps |
CPU time | 685.01 seconds |
Started | Jul 19 06:09:39 PM PDT 24 |
Finished | Jul 19 06:21:05 PM PDT 24 |
Peak memory | 356504 kb |
Host | smart-50c58a49-1140-4f36-b15a-4ddee0c37677 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671962164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 30.sram_ctrl_access_during_key_req.671962164 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.3967797926 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 46055432 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:09:57 PM PDT 24 |
Finished | Jul 19 06:09:58 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-005cc1b6-ff01-42d2-ac4a-5a8450ebc400 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967797926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3967797926 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.3519590367 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 203978046463 ps |
CPU time | 1597.51 seconds |
Started | Jul 19 06:09:39 PM PDT 24 |
Finished | Jul 19 06:36:17 PM PDT 24 |
Peak memory | 203228 kb |
Host | smart-3e003692-1d88-48aa-8ece-b04fba083403 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519590367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .3519590367 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.1954192555 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 23822742846 ps |
CPU time | 781.21 seconds |
Started | Jul 19 06:09:40 PM PDT 24 |
Finished | Jul 19 06:22:41 PM PDT 24 |
Peak memory | 340948 kb |
Host | smart-d5ed70e6-5832-4049-b767-2f161982de0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954192555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.1954192555 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.2662872297 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 68942824126 ps |
CPU time | 98.41 seconds |
Started | Jul 19 06:09:40 PM PDT 24 |
Finished | Jul 19 06:11:19 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-90dbde46-f1a5-4134-b684-cb3ec19fe928 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662872297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.2662872297 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.652807833 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 3029585647 ps |
CPU time | 17.03 seconds |
Started | Jul 19 06:09:40 PM PDT 24 |
Finished | Jul 19 06:09:57 PM PDT 24 |
Peak memory | 251976 kb |
Host | smart-2114d62f-177b-4db7-a08e-7e720c4ef4eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652807833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.sram_ctrl_max_throughput.652807833 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3803412071 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 3095690240 ps |
CPU time | 82.72 seconds |
Started | Jul 19 06:09:48 PM PDT 24 |
Finished | Jul 19 06:11:11 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-4bc16e4c-7953-49b7-8a60-d80d081fa074 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803412071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.3803412071 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.3096680838 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 20304987595 ps |
CPU time | 161.06 seconds |
Started | Jul 19 06:09:48 PM PDT 24 |
Finished | Jul 19 06:12:30 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-dd39b04c-e871-4fb1-bb3f-34b1a56bc92e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096680838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.3096680838 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1067329694 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 13032356206 ps |
CPU time | 1288.32 seconds |
Started | Jul 19 06:09:40 PM PDT 24 |
Finished | Jul 19 06:31:09 PM PDT 24 |
Peak memory | 372768 kb |
Host | smart-dcbeee67-114d-4ae5-9add-d44fa7e6134d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067329694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1067329694 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.1390029912 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 1265794533 ps |
CPU time | 20.66 seconds |
Started | Jul 19 06:09:40 PM PDT 24 |
Finished | Jul 19 06:10:01 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-af7296c6-7197-4e4b-a57f-304f819fafa4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390029912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.1390029912 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3951458010 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 37506196220 ps |
CPU time | 477.84 seconds |
Started | Jul 19 06:09:41 PM PDT 24 |
Finished | Jul 19 06:17:40 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-2ca5e65d-b5a3-4074-b4c3-1581c1842f96 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951458010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3951458010 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.4069685371 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 697052098 ps |
CPU time | 3.48 seconds |
Started | Jul 19 06:09:48 PM PDT 24 |
Finished | Jul 19 06:09:52 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-8d4fb0f1-6ab9-42b9-841c-6ef096d92c75 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069685371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.4069685371 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.2057202269 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 30821405226 ps |
CPU time | 1636.8 seconds |
Started | Jul 19 06:09:51 PM PDT 24 |
Finished | Jul 19 06:37:08 PM PDT 24 |
Peak memory | 379276 kb |
Host | smart-9973f5d2-1039-486e-a5be-eaac573217ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057202269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2057202269 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.2022783652 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 2786360742 ps |
CPU time | 8.13 seconds |
Started | Jul 19 06:09:41 PM PDT 24 |
Finished | Jul 19 06:09:50 PM PDT 24 |
Peak memory | 217212 kb |
Host | smart-3117b504-40fe-4935-9872-02bf4e251b2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022783652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2022783652 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.3224056754 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 376216491009 ps |
CPU time | 3331.79 seconds |
Started | Jul 19 06:09:56 PM PDT 24 |
Finished | Jul 19 07:05:30 PM PDT 24 |
Peak memory | 390064 kb |
Host | smart-56c86de6-d9f4-4d7a-9eb4-735b59832501 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224056754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 30.sram_ctrl_stress_all.3224056754 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1139965254 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 2379358990 ps |
CPU time | 260.71 seconds |
Started | Jul 19 06:09:49 PM PDT 24 |
Finished | Jul 19 06:14:10 PM PDT 24 |
Peak memory | 378808 kb |
Host | smart-f3234485-4db0-4e83-9dd1-d3f1be2a2408 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1139965254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1139965254 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1872482995 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 8343980216 ps |
CPU time | 310.07 seconds |
Started | Jul 19 06:09:40 PM PDT 24 |
Finished | Jul 19 06:14:51 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-5272a1e0-3698-4e08-b7e3-12a5485ad3b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872482995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1872482995 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.149087172 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 765792889 ps |
CPU time | 78.88 seconds |
Started | Jul 19 06:09:41 PM PDT 24 |
Finished | Jul 19 06:11:00 PM PDT 24 |
Peak memory | 336748 kb |
Host | smart-fcf3f297-6f82-43db-b0f9-e047864f1e88 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149087172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.149087172 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.532285243 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 21662910268 ps |
CPU time | 984.87 seconds |
Started | Jul 19 06:09:56 PM PDT 24 |
Finished | Jul 19 06:26:22 PM PDT 24 |
Peak memory | 378796 kb |
Host | smart-37f87e7a-fbb1-419d-920b-bfc807b681b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532285243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 31.sram_ctrl_access_during_key_req.532285243 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.3733279207 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 12559725 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:10:06 PM PDT 24 |
Finished | Jul 19 06:10:08 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-86d03fb5-5ef1-4345-9721-0000dff955c9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733279207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3733279207 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.1152606055 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 225343016242 ps |
CPU time | 2000.75 seconds |
Started | Jul 19 06:09:56 PM PDT 24 |
Finished | Jul 19 06:43:18 PM PDT 24 |
Peak memory | 203456 kb |
Host | smart-ea9a9917-f6b3-421d-ba0d-14760c5827d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152606055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .1152606055 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.2378096647 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 7381351993 ps |
CPU time | 1094.44 seconds |
Started | Jul 19 06:10:07 PM PDT 24 |
Finished | Jul 19 06:28:23 PM PDT 24 |
Peak memory | 372584 kb |
Host | smart-5f417386-0659-497e-9218-479cf76ac156 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378096647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.2378096647 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.3717144298 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 45097796463 ps |
CPU time | 75.61 seconds |
Started | Jul 19 06:09:57 PM PDT 24 |
Finished | Jul 19 06:11:14 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-fe5e1116-f650-4ddb-a926-7c56e84c8859 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717144298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.3717144298 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.3379167761 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 2578922274 ps |
CPU time | 18.28 seconds |
Started | Jul 19 06:09:56 PM PDT 24 |
Finished | Jul 19 06:10:16 PM PDT 24 |
Peak memory | 251996 kb |
Host | smart-ae9df877-6a0a-44d4-9ccc-8e15bacbcc87 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379167761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.3379167761 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2785559004 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 1469940700 ps |
CPU time | 79.02 seconds |
Started | Jul 19 06:10:08 PM PDT 24 |
Finished | Jul 19 06:11:28 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-cab7ab3f-7970-4022-85de-3d005252e639 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785559004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.2785559004 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.1323647773 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 13849579476 ps |
CPU time | 347.41 seconds |
Started | Jul 19 06:10:07 PM PDT 24 |
Finished | Jul 19 06:15:55 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-3432aee3-8595-4263-9c5e-869f66a53814 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323647773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.1323647773 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.4151184485 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 39058616472 ps |
CPU time | 769.79 seconds |
Started | Jul 19 06:09:58 PM PDT 24 |
Finished | Jul 19 06:22:49 PM PDT 24 |
Peak memory | 378768 kb |
Host | smart-c17bc8f4-c181-4b7c-be66-e998c6334009 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151184485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.4151184485 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.455559546 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 2319366348 ps |
CPU time | 17.37 seconds |
Started | Jul 19 06:09:58 PM PDT 24 |
Finished | Jul 19 06:10:17 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-2a24bb24-10cc-46d9-bdd8-9669f04d0351 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455559546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.s ram_ctrl_partial_access.455559546 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3409429464 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 24183516820 ps |
CPU time | 574.46 seconds |
Started | Jul 19 06:09:56 PM PDT 24 |
Finished | Jul 19 06:19:32 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-d961461c-29ab-45da-9819-238d4185aa37 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409429464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.3409429464 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.3429158791 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 362524829 ps |
CPU time | 3.23 seconds |
Started | Jul 19 06:10:07 PM PDT 24 |
Finished | Jul 19 06:10:12 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-0355040d-5837-49d1-8ef6-02288c2410c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429158791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3429158791 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.960188324 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 1325166834 ps |
CPU time | 167.99 seconds |
Started | Jul 19 06:10:10 PM PDT 24 |
Finished | Jul 19 06:13:00 PM PDT 24 |
Peak memory | 344908 kb |
Host | smart-9d438c0d-071f-44da-a843-fcb64157317a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960188324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.960188324 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.3174605498 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1659883475 ps |
CPU time | 17.25 seconds |
Started | Jul 19 06:09:58 PM PDT 24 |
Finished | Jul 19 06:10:17 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-4345c036-57c2-4d97-88fb-bd5b305c1326 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174605498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3174605498 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.2137722918 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 18228276427 ps |
CPU time | 2172.03 seconds |
Started | Jul 19 06:10:08 PM PDT 24 |
Finished | Jul 19 06:46:21 PM PDT 24 |
Peak memory | 383056 kb |
Host | smart-fbfe22a4-2b69-4655-85fd-73c2131a4bb7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137722918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.2137722918 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3783620499 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 2343264202 ps |
CPU time | 34.31 seconds |
Started | Jul 19 06:10:07 PM PDT 24 |
Finished | Jul 19 06:10:43 PM PDT 24 |
Peak memory | 211216 kb |
Host | smart-2892f64f-ee42-460c-b6eb-1ae97d268e22 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3783620499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3783620499 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2317404906 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 8700210533 ps |
CPU time | 287.05 seconds |
Started | Jul 19 06:09:55 PM PDT 24 |
Finished | Jul 19 06:14:43 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-083dcc58-cbf6-4c27-bb9c-ae5048e2a4a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317404906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.2317404906 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2018639371 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 2596085930 ps |
CPU time | 131.09 seconds |
Started | Jul 19 06:09:58 PM PDT 24 |
Finished | Jul 19 06:12:09 PM PDT 24 |
Peak memory | 365424 kb |
Host | smart-1d3b795d-c631-447b-b22e-02dc4329dfee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018639371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2018639371 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3657386703 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 20253666214 ps |
CPU time | 803.16 seconds |
Started | Jul 19 06:10:14 PM PDT 24 |
Finished | Jul 19 06:23:39 PM PDT 24 |
Peak memory | 378968 kb |
Host | smart-0abd13d7-f77f-47fe-9166-f37af2faf692 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657386703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.3657386703 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.2671384530 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 16472353 ps |
CPU time | 0.71 seconds |
Started | Jul 19 06:10:16 PM PDT 24 |
Finished | Jul 19 06:10:17 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-31be26eb-186c-4ca0-b00d-359a0ad05567 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671384530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.2671384530 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.706559395 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 25335727710 ps |
CPU time | 846.14 seconds |
Started | Jul 19 06:10:07 PM PDT 24 |
Finished | Jul 19 06:24:15 PM PDT 24 |
Peak memory | 203672 kb |
Host | smart-0179b361-2a08-4b93-bd12-0062eaf7dde1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706559395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection. 706559395 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.382581453 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 22540619570 ps |
CPU time | 827.71 seconds |
Started | Jul 19 06:10:19 PM PDT 24 |
Finished | Jul 19 06:24:08 PM PDT 24 |
Peak memory | 377724 kb |
Host | smart-5f874e60-669d-4749-b0a2-dfc358bd0f28 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382581453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executabl e.382581453 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.3233798142 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 16291368992 ps |
CPU time | 107.22 seconds |
Started | Jul 19 06:10:10 PM PDT 24 |
Finished | Jul 19 06:11:59 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-57419370-dced-437c-8675-392c079e89c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233798142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.3233798142 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.21741478 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 3079894621 ps |
CPU time | 81.5 seconds |
Started | Jul 19 06:10:07 PM PDT 24 |
Finished | Jul 19 06:11:29 PM PDT 24 |
Peak memory | 326644 kb |
Host | smart-15b93acb-7ee2-496c-bdc0-87709f94595a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21741478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 32.sram_ctrl_max_throughput.21741478 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.1505710532 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 10296602497 ps |
CPU time | 323.65 seconds |
Started | Jul 19 06:10:14 PM PDT 24 |
Finished | Jul 19 06:15:40 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-86f66c3f-c2e1-4c1d-99ae-a1eee65c5e57 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505710532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.1505710532 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.4186530078 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 83215617391 ps |
CPU time | 935.98 seconds |
Started | Jul 19 06:10:09 PM PDT 24 |
Finished | Jul 19 06:25:45 PM PDT 24 |
Peak memory | 377780 kb |
Host | smart-6c6f24dc-55b7-437c-a678-78767e1faa67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186530078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.4186530078 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1511221073 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 1702710717 ps |
CPU time | 22.39 seconds |
Started | Jul 19 06:10:07 PM PDT 24 |
Finished | Jul 19 06:10:30 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-691bba2f-f7e6-4f37-a837-a9954a8572ab |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511221073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1511221073 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2804029565 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 5348656692 ps |
CPU time | 344.69 seconds |
Started | Jul 19 06:10:06 PM PDT 24 |
Finished | Jul 19 06:15:51 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-f1cd9eb5-6698-484d-8dc0-119ea9a6d2e8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804029565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.2804029565 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.370983127 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 2112899976 ps |
CPU time | 4.18 seconds |
Started | Jul 19 06:10:14 PM PDT 24 |
Finished | Jul 19 06:10:20 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-6f4fda01-2eed-43e6-8806-176d3b33e07e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370983127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.370983127 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.1471274451 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 18680035643 ps |
CPU time | 401.37 seconds |
Started | Jul 19 06:10:13 PM PDT 24 |
Finished | Jul 19 06:16:56 PM PDT 24 |
Peak memory | 343948 kb |
Host | smart-51fce2d3-a33f-4153-b269-3de93c7ae83d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471274451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1471274451 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.1436030425 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 1926268283 ps |
CPU time | 12.62 seconds |
Started | Jul 19 06:10:08 PM PDT 24 |
Finished | Jul 19 06:10:22 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-4c65711d-d47b-4c0b-a1db-b1b64135c91d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436030425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1436030425 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.1649809241 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 575335665669 ps |
CPU time | 5755.92 seconds |
Started | Jul 19 06:10:20 PM PDT 24 |
Finished | Jul 19 07:46:17 PM PDT 24 |
Peak memory | 380792 kb |
Host | smart-a9197c1b-7784-4d21-906a-8a7131aebe85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649809241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.1649809241 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.652113507 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 2036682223 ps |
CPU time | 176.25 seconds |
Started | Jul 19 06:10:06 PM PDT 24 |
Finished | Jul 19 06:13:02 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-0b8992fb-c78e-498a-86f5-0082842eaf63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652113507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sram_ctrl_stress_pipeline.652113507 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2407511723 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 703505165 ps |
CPU time | 15.23 seconds |
Started | Jul 19 06:10:07 PM PDT 24 |
Finished | Jul 19 06:10:23 PM PDT 24 |
Peak memory | 251948 kb |
Host | smart-61bd9bdb-e7b5-4391-b8dd-3ebcbad15cbb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407511723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2407511723 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2144368563 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 1152170654 ps |
CPU time | 188.46 seconds |
Started | Jul 19 06:10:24 PM PDT 24 |
Finished | Jul 19 06:13:33 PM PDT 24 |
Peak memory | 372480 kb |
Host | smart-0f64f1e0-3380-4fae-9a86-6c1449345a11 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144368563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.2144368563 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.874684680 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 70216056 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:10:30 PM PDT 24 |
Finished | Jul 19 06:10:32 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-2e433125-485d-4ea2-9fac-d4d9d97c15f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874684680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.874684680 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.2333942725 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 442058515277 ps |
CPU time | 1919.65 seconds |
Started | Jul 19 06:10:20 PM PDT 24 |
Finished | Jul 19 06:42:21 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-001546f6-606e-4b58-963b-51b87a8d12f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333942725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .2333942725 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.547192178 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 17423425791 ps |
CPU time | 1223.38 seconds |
Started | Jul 19 06:10:23 PM PDT 24 |
Finished | Jul 19 06:30:47 PM PDT 24 |
Peak memory | 379852 kb |
Host | smart-d43587a9-c05c-48e1-abf1-941ec2fabe5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547192178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl e.547192178 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.2431476422 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 9349984672 ps |
CPU time | 55.47 seconds |
Started | Jul 19 06:10:23 PM PDT 24 |
Finished | Jul 19 06:11:19 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-d4390605-bd10-4cb0-adc6-99b03244c496 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431476422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.2431476422 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.3809497499 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 1545146717 ps |
CPU time | 49.9 seconds |
Started | Jul 19 06:10:14 PM PDT 24 |
Finished | Jul 19 06:11:05 PM PDT 24 |
Peak memory | 314292 kb |
Host | smart-c57ddc91-b8b6-42bc-9ac2-56dfaa1e2d4b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809497499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.3809497499 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1105553883 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 9793434497 ps |
CPU time | 72.05 seconds |
Started | Jul 19 06:10:22 PM PDT 24 |
Finished | Jul 19 06:11:35 PM PDT 24 |
Peak memory | 219216 kb |
Host | smart-493c1b06-4d06-44bc-9870-b362b2d69bb6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105553883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.1105553883 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.4063430361 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 3950900375 ps |
CPU time | 133.18 seconds |
Started | Jul 19 06:10:23 PM PDT 24 |
Finished | Jul 19 06:12:37 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-4b152c8b-d4dc-481a-a2a6-20663a35725c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063430361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.4063430361 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.286023490 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 28212803286 ps |
CPU time | 1339.2 seconds |
Started | Jul 19 06:10:15 PM PDT 24 |
Finished | Jul 19 06:32:36 PM PDT 24 |
Peak memory | 375664 kb |
Host | smart-19965060-24cf-49d6-8f4e-97cbbc362b8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286023490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip le_keys.286023490 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.2286464704 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 2005767443 ps |
CPU time | 7.07 seconds |
Started | Jul 19 06:10:13 PM PDT 24 |
Finished | Jul 19 06:10:22 PM PDT 24 |
Peak memory | 216512 kb |
Host | smart-93992a8c-c795-46a2-aedf-619402eb2d2e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286464704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.2286464704 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.886967990 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 67974747802 ps |
CPU time | 425.47 seconds |
Started | Jul 19 06:10:14 PM PDT 24 |
Finished | Jul 19 06:17:21 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-66557be3-fd74-4806-94c5-086f3c290812 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886967990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.sram_ctrl_partial_access_b2b.886967990 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.4036726027 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 1780548623 ps |
CPU time | 3.4 seconds |
Started | Jul 19 06:10:23 PM PDT 24 |
Finished | Jul 19 06:10:27 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-36a9ac24-6abc-48e1-a446-dc805fedeafa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036726027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.4036726027 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.1105649857 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 8807575554 ps |
CPU time | 707.25 seconds |
Started | Jul 19 06:10:23 PM PDT 24 |
Finished | Jul 19 06:22:11 PM PDT 24 |
Peak memory | 374660 kb |
Host | smart-79f4308a-bb3e-4106-b616-43cecc60ccb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105649857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1105649857 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.2862775791 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 1551310524 ps |
CPU time | 124.55 seconds |
Started | Jul 19 06:10:20 PM PDT 24 |
Finished | Jul 19 06:12:25 PM PDT 24 |
Peak memory | 350956 kb |
Host | smart-71394ab9-e9c7-4040-9806-fba922e00f40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862775791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2862775791 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.3232127328 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 153386564757 ps |
CPU time | 5993.41 seconds |
Started | Jul 19 06:10:29 PM PDT 24 |
Finished | Jul 19 07:50:24 PM PDT 24 |
Peak memory | 380828 kb |
Host | smart-4d938c98-91cd-4bf0-b5b4-55318153a4b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232127328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.3232127328 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1276188938 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 11604148500 ps |
CPU time | 20.92 seconds |
Started | Jul 19 06:10:30 PM PDT 24 |
Finished | Jul 19 06:10:51 PM PDT 24 |
Peak memory | 211520 kb |
Host | smart-6f287b58-c927-48d2-a6e4-2c4146f0f42e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1276188938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1276188938 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2345724055 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 31651564885 ps |
CPU time | 390 seconds |
Started | Jul 19 06:10:16 PM PDT 24 |
Finished | Jul 19 06:16:47 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-5d5fcd88-b8c6-41a2-b3c2-662892d574ef |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345724055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.2345724055 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1920783248 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 802700858 ps |
CPU time | 80.95 seconds |
Started | Jul 19 06:10:22 PM PDT 24 |
Finished | Jul 19 06:11:44 PM PDT 24 |
Peak memory | 317496 kb |
Host | smart-3a82b0b5-556f-40b7-842e-4da3469e649e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920783248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1920783248 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3824227581 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 4779086320 ps |
CPU time | 569.11 seconds |
Started | Jul 19 06:10:36 PM PDT 24 |
Finished | Jul 19 06:20:05 PM PDT 24 |
Peak memory | 378588 kb |
Host | smart-305cb166-536c-4828-8ccd-ba4210691346 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824227581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.3824227581 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.1515725926 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 39613029 ps |
CPU time | 0.69 seconds |
Started | Jul 19 06:10:44 PM PDT 24 |
Finished | Jul 19 06:10:46 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-e4d04836-f08b-4682-b01f-81a1227795a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515725926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1515725926 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.2317351586 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 24320922599 ps |
CPU time | 863.85 seconds |
Started | Jul 19 06:10:29 PM PDT 24 |
Finished | Jul 19 06:24:54 PM PDT 24 |
Peak memory | 203728 kb |
Host | smart-6b2895fd-9452-4887-8d90-73851ea8b131 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317351586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .2317351586 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.1381662256 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 9885748192 ps |
CPU time | 1268.03 seconds |
Started | Jul 19 06:10:39 PM PDT 24 |
Finished | Jul 19 06:31:48 PM PDT 24 |
Peak memory | 375668 kb |
Host | smart-af6e5185-1a86-4361-9d5b-5ab18c896933 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381662256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.1381662256 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.1312574303 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 39957683728 ps |
CPU time | 52.63 seconds |
Started | Jul 19 06:10:37 PM PDT 24 |
Finished | Jul 19 06:11:30 PM PDT 24 |
Peak memory | 216036 kb |
Host | smart-321856bf-3220-4385-ba22-e010af1db1d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312574303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.1312574303 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.1104544575 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 2943608422 ps |
CPU time | 82.91 seconds |
Started | Jul 19 06:10:30 PM PDT 24 |
Finished | Jul 19 06:11:54 PM PDT 24 |
Peak memory | 320480 kb |
Host | smart-ac65f11d-2b70-42a3-8251-feb8645624f2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104544575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.1104544575 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.4246525161 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 2390000625 ps |
CPU time | 74.56 seconds |
Started | Jul 19 06:10:36 PM PDT 24 |
Finished | Jul 19 06:11:51 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-6d9b0314-ca93-47c9-a055-f4b37b5bc4d9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246525161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.4246525161 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.2024008739 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 82765415709 ps |
CPU time | 352.74 seconds |
Started | Jul 19 06:10:36 PM PDT 24 |
Finished | Jul 19 06:16:30 PM PDT 24 |
Peak memory | 211776 kb |
Host | smart-1cb26f72-6e32-4032-80dd-bb1986984c95 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024008739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.2024008739 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.1395554101 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 21978630995 ps |
CPU time | 958.74 seconds |
Started | Jul 19 06:10:29 PM PDT 24 |
Finished | Jul 19 06:26:28 PM PDT 24 |
Peak memory | 380840 kb |
Host | smart-f0aef62c-44d2-4af3-a2cc-758ef63be0df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395554101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1395554101 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.2183284333 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 2190134217 ps |
CPU time | 16.7 seconds |
Started | Jul 19 06:10:34 PM PDT 24 |
Finished | Jul 19 06:10:51 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-8bef032c-18f3-4ac0-835f-6e7efd49830d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183284333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.2183284333 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1150703834 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 12932827024 ps |
CPU time | 195.25 seconds |
Started | Jul 19 06:10:30 PM PDT 24 |
Finished | Jul 19 06:13:46 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-babe1d2a-87a2-4119-bb60-84d9101a3906 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150703834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.1150703834 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.2501520899 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 352943313 ps |
CPU time | 3.1 seconds |
Started | Jul 19 06:10:37 PM PDT 24 |
Finished | Jul 19 06:10:41 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-5e968e7d-3c49-4121-9a6c-5c93fadfe32c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501520899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2501520899 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.3465985394 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 283320578937 ps |
CPU time | 840.87 seconds |
Started | Jul 19 06:10:38 PM PDT 24 |
Finished | Jul 19 06:24:40 PM PDT 24 |
Peak memory | 348084 kb |
Host | smart-64c1cdaa-e59a-460f-93ac-7bc0785ea6e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465985394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3465985394 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.2120004970 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 3541817847 ps |
CPU time | 7.26 seconds |
Started | Jul 19 06:10:32 PM PDT 24 |
Finished | Jul 19 06:10:40 PM PDT 24 |
Peak memory | 207352 kb |
Host | smart-c4a1b126-cffa-4a5a-82a2-611b88b86681 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120004970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2120004970 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.1304150558 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 668303528960 ps |
CPU time | 3362.18 seconds |
Started | Jul 19 06:10:45 PM PDT 24 |
Finished | Jul 19 07:06:49 PM PDT 24 |
Peak memory | 380900 kb |
Host | smart-27ae1a32-018f-4f84-bbb9-6fcd136fb7d7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304150558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.1304150558 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2685645531 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 1163944829 ps |
CPU time | 65.69 seconds |
Started | Jul 19 06:10:38 PM PDT 24 |
Finished | Jul 19 06:11:44 PM PDT 24 |
Peak memory | 276412 kb |
Host | smart-a7d05125-0172-4ee2-a10b-93ed3b6826b5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2685645531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2685645531 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.3020654354 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 2707854456 ps |
CPU time | 181.37 seconds |
Started | Jul 19 06:10:30 PM PDT 24 |
Finished | Jul 19 06:13:32 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-4a3f0810-b9e2-4866-bb4b-410e156e08f6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020654354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.3020654354 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3160447280 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 2696985686 ps |
CPU time | 7.71 seconds |
Started | Jul 19 06:10:37 PM PDT 24 |
Finished | Jul 19 06:10:45 PM PDT 24 |
Peak memory | 212140 kb |
Host | smart-a208e6ca-7fe6-4fc8-ac52-110e7c6cf8bf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160447280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3160447280 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.109169904 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 34255161937 ps |
CPU time | 1215.66 seconds |
Started | Jul 19 06:10:52 PM PDT 24 |
Finished | Jul 19 06:31:08 PM PDT 24 |
Peak memory | 374648 kb |
Host | smart-708ab682-8e6b-4220-aea4-8ccb7265a683 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109169904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.sram_ctrl_access_during_key_req.109169904 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.2729343103 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 21336591 ps |
CPU time | 0.67 seconds |
Started | Jul 19 06:10:53 PM PDT 24 |
Finished | Jul 19 06:10:55 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-7f79855a-d6cd-4695-82fe-20eea8d12f8d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729343103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2729343103 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.2320816825 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 22643189566 ps |
CPU time | 1563.54 seconds |
Started | Jul 19 06:10:46 PM PDT 24 |
Finished | Jul 19 06:36:50 PM PDT 24 |
Peak memory | 203748 kb |
Host | smart-317e9945-cef5-4357-ac3d-183de747549d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320816825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .2320816825 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.1352617554 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 48157162778 ps |
CPU time | 1215.17 seconds |
Started | Jul 19 06:10:52 PM PDT 24 |
Finished | Jul 19 06:31:08 PM PDT 24 |
Peak memory | 379796 kb |
Host | smart-1a70e3d3-ba1b-4bca-9f8c-23a2b5cd02e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352617554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.1352617554 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.2316641235 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 12340142846 ps |
CPU time | 39.3 seconds |
Started | Jul 19 06:10:51 PM PDT 24 |
Finished | Jul 19 06:11:31 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-b5962cf3-4bf7-4306-9c55-32da68fb9be9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316641235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.2316641235 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.2674886242 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 5613946304 ps |
CPU time | 8.41 seconds |
Started | Jul 19 06:10:52 PM PDT 24 |
Finished | Jul 19 06:11:01 PM PDT 24 |
Peak memory | 219336 kb |
Host | smart-02b13e95-8c85-43f4-8477-c78060b4e07e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674886242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.2674886242 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.895299098 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 30533371434 ps |
CPU time | 154.98 seconds |
Started | Jul 19 06:10:53 PM PDT 24 |
Finished | Jul 19 06:13:29 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-8b997eca-ce1c-4403-bd17-d1140d9bc07f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895299098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sram_ctrl_mem_partial_access.895299098 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.1341089062 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 9884914023 ps |
CPU time | 165.68 seconds |
Started | Jul 19 06:10:52 PM PDT 24 |
Finished | Jul 19 06:13:39 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-110034dd-eaba-4df1-b322-41beda9fad37 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341089062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.1341089062 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.3322484593 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 61099172286 ps |
CPU time | 1263.93 seconds |
Started | Jul 19 06:10:46 PM PDT 24 |
Finished | Jul 19 06:31:50 PM PDT 24 |
Peak memory | 378780 kb |
Host | smart-7801d3a0-aad9-40b0-96e3-9f5d8209faf7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322484593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.3322484593 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.3828655944 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 3709533727 ps |
CPU time | 85.25 seconds |
Started | Jul 19 06:10:44 PM PDT 24 |
Finished | Jul 19 06:12:10 PM PDT 24 |
Peak memory | 349244 kb |
Host | smart-207039cf-93cf-48d4-a699-362e11a0941c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828655944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3828655944 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.915920223 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 8378485603 ps |
CPU time | 493.84 seconds |
Started | Jul 19 06:10:52 PM PDT 24 |
Finished | Jul 19 06:19:06 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-cce791e1-b969-4b65-bdf4-5bccdf853db6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915920223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 35.sram_ctrl_partial_access_b2b.915920223 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.939396509 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 362232031 ps |
CPU time | 3.23 seconds |
Started | Jul 19 06:10:53 PM PDT 24 |
Finished | Jul 19 06:10:57 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-de56e016-5c8c-4dba-bb4a-cbed36000ea5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939396509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.939396509 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.2695861258 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 7786312477 ps |
CPU time | 405.33 seconds |
Started | Jul 19 06:10:54 PM PDT 24 |
Finished | Jul 19 06:17:40 PM PDT 24 |
Peak memory | 368516 kb |
Host | smart-275d00fd-cb36-4074-a08e-14fdb8310a79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695861258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2695861258 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.211643838 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 1518176097 ps |
CPU time | 19.31 seconds |
Started | Jul 19 06:10:45 PM PDT 24 |
Finished | Jul 19 06:11:05 PM PDT 24 |
Peak memory | 268204 kb |
Host | smart-2f0877f0-9e75-41cf-8d95-48a6491e8f8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211643838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.211643838 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.1323047810 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 12349385157 ps |
CPU time | 2043.53 seconds |
Started | Jul 19 06:10:53 PM PDT 24 |
Finished | Jul 19 06:44:58 PM PDT 24 |
Peak memory | 378772 kb |
Host | smart-0947367e-f60c-47b1-9d0c-d3b4be7f3fae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323047810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.1323047810 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3973129784 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 8734056442 ps |
CPU time | 33.26 seconds |
Started | Jul 19 06:10:54 PM PDT 24 |
Finished | Jul 19 06:11:28 PM PDT 24 |
Peak memory | 211800 kb |
Host | smart-4214cc2a-5a80-4ab5-a9d4-be8d3e142ab4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3973129784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3973129784 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2469119384 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 2502909466 ps |
CPU time | 117.57 seconds |
Started | Jul 19 06:10:46 PM PDT 24 |
Finished | Jul 19 06:12:45 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-c71cb58f-a1f0-464e-86b3-f08cc3dbaee5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469119384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.2469119384 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1677353177 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 742680054 ps |
CPU time | 29.68 seconds |
Started | Jul 19 06:10:52 PM PDT 24 |
Finished | Jul 19 06:11:23 PM PDT 24 |
Peak memory | 277840 kb |
Host | smart-4e2272fe-fe35-43f2-b575-e6a8f4ef73b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677353177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1677353177 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3284871649 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 9859588105 ps |
CPU time | 823.54 seconds |
Started | Jul 19 06:11:00 PM PDT 24 |
Finished | Jul 19 06:24:44 PM PDT 24 |
Peak memory | 376864 kb |
Host | smart-247eff4d-3172-4844-9a6d-a51aece4e580 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284871649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.3284871649 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.1984350931 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 103642611 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:11:09 PM PDT 24 |
Finished | Jul 19 06:11:10 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-4ba20ef7-2da8-43ad-9fe6-4a74102c6957 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984350931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1984350931 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.474815491 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 153583619168 ps |
CPU time | 1925.14 seconds |
Started | Jul 19 06:11:01 PM PDT 24 |
Finished | Jul 19 06:43:07 PM PDT 24 |
Peak memory | 203588 kb |
Host | smart-0fef862c-32d3-4ee8-8d9b-41e7db186de1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474815491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection. 474815491 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.1371439850 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 103293966520 ps |
CPU time | 793.66 seconds |
Started | Jul 19 06:11:01 PM PDT 24 |
Finished | Jul 19 06:24:16 PM PDT 24 |
Peak memory | 375636 kb |
Host | smart-8ed04d5f-4423-49e1-9e2e-4244394838c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371439850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.1371439850 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.2782061643 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 7090378336 ps |
CPU time | 40.6 seconds |
Started | Jul 19 06:10:59 PM PDT 24 |
Finished | Jul 19 06:11:40 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-465c6861-bb9d-40b5-b904-1de8105cdd44 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782061643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.2782061643 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.2393808440 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 2867002682 ps |
CPU time | 10.93 seconds |
Started | Jul 19 06:11:02 PM PDT 24 |
Finished | Jul 19 06:11:13 PM PDT 24 |
Peak memory | 235640 kb |
Host | smart-6a15a975-80a1-454a-bd95-26873afb50d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393808440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.2393808440 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.783601300 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 2003014668 ps |
CPU time | 67.44 seconds |
Started | Jul 19 06:11:09 PM PDT 24 |
Finished | Jul 19 06:12:17 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-58d73026-3c68-443b-90ba-e9c373b654d7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783601300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sram_ctrl_mem_partial_access.783601300 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.3789187618 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2634062197 ps |
CPU time | 153.29 seconds |
Started | Jul 19 06:11:11 PM PDT 24 |
Finished | Jul 19 06:13:45 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-71bd0994-7757-4ba1-b1b3-871076174611 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789187618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.3789187618 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.2588005581 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 10856960158 ps |
CPU time | 456.28 seconds |
Started | Jul 19 06:11:01 PM PDT 24 |
Finished | Jul 19 06:18:38 PM PDT 24 |
Peak memory | 376624 kb |
Host | smart-87966a6b-fd7a-4a91-b48f-6ce04e4bd618 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588005581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.2588005581 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.3570691486 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 2139653835 ps |
CPU time | 51.93 seconds |
Started | Jul 19 06:11:01 PM PDT 24 |
Finished | Jul 19 06:11:53 PM PDT 24 |
Peak memory | 291960 kb |
Host | smart-b5d66e9f-186a-4457-8db6-f195fe956690 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570691486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.3570691486 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2547270847 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 79279977951 ps |
CPU time | 467.64 seconds |
Started | Jul 19 06:11:02 PM PDT 24 |
Finished | Jul 19 06:18:50 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-8f4e3201-38e9-4565-81a1-b58ec1d020f9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547270847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.2547270847 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.799664069 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 1680638391 ps |
CPU time | 3.82 seconds |
Started | Jul 19 06:11:09 PM PDT 24 |
Finished | Jul 19 06:11:13 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-8802cc51-4cd5-41d2-9a97-018f9be4e47b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799664069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.799664069 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.4242778508 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 13224363597 ps |
CPU time | 1208.56 seconds |
Started | Jul 19 06:11:01 PM PDT 24 |
Finished | Jul 19 06:31:10 PM PDT 24 |
Peak memory | 378808 kb |
Host | smart-c049a754-8581-400c-9d24-5ef180f43197 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242778508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.4242778508 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.4048685945 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 705355119 ps |
CPU time | 137.38 seconds |
Started | Jul 19 06:11:00 PM PDT 24 |
Finished | Jul 19 06:13:18 PM PDT 24 |
Peak memory | 363404 kb |
Host | smart-bcfa7edf-c7ac-409d-a78f-b93bd7ee7f0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048685945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.4048685945 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.2906307058 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 835291932816 ps |
CPU time | 4334.47 seconds |
Started | Jul 19 06:11:08 PM PDT 24 |
Finished | Jul 19 07:23:24 PM PDT 24 |
Peak memory | 307616 kb |
Host | smart-13d79b03-1847-4563-90c9-276e47b0eac0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906307058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.2906307058 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2396492547 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 1598105278 ps |
CPU time | 24.54 seconds |
Started | Jul 19 06:11:09 PM PDT 24 |
Finished | Jul 19 06:11:34 PM PDT 24 |
Peak memory | 212424 kb |
Host | smart-02dd074d-9f4e-4c6d-b109-59b210d83761 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2396492547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2396492547 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1116903283 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 4078747934 ps |
CPU time | 156.35 seconds |
Started | Jul 19 06:11:01 PM PDT 24 |
Finished | Jul 19 06:13:38 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-183fc378-a261-43a3-9c05-b64665b54682 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116903283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.1116903283 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3307723895 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 2468086572 ps |
CPU time | 6.16 seconds |
Started | Jul 19 06:10:59 PM PDT 24 |
Finished | Jul 19 06:11:06 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-91951f44-2cd3-425f-8203-93923daabe0b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307723895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.3307723895 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3481779521 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 9207530996 ps |
CPU time | 524.01 seconds |
Started | Jul 19 06:11:16 PM PDT 24 |
Finished | Jul 19 06:20:00 PM PDT 24 |
Peak memory | 376684 kb |
Host | smart-a95e9148-4f59-4ae6-90eb-ea5fd2175409 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481779521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.3481779521 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.1547310641 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 31517993 ps |
CPU time | 0.69 seconds |
Started | Jul 19 06:11:34 PM PDT 24 |
Finished | Jul 19 06:11:35 PM PDT 24 |
Peak memory | 202476 kb |
Host | smart-0b2577de-563e-49ef-8253-935c5a9d210e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547310641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1547310641 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.1455928347 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 36206784075 ps |
CPU time | 1191.5 seconds |
Started | Jul 19 06:11:16 PM PDT 24 |
Finished | Jul 19 06:31:08 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-296a821a-6a78-4f00-a9ad-f3b1226e504f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455928347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .1455928347 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.3392030640 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 43334919746 ps |
CPU time | 1054.48 seconds |
Started | Jul 19 06:11:24 PM PDT 24 |
Finished | Jul 19 06:28:59 PM PDT 24 |
Peak memory | 371560 kb |
Host | smart-9e8da31c-4879-4a0f-809a-9703263e27ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392030640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.3392030640 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.2203205813 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 13553105280 ps |
CPU time | 11.02 seconds |
Started | Jul 19 06:11:17 PM PDT 24 |
Finished | Jul 19 06:11:28 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-fd3b38e3-7f9c-41e7-91d5-348f85f69344 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203205813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.2203205813 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.1077218479 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 2987055406 ps |
CPU time | 38.67 seconds |
Started | Jul 19 06:11:16 PM PDT 24 |
Finished | Jul 19 06:11:56 PM PDT 24 |
Peak memory | 286740 kb |
Host | smart-1c6c9167-3d89-4d75-b752-7cda45172bdc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077218479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.1077218479 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1623921128 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 4394296750 ps |
CPU time | 156.02 seconds |
Started | Jul 19 06:11:22 PM PDT 24 |
Finished | Jul 19 06:13:59 PM PDT 24 |
Peak memory | 211156 kb |
Host | smart-95d9f719-7d7a-4226-b11a-7790e63009a7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623921128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_mem_partial_access.1623921128 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.1738146928 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 16425052885 ps |
CPU time | 255.92 seconds |
Started | Jul 19 06:11:27 PM PDT 24 |
Finished | Jul 19 06:15:43 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-aa2c003e-e2a3-42bd-b157-b98c627a2145 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738146928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.1738146928 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.3203029534 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 26773211356 ps |
CPU time | 940.33 seconds |
Started | Jul 19 06:11:18 PM PDT 24 |
Finished | Jul 19 06:26:59 PM PDT 24 |
Peak memory | 381076 kb |
Host | smart-76225bac-0572-4213-ba86-d592be224ddf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203029534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.3203029534 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.1223239642 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 912714704 ps |
CPU time | 9.86 seconds |
Started | Jul 19 06:11:19 PM PDT 24 |
Finished | Jul 19 06:11:29 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-fcd53529-817c-41e8-b888-e3e7f532cf1a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223239642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.1223239642 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1722752299 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 48730058993 ps |
CPU time | 631.11 seconds |
Started | Jul 19 06:11:15 PM PDT 24 |
Finished | Jul 19 06:21:47 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-871b1f11-480c-4fe8-ad91-e0eda7ee59d6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722752299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.1722752299 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.1937955310 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 518919406 ps |
CPU time | 3.16 seconds |
Started | Jul 19 06:11:23 PM PDT 24 |
Finished | Jul 19 06:11:26 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-7ca851cd-e6d3-446e-ac49-6af13ccc59c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937955310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1937955310 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.445464585 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 27775419880 ps |
CPU time | 1617.9 seconds |
Started | Jul 19 06:11:22 PM PDT 24 |
Finished | Jul 19 06:38:21 PM PDT 24 |
Peak memory | 381824 kb |
Host | smart-c05e926b-2fb8-4850-a7aa-3ccb432131ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445464585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.445464585 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.1360104409 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 1668914713 ps |
CPU time | 17.5 seconds |
Started | Jul 19 06:11:08 PM PDT 24 |
Finished | Jul 19 06:11:26 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-9be51a9a-d943-4729-acd3-1a3647774637 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360104409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1360104409 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.26951946 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 237144836253 ps |
CPU time | 6272.79 seconds |
Started | Jul 19 06:11:24 PM PDT 24 |
Finished | Jul 19 07:55:59 PM PDT 24 |
Peak memory | 390052 kb |
Host | smart-8c96c549-0b87-40b2-a60c-34e74ea2d25b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26951946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.sram_ctrl_stress_all.26951946 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3111529588 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 1786550706 ps |
CPU time | 150.69 seconds |
Started | Jul 19 06:11:23 PM PDT 24 |
Finished | Jul 19 06:13:54 PM PDT 24 |
Peak memory | 300868 kb |
Host | smart-c5b0343d-aba8-456a-ad8d-08da60f5efa8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3111529588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3111529588 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2554409912 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 6634360641 ps |
CPU time | 199.74 seconds |
Started | Jul 19 06:11:18 PM PDT 24 |
Finished | Jul 19 06:14:38 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-bddc9992-9afb-434a-b766-61bb28335c69 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554409912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.2554409912 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2569664918 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 977476570 ps |
CPU time | 160.03 seconds |
Started | Jul 19 06:11:15 PM PDT 24 |
Finished | Jul 19 06:13:56 PM PDT 24 |
Peak memory | 365396 kb |
Host | smart-87926efe-38fb-49c7-9d02-f81dca4bdd4b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569664918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2569664918 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3686191868 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 19057681306 ps |
CPU time | 2080.21 seconds |
Started | Jul 19 06:11:33 PM PDT 24 |
Finished | Jul 19 06:46:15 PM PDT 24 |
Peak memory | 371700 kb |
Host | smart-45ca56fd-d5cc-4c02-80bf-c9220425307e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686191868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.3686191868 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.1568225813 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 41058670 ps |
CPU time | 0.69 seconds |
Started | Jul 19 06:11:40 PM PDT 24 |
Finished | Jul 19 06:11:42 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-f462eed5-38b9-45de-b39e-2d256a1fe23b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568225813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.1568225813 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.3148517073 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 345312856945 ps |
CPU time | 2056.22 seconds |
Started | Jul 19 06:11:32 PM PDT 24 |
Finished | Jul 19 06:45:49 PM PDT 24 |
Peak memory | 203748 kb |
Host | smart-67a84ec4-aa1f-4a4a-96a1-6a8a917dc352 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148517073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .3148517073 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.2684136280 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 41966060146 ps |
CPU time | 797.09 seconds |
Started | Jul 19 06:11:32 PM PDT 24 |
Finished | Jul 19 06:24:50 PM PDT 24 |
Peak memory | 378648 kb |
Host | smart-2c2be76f-1c20-4ca7-8aeb-c845040d1a1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684136280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.2684136280 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.3012316349 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 32633289004 ps |
CPU time | 54.22 seconds |
Started | Jul 19 06:11:32 PM PDT 24 |
Finished | Jul 19 06:12:27 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-0fed0a7e-f6b2-4f0c-8f98-e32ea939a807 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012316349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.3012316349 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.3032703859 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 3141917568 ps |
CPU time | 141.17 seconds |
Started | Jul 19 06:11:32 PM PDT 24 |
Finished | Jul 19 06:13:53 PM PDT 24 |
Peak memory | 358376 kb |
Host | smart-1ce8a792-ac18-4180-b6a2-ce34879b95a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032703859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.3032703859 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2056100889 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 6328727448 ps |
CPU time | 131.44 seconds |
Started | Jul 19 06:11:41 PM PDT 24 |
Finished | Jul 19 06:13:53 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-6ca2a3b4-cb41-4411-afeb-4c159c92be0e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056100889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.2056100889 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.3020839665 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 21874047739 ps |
CPU time | 303.25 seconds |
Started | Jul 19 06:11:41 PM PDT 24 |
Finished | Jul 19 06:16:45 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-b7b986e5-5c87-4c0c-9c15-153e15d9e6c9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020839665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.3020839665 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.202932569 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 35826797626 ps |
CPU time | 1408.19 seconds |
Started | Jul 19 06:11:33 PM PDT 24 |
Finished | Jul 19 06:35:02 PM PDT 24 |
Peak memory | 377700 kb |
Host | smart-4c052aab-65df-481a-bf6e-d79097e0952f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202932569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip le_keys.202932569 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.2155419419 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 421894786 ps |
CPU time | 8.61 seconds |
Started | Jul 19 06:11:32 PM PDT 24 |
Finished | Jul 19 06:11:42 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-b6197179-8022-4faf-af4c-a87e953d61e4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155419419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.2155419419 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3898746910 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 14338275694 ps |
CPU time | 320.99 seconds |
Started | Jul 19 06:11:36 PM PDT 24 |
Finished | Jul 19 06:16:58 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-b3d575b0-a6ce-49b9-bff9-8c3dc6b7016b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898746910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.3898746910 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.2549243400 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 348222216 ps |
CPU time | 3.24 seconds |
Started | Jul 19 06:11:40 PM PDT 24 |
Finished | Jul 19 06:11:44 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-35a555d7-4b2a-4e3d-922b-7dd753736d1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549243400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2549243400 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.1769706838 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 46207884244 ps |
CPU time | 148.6 seconds |
Started | Jul 19 06:11:40 PM PDT 24 |
Finished | Jul 19 06:14:09 PM PDT 24 |
Peak memory | 300348 kb |
Host | smart-c69b09d6-1a27-4e0e-bc80-2b56d5c53c73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769706838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1769706838 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.485620815 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 1715443682 ps |
CPU time | 13.07 seconds |
Started | Jul 19 06:11:32 PM PDT 24 |
Finished | Jul 19 06:11:46 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-58af7c17-972d-4ce0-a988-58e745b4193d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485620815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.485620815 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.3979661293 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 87778989957 ps |
CPU time | 4683.87 seconds |
Started | Jul 19 06:11:40 PM PDT 24 |
Finished | Jul 19 07:29:45 PM PDT 24 |
Peak memory | 381240 kb |
Host | smart-79ec238b-5cb7-4814-bb66-de57a79d01fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979661293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.3979661293 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.4284075062 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 38315438581 ps |
CPU time | 264.46 seconds |
Started | Jul 19 06:11:35 PM PDT 24 |
Finished | Jul 19 06:16:00 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-5ce02d0a-de2b-4e32-b5f2-d69bfc44fa51 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284075062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.4284075062 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2278861392 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 2887053880 ps |
CPU time | 36.03 seconds |
Started | Jul 19 06:11:33 PM PDT 24 |
Finished | Jul 19 06:12:10 PM PDT 24 |
Peak memory | 284652 kb |
Host | smart-2b7e88c9-d383-49ab-b2f2-91e5062f7029 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278861392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2278861392 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3386065006 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 14704642294 ps |
CPU time | 1251.61 seconds |
Started | Jul 19 06:11:53 PM PDT 24 |
Finished | Jul 19 06:32:45 PM PDT 24 |
Peak memory | 375696 kb |
Host | smart-f4abf1a9-8aa3-47a1-8684-69fae0bc768c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386065006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.3386065006 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.2597339191 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 44225099 ps |
CPU time | 0.69 seconds |
Started | Jul 19 06:12:02 PM PDT 24 |
Finished | Jul 19 06:12:03 PM PDT 24 |
Peak memory | 202452 kb |
Host | smart-e4532a49-37ff-4c5e-a791-25d830bafb67 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597339191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2597339191 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.1700087827 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 897476557740 ps |
CPU time | 1650.38 seconds |
Started | Jul 19 06:11:48 PM PDT 24 |
Finished | Jul 19 06:39:19 PM PDT 24 |
Peak memory | 203392 kb |
Host | smart-86b146be-c70a-4ca6-981f-9f5c09aeade0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700087827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1700087827 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.585683864 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 5253729924 ps |
CPU time | 723.4 seconds |
Started | Jul 19 06:11:55 PM PDT 24 |
Finished | Jul 19 06:23:59 PM PDT 24 |
Peak memory | 374644 kb |
Host | smart-18da8084-55ff-43fc-8709-d25277e38276 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585683864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executabl e.585683864 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.3406812641 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 8850116052 ps |
CPU time | 56.39 seconds |
Started | Jul 19 06:11:55 PM PDT 24 |
Finished | Jul 19 06:12:52 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-29b54728-60ee-477a-9ee2-ad44db96a72e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406812641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.3406812641 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.1136832821 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 1440046446 ps |
CPU time | 111.49 seconds |
Started | Jul 19 06:11:48 PM PDT 24 |
Finished | Jul 19 06:13:40 PM PDT 24 |
Peak memory | 341908 kb |
Host | smart-0f05d55b-cdc8-4561-8c8e-ffab1e2a510a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136832821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.1136832821 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.1568747077 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 2374797207 ps |
CPU time | 75.29 seconds |
Started | Jul 19 06:12:02 PM PDT 24 |
Finished | Jul 19 06:13:18 PM PDT 24 |
Peak memory | 219256 kb |
Host | smart-b25c1fee-292b-4ee8-ae3f-2b23f928151f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568747077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.1568747077 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.337327563 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 89611528121 ps |
CPU time | 342.13 seconds |
Started | Jul 19 06:12:03 PM PDT 24 |
Finished | Jul 19 06:17:46 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-345ce8a3-3972-484f-bdfb-6163aa36b8f1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337327563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _mem_walk.337327563 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.4214194072 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 27085628606 ps |
CPU time | 1100.85 seconds |
Started | Jul 19 06:11:41 PM PDT 24 |
Finished | Jul 19 06:30:02 PM PDT 24 |
Peak memory | 373104 kb |
Host | smart-9023dc35-7e5c-48cb-9a11-fc470a3c6fc2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214194072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.4214194072 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.355294325 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 3402415650 ps |
CPU time | 13.2 seconds |
Started | Jul 19 06:11:47 PM PDT 24 |
Finished | Jul 19 06:12:00 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-abf8b933-8848-41a9-979a-3424b2530964 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355294325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s ram_ctrl_partial_access.355294325 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.709738364 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 22511137683 ps |
CPU time | 294.78 seconds |
Started | Jul 19 06:11:48 PM PDT 24 |
Finished | Jul 19 06:16:44 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-d03bdbc0-9aa9-40d6-ada5-28b58a6c6c64 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709738364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_partial_access_b2b.709738364 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.2127335037 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 3744173166 ps |
CPU time | 4.64 seconds |
Started | Jul 19 06:11:56 PM PDT 24 |
Finished | Jul 19 06:12:01 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-dd913a0b-cd71-4362-8c80-5049bc71c672 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127335037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2127335037 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.3195855326 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 24107348032 ps |
CPU time | 615.65 seconds |
Started | Jul 19 06:11:53 PM PDT 24 |
Finished | Jul 19 06:22:10 PM PDT 24 |
Peak memory | 374656 kb |
Host | smart-3d21bbe0-3600-4ecb-8854-c651d8c0a29f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195855326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3195855326 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.2889294575 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 4814821611 ps |
CPU time | 57.68 seconds |
Started | Jul 19 06:11:40 PM PDT 24 |
Finished | Jul 19 06:12:38 PM PDT 24 |
Peak memory | 293176 kb |
Host | smart-39616bdf-9dec-413d-adf7-d7d410d29238 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889294575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2889294575 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.4022910105 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 46963164317 ps |
CPU time | 1577.83 seconds |
Started | Jul 19 06:12:06 PM PDT 24 |
Finished | Jul 19 06:38:25 PM PDT 24 |
Peak memory | 377760 kb |
Host | smart-e94199ae-5332-4d1c-a9f5-c275fcc03a58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022910105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.4022910105 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2988153691 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 1137357700 ps |
CPU time | 41.69 seconds |
Started | Jul 19 06:12:01 PM PDT 24 |
Finished | Jul 19 06:12:43 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-367c945e-2faf-4c27-94bc-d561dd6537e8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2988153691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2988153691 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1985275004 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 5655320069 ps |
CPU time | 337.62 seconds |
Started | Jul 19 06:11:48 PM PDT 24 |
Finished | Jul 19 06:17:26 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-f23b2352-5731-49e3-843e-93c4c8536a60 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985275004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.1985275004 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.222773768 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 2800953586 ps |
CPU time | 7.32 seconds |
Started | Jul 19 06:11:48 PM PDT 24 |
Finished | Jul 19 06:11:56 PM PDT 24 |
Peak memory | 211272 kb |
Host | smart-c1cc30a4-3b9c-42f6-9e55-3e83f579d38e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222773768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.222773768 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1392376161 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 17026634509 ps |
CPU time | 1420.17 seconds |
Started | Jul 19 06:04:23 PM PDT 24 |
Finished | Jul 19 06:28:04 PM PDT 24 |
Peak memory | 374720 kb |
Host | smart-f6c25313-0f22-40ea-b095-27fbe8622bc9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392376161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.1392376161 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.1857272179 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 12948572 ps |
CPU time | 0.66 seconds |
Started | Jul 19 06:04:24 PM PDT 24 |
Finished | Jul 19 06:04:25 PM PDT 24 |
Peak memory | 202476 kb |
Host | smart-05ea22c8-46f6-4902-985b-913f9d59b8fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857272179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1857272179 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.1857265243 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 87877302214 ps |
CPU time | 932.08 seconds |
Started | Jul 19 06:04:22 PM PDT 24 |
Finished | Jul 19 06:19:55 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-48327c7a-63d5-4ace-8512-0186648cf2e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857265243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 1857265243 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.277665453 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 72574281159 ps |
CPU time | 843.11 seconds |
Started | Jul 19 06:04:22 PM PDT 24 |
Finished | Jul 19 06:18:25 PM PDT 24 |
Peak memory | 378812 kb |
Host | smart-f5534f16-8d87-40a0-94b4-17ab739f48df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277665453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable .277665453 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.920068381 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 10343894687 ps |
CPU time | 61.74 seconds |
Started | Jul 19 06:04:25 PM PDT 24 |
Finished | Jul 19 06:05:27 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-80ceb693-cabc-4403-ab90-9da4c88a1162 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920068381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca lation.920068381 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.3002353184 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 779732967 ps |
CPU time | 71.08 seconds |
Started | Jul 19 06:04:22 PM PDT 24 |
Finished | Jul 19 06:05:34 PM PDT 24 |
Peak memory | 308488 kb |
Host | smart-40f1507c-186e-4057-ba67-5ca6408f2528 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002353184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.3002353184 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1300076131 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 2557586263 ps |
CPU time | 74.53 seconds |
Started | Jul 19 06:04:23 PM PDT 24 |
Finished | Jul 19 06:05:38 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-1e6869e5-80f4-4696-b0c7-52c2b1d75d4e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300076131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.1300076131 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.604298902 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 8214945730 ps |
CPU time | 252.28 seconds |
Started | Jul 19 06:04:28 PM PDT 24 |
Finished | Jul 19 06:08:41 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-5b5a805a-55f3-4fb3-ac29-84906f1466cf |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604298902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ mem_walk.604298902 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.699641662 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 14421277243 ps |
CPU time | 1050.83 seconds |
Started | Jul 19 06:04:15 PM PDT 24 |
Finished | Jul 19 06:21:47 PM PDT 24 |
Peak memory | 380768 kb |
Host | smart-a6df9a86-9996-4d3b-9a8e-f0bebd476b63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699641662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl e_keys.699641662 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.2701591378 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 700128861 ps |
CPU time | 3.93 seconds |
Started | Jul 19 06:04:25 PM PDT 24 |
Finished | Jul 19 06:04:30 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-4cbf48c6-ae45-4d54-9e94-ea4dcf52685d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701591378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.2701591378 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1270681550 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 21985805034 ps |
CPU time | 527.77 seconds |
Started | Jul 19 06:04:23 PM PDT 24 |
Finished | Jul 19 06:13:11 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-eb026973-eb8f-438e-8422-6bfe4fac41af |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270681550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.1270681550 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.4191654744 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 3367295917 ps |
CPU time | 3.41 seconds |
Started | Jul 19 06:04:25 PM PDT 24 |
Finished | Jul 19 06:04:30 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-d1d4b4b8-b756-46b6-b1da-04ea38814f5a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191654744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4191654744 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.4240161842 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 6099825012 ps |
CPU time | 93.02 seconds |
Started | Jul 19 06:04:22 PM PDT 24 |
Finished | Jul 19 06:05:56 PM PDT 24 |
Peak memory | 308968 kb |
Host | smart-1e7991ae-2676-4ba4-8a08-fb732c2c432e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240161842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.4240161842 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.3579123869 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 688246928 ps |
CPU time | 2.55 seconds |
Started | Jul 19 06:04:23 PM PDT 24 |
Finished | Jul 19 06:04:26 PM PDT 24 |
Peak memory | 221912 kb |
Host | smart-61694141-1080-4387-b049-713e2f83c9f2 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579123869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3579123869 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.2921224718 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 1911860657 ps |
CPU time | 9.11 seconds |
Started | Jul 19 06:04:20 PM PDT 24 |
Finished | Jul 19 06:04:30 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-82582cf9-89d2-44b5-9152-01fc4847a3c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921224718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2921224718 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.2226470413 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 214534555674 ps |
CPU time | 4233.58 seconds |
Started | Jul 19 06:04:24 PM PDT 24 |
Finished | Jul 19 07:14:58 PM PDT 24 |
Peak memory | 380740 kb |
Host | smart-04d4a2d5-cde4-4769-99d3-59cf74126674 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226470413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.2226470413 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.20776040 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 3217707040 ps |
CPU time | 165.62 seconds |
Started | Jul 19 06:04:24 PM PDT 24 |
Finished | Jul 19 06:07:11 PM PDT 24 |
Peak memory | 361476 kb |
Host | smart-5cd4912a-ecf5-480a-b34a-9bf6a5ffbfe4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=20776040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.20776040 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2257509248 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 9246950221 ps |
CPU time | 296.84 seconds |
Started | Jul 19 06:04:24 PM PDT 24 |
Finished | Jul 19 06:09:22 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-c3d32fd1-2cde-4b33-8b10-319f02a4e0d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257509248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.2257509248 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.4063278942 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 771908001 ps |
CPU time | 38.38 seconds |
Started | Jul 19 06:04:24 PM PDT 24 |
Finished | Jul 19 06:05:03 PM PDT 24 |
Peak memory | 301008 kb |
Host | smart-63ba89e6-53fd-41b7-a627-8b84945f28ac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063278942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.4063278942 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.4252684344 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 9226370136 ps |
CPU time | 658.8 seconds |
Started | Jul 19 06:12:09 PM PDT 24 |
Finished | Jul 19 06:23:08 PM PDT 24 |
Peak memory | 367320 kb |
Host | smart-8133e9aa-cd8c-42c6-a622-8032acbb5b95 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252684344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.4252684344 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.561575899 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 33759468 ps |
CPU time | 0.64 seconds |
Started | Jul 19 06:12:11 PM PDT 24 |
Finished | Jul 19 06:12:12 PM PDT 24 |
Peak memory | 202352 kb |
Host | smart-6f904830-3562-4ead-842e-ba07ef79d94a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561575899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.561575899 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.2388119543 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 30666744033 ps |
CPU time | 2271.32 seconds |
Started | Jul 19 06:12:02 PM PDT 24 |
Finished | Jul 19 06:49:54 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-283fc9dd-1c9a-4d48-bc08-69aa1451cd4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388119543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .2388119543 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.1973184508 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 3693729986 ps |
CPU time | 341.73 seconds |
Started | Jul 19 06:12:10 PM PDT 24 |
Finished | Jul 19 06:17:53 PM PDT 24 |
Peak memory | 375624 kb |
Host | smart-837e79c1-6dbb-41a8-b027-e0c9394fae11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973184508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.1973184508 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.1094505860 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 33156003168 ps |
CPU time | 99.47 seconds |
Started | Jul 19 06:12:08 PM PDT 24 |
Finished | Jul 19 06:13:48 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-6c0b1fc1-3845-43dc-8bac-1754c401aeca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094505860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.1094505860 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.958040351 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 1476363489 ps |
CPU time | 25.33 seconds |
Started | Jul 19 06:12:06 PM PDT 24 |
Finished | Jul 19 06:12:31 PM PDT 24 |
Peak memory | 268272 kb |
Host | smart-8f8342d8-ca81-4eb5-9742-f13a71b338a3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958040351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.sram_ctrl_max_throughput.958040351 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2882486620 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 12532296095 ps |
CPU time | 81.64 seconds |
Started | Jul 19 06:12:11 PM PDT 24 |
Finished | Jul 19 06:13:33 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-36f188af-99d5-4249-8a42-802562969c57 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882486620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.2882486620 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.2203426861 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 7058371824 ps |
CPU time | 158.07 seconds |
Started | Jul 19 06:12:13 PM PDT 24 |
Finished | Jul 19 06:14:51 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-ab7ea9d7-3b06-4f04-b177-f369682b6ba7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203426861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr l_mem_walk.2203426861 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.3483394651 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 77996897742 ps |
CPU time | 1440.67 seconds |
Started | Jul 19 06:12:02 PM PDT 24 |
Finished | Jul 19 06:36:03 PM PDT 24 |
Peak memory | 379768 kb |
Host | smart-9dc2d3be-1d4f-4910-a5d4-013e15c31766 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483394651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.3483394651 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.404410694 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 2842415305 ps |
CPU time | 45.49 seconds |
Started | Jul 19 06:12:03 PM PDT 24 |
Finished | Jul 19 06:12:49 PM PDT 24 |
Peak memory | 280668 kb |
Host | smart-fad2ab01-54d4-4feb-8e48-da2357a32e59 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404410694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.404410694 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1836275894 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 4939364256 ps |
CPU time | 268.29 seconds |
Started | Jul 19 06:12:01 PM PDT 24 |
Finished | Jul 19 06:16:30 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-3f1d7b69-766c-47d6-b147-6f47522961d8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836275894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.1836275894 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.1829979927 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 2792062163 ps |
CPU time | 3.86 seconds |
Started | Jul 19 06:12:09 PM PDT 24 |
Finished | Jul 19 06:12:14 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-30984231-0ccc-4200-b903-543d6ebfb720 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829979927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1829979927 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.55750215 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 8678526504 ps |
CPU time | 277.39 seconds |
Started | Jul 19 06:12:11 PM PDT 24 |
Finished | Jul 19 06:16:49 PM PDT 24 |
Peak memory | 351280 kb |
Host | smart-182b3f0e-c4f8-40f8-a971-3b3801c04ec2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55750215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.55750215 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.3418064452 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 2365444230 ps |
CPU time | 95.25 seconds |
Started | Jul 19 06:12:04 PM PDT 24 |
Finished | Jul 19 06:13:39 PM PDT 24 |
Peak memory | 341936 kb |
Host | smart-26b30ddc-1bc8-4834-ba72-6063f7cd5533 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418064452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3418064452 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.3936628570 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 17027537549 ps |
CPU time | 947.9 seconds |
Started | Jul 19 06:12:10 PM PDT 24 |
Finished | Jul 19 06:27:59 PM PDT 24 |
Peak memory | 367572 kb |
Host | smart-e530528f-b098-4c20-bdb8-aa7e47614458 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936628570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.3936628570 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1698924529 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1312857763 ps |
CPU time | 35.6 seconds |
Started | Jul 19 06:12:09 PM PDT 24 |
Finished | Jul 19 06:12:45 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-fb469cb8-4bb8-49cd-8019-fd6c17e362c3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1698924529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1698924529 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1426066592 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 4786265484 ps |
CPU time | 288.62 seconds |
Started | Jul 19 06:12:02 PM PDT 24 |
Finished | Jul 19 06:16:52 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-73909497-53ba-4670-a648-960a554a9711 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426066592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.1426066592 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2773120845 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 812358570 ps |
CPU time | 138.45 seconds |
Started | Jul 19 06:12:09 PM PDT 24 |
Finished | Jul 19 06:14:28 PM PDT 24 |
Peak memory | 370496 kb |
Host | smart-026ebe51-1d91-42f0-9542-fd7400979e89 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773120845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.2773120845 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3176863981 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 15344444546 ps |
CPU time | 1124.12 seconds |
Started | Jul 19 06:12:20 PM PDT 24 |
Finished | Jul 19 06:31:05 PM PDT 24 |
Peak memory | 379756 kb |
Host | smart-fa4be692-c13a-403b-94a5-b9ba68668164 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176863981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.3176863981 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.2099023331 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 12600324 ps |
CPU time | 0.71 seconds |
Started | Jul 19 06:12:28 PM PDT 24 |
Finished | Jul 19 06:12:30 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-2eb6fe10-4bfc-4486-9a66-a0303b6aedb3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099023331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2099023331 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.821152715 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 27452603865 ps |
CPU time | 956.18 seconds |
Started | Jul 19 06:12:18 PM PDT 24 |
Finished | Jul 19 06:28:15 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-962ba71d-8cf8-45ed-81c1-d6d8a362b940 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821152715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection. 821152715 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.3538028829 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 21588240420 ps |
CPU time | 1263.75 seconds |
Started | Jul 19 06:12:27 PM PDT 24 |
Finished | Jul 19 06:33:31 PM PDT 24 |
Peak memory | 379792 kb |
Host | smart-4525bbb3-35af-4354-b9e1-77a144824003 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538028829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.3538028829 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.2244152835 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 1366319157 ps |
CPU time | 11.13 seconds |
Started | Jul 19 06:12:23 PM PDT 24 |
Finished | Jul 19 06:12:34 PM PDT 24 |
Peak memory | 235452 kb |
Host | smart-c3438ca3-62dc-4337-bef9-cd01357c172f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244152835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.2244152835 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.4155160927 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 1656813374 ps |
CPU time | 129.11 seconds |
Started | Jul 19 06:12:26 PM PDT 24 |
Finished | Jul 19 06:14:36 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-c665421b-b913-4368-bdbd-8d81060e7326 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155160927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.4155160927 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.2205103335 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 39840946335 ps |
CPU time | 339.83 seconds |
Started | Jul 19 06:12:30 PM PDT 24 |
Finished | Jul 19 06:18:10 PM PDT 24 |
Peak memory | 211840 kb |
Host | smart-d5ee7217-fef0-490a-8d73-296f82d23a02 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205103335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.2205103335 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.2032732539 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 133309387497 ps |
CPU time | 1758.76 seconds |
Started | Jul 19 06:12:27 PM PDT 24 |
Finished | Jul 19 06:41:47 PM PDT 24 |
Peak memory | 380812 kb |
Host | smart-e8cd8172-1125-4158-aa6b-b9742a2791b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032732539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.2032732539 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.2565462790 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 1650088671 ps |
CPU time | 108.56 seconds |
Started | Jul 19 06:12:22 PM PDT 24 |
Finished | Jul 19 06:14:11 PM PDT 24 |
Peak memory | 350024 kb |
Host | smart-1a3b62a5-1aba-498e-b512-dfb59cb12547 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565462790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.2565462790 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2625684298 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 14072929973 ps |
CPU time | 393.77 seconds |
Started | Jul 19 06:12:20 PM PDT 24 |
Finished | Jul 19 06:18:55 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-6487d4f1-6bb2-4558-8c40-ffb54a97d59b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625684298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.2625684298 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.1591189091 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 1608915571 ps |
CPU time | 3.42 seconds |
Started | Jul 19 06:12:25 PM PDT 24 |
Finished | Jul 19 06:12:29 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-4d5b16df-2144-4153-b603-e026bb96b5aa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591189091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1591189091 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.1818658698 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 7992351521 ps |
CPU time | 81.21 seconds |
Started | Jul 19 06:12:27 PM PDT 24 |
Finished | Jul 19 06:13:48 PM PDT 24 |
Peak memory | 310112 kb |
Host | smart-40825c9a-30bc-476e-bba0-6a7d9d1cc4a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818658698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1818658698 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.4201263439 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 819898186 ps |
CPU time | 184.99 seconds |
Started | Jul 19 06:12:10 PM PDT 24 |
Finished | Jul 19 06:15:16 PM PDT 24 |
Peak memory | 368412 kb |
Host | smart-9813e661-8c05-4926-9def-4b739f2df749 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201263439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4201263439 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.2173674416 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 85542017044 ps |
CPU time | 1653.67 seconds |
Started | Jul 19 06:12:26 PM PDT 24 |
Finished | Jul 19 06:40:00 PM PDT 24 |
Peak memory | 372856 kb |
Host | smart-bc6456f3-1e98-48b9-b4f3-899f7359c4f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173674416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.2173674416 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1694823797 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 1205876013 ps |
CPU time | 48.86 seconds |
Started | Jul 19 06:12:27 PM PDT 24 |
Finished | Jul 19 06:13:17 PM PDT 24 |
Peak memory | 219012 kb |
Host | smart-657c289b-ff6a-4daa-bb6b-97672c5c5d35 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1694823797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1694823797 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.889520419 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 7094969862 ps |
CPU time | 148.31 seconds |
Started | Jul 19 06:12:20 PM PDT 24 |
Finished | Jul 19 06:14:48 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-4d3aaaff-371c-408c-96e1-bad0dfa0e781 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889520419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_stress_pipeline.889520419 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1626429871 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 2707241289 ps |
CPU time | 155.63 seconds |
Started | Jul 19 06:12:22 PM PDT 24 |
Finished | Jul 19 06:14:58 PM PDT 24 |
Peak memory | 372708 kb |
Host | smart-ed0b75af-3df9-4af8-8ba0-72f736c0add8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626429871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1626429871 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3779808040 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 6520269267 ps |
CPU time | 137.26 seconds |
Started | Jul 19 06:12:35 PM PDT 24 |
Finished | Jul 19 06:14:53 PM PDT 24 |
Peak memory | 349208 kb |
Host | smart-bbe2eddc-bc6d-4d76-bba3-b418f4ea74e0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779808040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.3779808040 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.49244571 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 24147606 ps |
CPU time | 0.66 seconds |
Started | Jul 19 06:12:44 PM PDT 24 |
Finished | Jul 19 06:12:45 PM PDT 24 |
Peak memory | 202488 kb |
Host | smart-6b2427d2-a6b1-4cb1-a730-c659fc7b3167 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49244571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_alert_test.49244571 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.1917112249 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 441930306095 ps |
CPU time | 2035.53 seconds |
Started | Jul 19 06:12:36 PM PDT 24 |
Finished | Jul 19 06:46:33 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-f66b9443-6a82-4c68-8d1b-2fcdeccebddb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917112249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .1917112249 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.3037322702 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 61509065633 ps |
CPU time | 510 seconds |
Started | Jul 19 06:12:35 PM PDT 24 |
Finished | Jul 19 06:21:05 PM PDT 24 |
Peak memory | 378884 kb |
Host | smart-dab42c43-c979-4a58-8935-1b37fcb78242 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037322702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.3037322702 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.2611683356 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 7838129879 ps |
CPU time | 14.01 seconds |
Started | Jul 19 06:12:39 PM PDT 24 |
Finished | Jul 19 06:12:53 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-489ae9ed-b814-4735-9a7f-2ca8476718a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611683356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.2611683356 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.24291268 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 908755231 ps |
CPU time | 22.91 seconds |
Started | Jul 19 06:12:38 PM PDT 24 |
Finished | Jul 19 06:13:02 PM PDT 24 |
Peak memory | 270344 kb |
Host | smart-06a13f1e-af16-46d8-85f3-abfdb4a8231b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24291268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.sram_ctrl_max_throughput.24291268 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3467135409 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 11122720071 ps |
CPU time | 173.22 seconds |
Started | Jul 19 06:12:45 PM PDT 24 |
Finished | Jul 19 06:15:38 PM PDT 24 |
Peak memory | 219276 kb |
Host | smart-accd5228-f74b-4913-afe4-df8efcea5b2f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467135409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.3467135409 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.1697203964 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 10348492927 ps |
CPU time | 179.88 seconds |
Started | Jul 19 06:12:44 PM PDT 24 |
Finished | Jul 19 06:15:44 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-97459d97-5874-4d6f-bee4-c233ddb71e60 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697203964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.1697203964 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.3434072461 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 39759509940 ps |
CPU time | 130.98 seconds |
Started | Jul 19 06:12:36 PM PDT 24 |
Finished | Jul 19 06:14:48 PM PDT 24 |
Peak memory | 306644 kb |
Host | smart-2202f7b1-fe2f-429b-86c4-f3d7418d9bd7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434072461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.3434072461 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.960653819 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 11879580312 ps |
CPU time | 7.45 seconds |
Started | Jul 19 06:12:37 PM PDT 24 |
Finished | Jul 19 06:12:45 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-6799ec87-99e4-497c-ba97-ae74b1e0a755 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960653819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s ram_ctrl_partial_access.960653819 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.28996216 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 39973141470 ps |
CPU time | 439.21 seconds |
Started | Jul 19 06:12:36 PM PDT 24 |
Finished | Jul 19 06:19:56 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-686e4842-ebd5-4dea-b3df-9b3c3796031d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28996216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_partial_access_b2b.28996216 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.2551046845 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 693488529 ps |
CPU time | 3.49 seconds |
Started | Jul 19 06:12:43 PM PDT 24 |
Finished | Jul 19 06:12:47 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-aa031f76-8247-4c30-9de9-8b39457f7a9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551046845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2551046845 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.400704839 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 4958818902 ps |
CPU time | 833.31 seconds |
Started | Jul 19 06:12:44 PM PDT 24 |
Finished | Jul 19 06:26:38 PM PDT 24 |
Peak memory | 374720 kb |
Host | smart-40cc538f-505d-48d3-907a-a0840eff6b1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400704839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.400704839 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.1196716776 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 7781978304 ps |
CPU time | 19.48 seconds |
Started | Jul 19 06:12:35 PM PDT 24 |
Finished | Jul 19 06:12:55 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-cee1cfa6-a079-4346-8839-5c1c6f209f50 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196716776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1196716776 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.1020120034 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 150406794156 ps |
CPU time | 6068.13 seconds |
Started | Jul 19 06:12:43 PM PDT 24 |
Finished | Jul 19 07:53:53 PM PDT 24 |
Peak memory | 380768 kb |
Host | smart-8f30b84f-0c5a-42d9-ac98-879b6371c383 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020120034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1020120034 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1833730989 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 737359898 ps |
CPU time | 19.96 seconds |
Started | Jul 19 06:12:43 PM PDT 24 |
Finished | Jul 19 06:13:04 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-58a8296b-57b7-42d6-9ce0-636f08ceefa5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1833730989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1833730989 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1161338982 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 46185820718 ps |
CPU time | 350.98 seconds |
Started | Jul 19 06:12:34 PM PDT 24 |
Finished | Jul 19 06:18:25 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-cd8a46ee-2b52-4b91-a550-aeaca44220c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161338982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1161338982 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4049950531 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 726611177 ps |
CPU time | 38.17 seconds |
Started | Jul 19 06:12:35 PM PDT 24 |
Finished | Jul 19 06:13:14 PM PDT 24 |
Peak memory | 284576 kb |
Host | smart-0a41a949-998b-44a1-a354-c26b8053f7d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049950531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.4049950531 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2470087266 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 27021452703 ps |
CPU time | 525.16 seconds |
Started | Jul 19 06:12:53 PM PDT 24 |
Finished | Jul 19 06:21:38 PM PDT 24 |
Peak memory | 375660 kb |
Host | smart-1ceef5cf-aada-4725-be55-7c9de66f4cd8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470087266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.2470087266 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.2889737606 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 96971771 ps |
CPU time | 0.65 seconds |
Started | Jul 19 06:12:58 PM PDT 24 |
Finished | Jul 19 06:13:00 PM PDT 24 |
Peak memory | 202592 kb |
Host | smart-ea2fb26d-6357-4329-af26-2dca0a845e9a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889737606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2889737606 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.4215324503 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 110892879024 ps |
CPU time | 1233.22 seconds |
Started | Jul 19 06:12:54 PM PDT 24 |
Finished | Jul 19 06:33:28 PM PDT 24 |
Peak memory | 203500 kb |
Host | smart-8c651c61-0a1a-42a2-9115-1acc5aecc97d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215324503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .4215324503 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.734097436 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 2500089786 ps |
CPU time | 543.7 seconds |
Started | Jul 19 06:12:51 PM PDT 24 |
Finished | Jul 19 06:21:55 PM PDT 24 |
Peak memory | 375692 kb |
Host | smart-080d2fcc-439a-4615-b088-364a8d89789b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734097436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl e.734097436 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.451951230 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 54766108154 ps |
CPU time | 87.2 seconds |
Started | Jul 19 06:12:52 PM PDT 24 |
Finished | Jul 19 06:14:20 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-62c08d01-7693-48c5-9419-fa34129c8c97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451951230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc alation.451951230 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.2347606368 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 767050725 ps |
CPU time | 126.13 seconds |
Started | Jul 19 06:12:54 PM PDT 24 |
Finished | Jul 19 06:15:00 PM PDT 24 |
Peak memory | 361268 kb |
Host | smart-04116624-673d-4e4d-9e5f-6dfcafd42e58 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347606368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.2347606368 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2945447267 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 10294928922 ps |
CPU time | 88.24 seconds |
Started | Jul 19 06:12:57 PM PDT 24 |
Finished | Jul 19 06:14:27 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-044aeac3-90f9-4067-9490-651bc6c36e26 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945447267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.2945447267 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.2905754999 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 10964978104 ps |
CPU time | 142.13 seconds |
Started | Jul 19 06:12:57 PM PDT 24 |
Finished | Jul 19 06:15:20 PM PDT 24 |
Peak memory | 212024 kb |
Host | smart-08ac8986-7cf9-4e02-b1f6-79bc88fe5fd3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905754999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.2905754999 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.3448166149 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 49459711461 ps |
CPU time | 852.12 seconds |
Started | Jul 19 06:12:49 PM PDT 24 |
Finished | Jul 19 06:27:01 PM PDT 24 |
Peak memory | 380544 kb |
Host | smart-1749fe46-9164-491c-a2a0-c04227c8c8a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448166149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.3448166149 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.1181071739 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 2034451455 ps |
CPU time | 19.92 seconds |
Started | Jul 19 06:12:51 PM PDT 24 |
Finished | Jul 19 06:13:11 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-32d14b0f-e462-4169-b19f-73d43c9a5a1d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181071739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.1181071739 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.131791887 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 6488757269 ps |
CPU time | 264.31 seconds |
Started | Jul 19 06:12:50 PM PDT 24 |
Finished | Jul 19 06:17:15 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-6fc5acbd-3162-4b8e-89a6-ea216df12d1a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131791887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.sram_ctrl_partial_access_b2b.131791887 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.983529365 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 352015558 ps |
CPU time | 3.31 seconds |
Started | Jul 19 06:12:50 PM PDT 24 |
Finished | Jul 19 06:12:54 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-05763520-948a-4659-bc46-7740a4a150fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983529365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.983529365 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.1694324327 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 17324895384 ps |
CPU time | 302.63 seconds |
Started | Jul 19 06:12:53 PM PDT 24 |
Finished | Jul 19 06:17:57 PM PDT 24 |
Peak memory | 376712 kb |
Host | smart-74538f29-0390-4e04-b7d1-27ce2b98fd47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694324327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1694324327 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.645053249 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 3000155122 ps |
CPU time | 39.84 seconds |
Started | Jul 19 06:12:51 PM PDT 24 |
Finished | Jul 19 06:13:31 PM PDT 24 |
Peak memory | 280520 kb |
Host | smart-dd5995ee-246a-4d55-9e95-086bd0b91c8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645053249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.645053249 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.2457758310 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 1199446780078 ps |
CPU time | 4703.8 seconds |
Started | Jul 19 06:12:57 PM PDT 24 |
Finished | Jul 19 07:31:22 PM PDT 24 |
Peak memory | 383920 kb |
Host | smart-f04c023e-ee75-4fb9-a1f9-af8fa4dca8d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457758310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.2457758310 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3209355468 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 1415032007 ps |
CPU time | 11.84 seconds |
Started | Jul 19 06:12:59 PM PDT 24 |
Finished | Jul 19 06:13:12 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-cfdaa583-3b80-4023-a720-b7a7fcdab8e2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3209355468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3209355468 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.4185477040 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 10060208712 ps |
CPU time | 159.42 seconds |
Started | Jul 19 06:12:54 PM PDT 24 |
Finished | Jul 19 06:15:34 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-27765b72-04d3-4633-a098-65895f81a4f7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185477040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.4185477040 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.578524739 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 2851424767 ps |
CPU time | 10.3 seconds |
Started | Jul 19 06:12:52 PM PDT 24 |
Finished | Jul 19 06:13:03 PM PDT 24 |
Peak memory | 227132 kb |
Host | smart-a191b3fa-c16c-458b-935d-de7cf6346867 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578524739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_throughput_w_partial_write.578524739 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.626458130 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 14312964106 ps |
CPU time | 1390.67 seconds |
Started | Jul 19 06:13:06 PM PDT 24 |
Finished | Jul 19 06:36:18 PM PDT 24 |
Peak memory | 378716 kb |
Host | smart-f0f0e590-1e90-40f9-b430-e0bfb67e63c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626458130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 44.sram_ctrl_access_during_key_req.626458130 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.4191946743 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 78425099 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:13:24 PM PDT 24 |
Finished | Jul 19 06:13:25 PM PDT 24 |
Peak memory | 202600 kb |
Host | smart-646d4246-6cb2-42ba-876e-fe9cee0b1b02 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191946743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.4191946743 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.582438170 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 19031828228 ps |
CPU time | 770.01 seconds |
Started | Jul 19 06:12:57 PM PDT 24 |
Finished | Jul 19 06:25:49 PM PDT 24 |
Peak memory | 203636 kb |
Host | smart-f12a4d6c-79aa-4aea-bd71-ac5b5b9459da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582438170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection. 582438170 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.3481247570 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 23172691011 ps |
CPU time | 1645.11 seconds |
Started | Jul 19 06:13:06 PM PDT 24 |
Finished | Jul 19 06:40:32 PM PDT 24 |
Peak memory | 378804 kb |
Host | smart-d016ca75-2256-4f99-851f-346ed783c741 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481247570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.3481247570 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.2591714877 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 47046916684 ps |
CPU time | 84.8 seconds |
Started | Jul 19 06:13:05 PM PDT 24 |
Finished | Jul 19 06:14:31 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-fd04c97a-2989-4cec-8ed9-71b666994810 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591714877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.2591714877 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.562840005 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 2942700903 ps |
CPU time | 27.84 seconds |
Started | Jul 19 06:13:05 PM PDT 24 |
Finished | Jul 19 06:13:34 PM PDT 24 |
Peak memory | 268228 kb |
Host | smart-c424d16e-8545-4d13-969b-70fa66d221a3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562840005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.sram_ctrl_max_throughput.562840005 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1223290089 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 958764027 ps |
CPU time | 73.22 seconds |
Started | Jul 19 06:13:11 PM PDT 24 |
Finished | Jul 19 06:14:25 PM PDT 24 |
Peak memory | 219168 kb |
Host | smart-ccbd8c06-5b3c-432d-915d-a313e2da9003 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223290089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.1223290089 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.4214320478 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 17936691189 ps |
CPU time | 132.66 seconds |
Started | Jul 19 06:13:18 PM PDT 24 |
Finished | Jul 19 06:15:31 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-dd2bf9d1-fa1d-4f01-bd9b-a0e534559857 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214320478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.4214320478 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.527758107 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 33598346671 ps |
CPU time | 934.57 seconds |
Started | Jul 19 06:13:00 PM PDT 24 |
Finished | Jul 19 06:28:35 PM PDT 24 |
Peak memory | 374540 kb |
Host | smart-18e14f6e-6dc3-4102-85fb-5866415ea65e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527758107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multip le_keys.527758107 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.2367181238 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1584108959 ps |
CPU time | 22.84 seconds |
Started | Jul 19 06:13:10 PM PDT 24 |
Finished | Jul 19 06:13:34 PM PDT 24 |
Peak memory | 256436 kb |
Host | smart-247bbbfb-37d5-4a5e-a1d6-1ac8ae8180f9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367181238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.2367181238 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1869318771 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 3339566361 ps |
CPU time | 179.7 seconds |
Started | Jul 19 06:13:07 PM PDT 24 |
Finished | Jul 19 06:16:07 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-45a44335-dc61-429e-8c6c-3979da511ebd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869318771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.1869318771 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.2991631320 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 426919252 ps |
CPU time | 3.13 seconds |
Started | Jul 19 06:13:12 PM PDT 24 |
Finished | Jul 19 06:13:16 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-085dde08-51e8-4709-8448-1fb2fce7b24b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991631320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.2991631320 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.1347323143 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 3962083875 ps |
CPU time | 299.59 seconds |
Started | Jul 19 06:13:13 PM PDT 24 |
Finished | Jul 19 06:18:13 PM PDT 24 |
Peak memory | 350044 kb |
Host | smart-37ff1854-47f4-4daa-808b-3b03134cfc72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347323143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1347323143 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.530890703 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 635335731 ps |
CPU time | 26.17 seconds |
Started | Jul 19 06:12:57 PM PDT 24 |
Finished | Jul 19 06:13:24 PM PDT 24 |
Peak memory | 260264 kb |
Host | smart-c78b8727-9f17-48fa-9899-f4b47593c764 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530890703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.530890703 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.355637247 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 126789213969 ps |
CPU time | 4845.17 seconds |
Started | Jul 19 06:13:13 PM PDT 24 |
Finished | Jul 19 07:33:59 PM PDT 24 |
Peak memory | 381844 kb |
Host | smart-9db1c5f8-400e-41f7-9649-06dbf6a010b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355637247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_stress_all.355637247 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1698443287 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 1028088370 ps |
CPU time | 8.1 seconds |
Started | Jul 19 06:13:13 PM PDT 24 |
Finished | Jul 19 06:13:22 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-d68f338d-2551-4f0d-b068-62e6b37e0f62 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1698443287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1698443287 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3536434685 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 5169389429 ps |
CPU time | 267.94 seconds |
Started | Jul 19 06:13:07 PM PDT 24 |
Finished | Jul 19 06:17:35 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-11283c9a-d32f-4f90-b606-a99c2e5cf25a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536434685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.3536434685 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1887991180 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 1415023256 ps |
CPU time | 8.5 seconds |
Started | Jul 19 06:13:06 PM PDT 24 |
Finished | Jul 19 06:13:15 PM PDT 24 |
Peak memory | 219268 kb |
Host | smart-4b83273b-f9ee-4bed-bfc2-96d4387d5c6c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887991180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1887991180 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3778229028 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 47955575979 ps |
CPU time | 918.57 seconds |
Started | Jul 19 06:13:31 PM PDT 24 |
Finished | Jul 19 06:28:50 PM PDT 24 |
Peak memory | 374668 kb |
Host | smart-761f484b-a8bc-45de-abf9-44f6429fc7ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778229028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.3778229028 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.4095817572 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 69624501 ps |
CPU time | 0.63 seconds |
Started | Jul 19 06:13:35 PM PDT 24 |
Finished | Jul 19 06:13:36 PM PDT 24 |
Peak memory | 202484 kb |
Host | smart-e45100ef-d1cc-4c6f-8074-60a4e62af564 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095817572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.4095817572 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.2328036832 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 257245054107 ps |
CPU time | 1119.41 seconds |
Started | Jul 19 06:13:25 PM PDT 24 |
Finished | Jul 19 06:32:05 PM PDT 24 |
Peak memory | 203596 kb |
Host | smart-a5ee81fe-8dcd-487b-af00-a428c0232bda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328036832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .2328036832 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.1389288753 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 128976319262 ps |
CPU time | 1237.47 seconds |
Started | Jul 19 06:13:34 PM PDT 24 |
Finished | Jul 19 06:34:12 PM PDT 24 |
Peak memory | 379740 kb |
Host | smart-cbebe419-2a4a-47de-acc5-d03926955794 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389288753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.1389288753 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.1747667870 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 65774831849 ps |
CPU time | 110.9 seconds |
Started | Jul 19 06:13:31 PM PDT 24 |
Finished | Jul 19 06:15:23 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-0770a563-a8bd-4485-8348-f4b1af58422d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747667870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.1747667870 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.3447940545 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 833734837 ps |
CPU time | 29.17 seconds |
Started | Jul 19 06:13:23 PM PDT 24 |
Finished | Jul 19 06:13:52 PM PDT 24 |
Peak memory | 270316 kb |
Host | smart-ca0dca4b-7571-4a37-bcfb-b591c2957c54 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447940545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.3447940545 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3362040066 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 6363229424 ps |
CPU time | 128.68 seconds |
Started | Jul 19 06:13:32 PM PDT 24 |
Finished | Jul 19 06:15:41 PM PDT 24 |
Peak memory | 219260 kb |
Host | smart-1f2df674-017b-4e2f-8f90-31674428353d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362040066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.3362040066 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.3996394949 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 8234675377 ps |
CPU time | 121.78 seconds |
Started | Jul 19 06:13:34 PM PDT 24 |
Finished | Jul 19 06:15:36 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-ca61b531-0214-4899-98d9-921fa35effd7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996394949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.3996394949 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.824342450 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 16746726100 ps |
CPU time | 595.1 seconds |
Started | Jul 19 06:13:24 PM PDT 24 |
Finished | Jul 19 06:23:20 PM PDT 24 |
Peak memory | 359180 kb |
Host | smart-e5fb0f16-7281-423e-984b-3e8b4cfce1d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824342450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip le_keys.824342450 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.744329683 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 1804365157 ps |
CPU time | 154.24 seconds |
Started | Jul 19 06:13:23 PM PDT 24 |
Finished | Jul 19 06:15:58 PM PDT 24 |
Peak memory | 369436 kb |
Host | smart-46bf844f-be95-4eaf-9cd9-d5ec870387e6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744329683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.s ram_ctrl_partial_access.744329683 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.128728779 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 39632245187 ps |
CPU time | 595.44 seconds |
Started | Jul 19 06:13:22 PM PDT 24 |
Finished | Jul 19 06:23:18 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-1b72cab1-a6f4-41a8-9891-7a6e09d73dea |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128728779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.sram_ctrl_partial_access_b2b.128728779 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.412651834 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 6686453048 ps |
CPU time | 4.26 seconds |
Started | Jul 19 06:13:32 PM PDT 24 |
Finished | Jul 19 06:13:37 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-de0dc1f3-bf43-4648-ba7d-f8c4cbf6d7c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412651834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.412651834 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.524926893 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 104469278941 ps |
CPU time | 717.01 seconds |
Started | Jul 19 06:13:32 PM PDT 24 |
Finished | Jul 19 06:25:30 PM PDT 24 |
Peak memory | 372620 kb |
Host | smart-11cd1c30-e0eb-4bb1-8e93-4dfbb0568cb7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524926893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.524926893 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.1015597847 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 802669673 ps |
CPU time | 140.55 seconds |
Started | Jul 19 06:13:27 PM PDT 24 |
Finished | Jul 19 06:15:48 PM PDT 24 |
Peak memory | 370432 kb |
Host | smart-3d31151f-8ef5-47f9-810d-046bdb1f08b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015597847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1015597847 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.7169141 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 101153068565 ps |
CPU time | 6905.22 seconds |
Started | Jul 19 06:13:32 PM PDT 24 |
Finished | Jul 19 08:08:39 PM PDT 24 |
Peak memory | 378792 kb |
Host | smart-9c255f97-b295-4881-bce0-d82b6687d572 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7169141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_stress_all.7169141 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.670187607 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 7018878480 ps |
CPU time | 60.48 seconds |
Started | Jul 19 06:13:32 PM PDT 24 |
Finished | Jul 19 06:14:33 PM PDT 24 |
Peak memory | 256760 kb |
Host | smart-9bcada1d-3f24-495c-9841-4e51dd93294b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=670187607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.670187607 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3326913970 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 3495937953 ps |
CPU time | 254.05 seconds |
Started | Jul 19 06:13:23 PM PDT 24 |
Finished | Jul 19 06:17:38 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-51822891-070d-4187-943a-fa39923d5ef5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326913970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.3326913970 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2826591876 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 1105196576 ps |
CPU time | 7.07 seconds |
Started | Jul 19 06:13:33 PM PDT 24 |
Finished | Jul 19 06:13:40 PM PDT 24 |
Peak memory | 216768 kb |
Host | smart-cefc71ce-e540-41a7-a416-dd1f8617b8e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826591876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2826591876 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1643877708 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 8312090664 ps |
CPU time | 741.2 seconds |
Started | Jul 19 06:13:46 PM PDT 24 |
Finished | Jul 19 06:26:08 PM PDT 24 |
Peak memory | 378996 kb |
Host | smart-f31c595a-1afa-48fb-8c27-c9a1f12d81cc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643877708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.1643877708 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.2408747098 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 17869101 ps |
CPU time | 0.67 seconds |
Started | Jul 19 06:13:50 PM PDT 24 |
Finished | Jul 19 06:13:51 PM PDT 24 |
Peak memory | 202460 kb |
Host | smart-3031777a-f86f-4c6a-a201-b03684e8e342 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408747098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.2408747098 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.3793273773 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 79999456282 ps |
CPU time | 1507.43 seconds |
Started | Jul 19 06:13:46 PM PDT 24 |
Finished | Jul 19 06:38:55 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-eb84ead6-24eb-48f8-a2e2-48c835033894 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793273773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .3793273773 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.3968074160 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 25250942332 ps |
CPU time | 1083.66 seconds |
Started | Jul 19 06:13:46 PM PDT 24 |
Finished | Jul 19 06:31:51 PM PDT 24 |
Peak memory | 361568 kb |
Host | smart-1332e7cf-1371-4e59-b13b-c9d7de3b749f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968074160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.3968074160 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.2438264878 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 19653497912 ps |
CPU time | 29.41 seconds |
Started | Jul 19 06:13:44 PM PDT 24 |
Finished | Jul 19 06:14:14 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-4c9e08e3-8896-43d8-a5a3-f0dab326cc4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438264878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.2438264878 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.2124600196 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 12386502019 ps |
CPU time | 78.46 seconds |
Started | Jul 19 06:13:40 PM PDT 24 |
Finished | Jul 19 06:14:59 PM PDT 24 |
Peak memory | 333908 kb |
Host | smart-a302b8bb-9425-43c4-b985-03e9e71d5dbb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124600196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.2124600196 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3343735254 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 2950878684 ps |
CPU time | 90.1 seconds |
Started | Jul 19 06:13:49 PM PDT 24 |
Finished | Jul 19 06:15:20 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-469a14f9-b52f-485a-bce5-e86c610887c0 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343735254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.3343735254 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.3945182234 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 5361132276 ps |
CPU time | 322.58 seconds |
Started | Jul 19 06:13:49 PM PDT 24 |
Finished | Jul 19 06:19:12 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-c501d12b-2c32-450f-8bcb-7ca51319ea55 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945182234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.3945182234 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.3033763013 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 23463763952 ps |
CPU time | 1025.1 seconds |
Started | Jul 19 06:13:41 PM PDT 24 |
Finished | Jul 19 06:30:46 PM PDT 24 |
Peak memory | 378768 kb |
Host | smart-63e40dd2-ede8-42d8-9310-627cbb9412e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033763013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.3033763013 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.434802747 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 3553824987 ps |
CPU time | 22.6 seconds |
Started | Jul 19 06:13:47 PM PDT 24 |
Finished | Jul 19 06:14:10 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-aee11566-8af1-4d98-ad13-121e64b3352d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434802747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s ram_ctrl_partial_access.434802747 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1771434303 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 11637229186 ps |
CPU time | 291.51 seconds |
Started | Jul 19 06:13:46 PM PDT 24 |
Finished | Jul 19 06:18:37 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-43413718-792c-4fdb-91a6-6f4669f3ae06 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771434303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.1771434303 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.2931272130 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 1400424374 ps |
CPU time | 3.36 seconds |
Started | Jul 19 06:13:49 PM PDT 24 |
Finished | Jul 19 06:13:53 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-eeb830a5-5e64-4a0f-9b0d-ad1fae8ec72f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931272130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2931272130 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.3395031457 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 55592163686 ps |
CPU time | 542.26 seconds |
Started | Jul 19 06:13:46 PM PDT 24 |
Finished | Jul 19 06:22:49 PM PDT 24 |
Peak memory | 355216 kb |
Host | smart-b54cd47b-9216-42ea-ac71-4cfb36a93d67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395031457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3395031457 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.3529515212 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 3837776101 ps |
CPU time | 46.57 seconds |
Started | Jul 19 06:13:33 PM PDT 24 |
Finished | Jul 19 06:14:20 PM PDT 24 |
Peak memory | 290744 kb |
Host | smart-73dae0ee-b2a9-42d6-80bb-7199a7b6bbbb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529515212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3529515212 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.3525838965 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 16582457482 ps |
CPU time | 3678.02 seconds |
Started | Jul 19 06:13:49 PM PDT 24 |
Finished | Jul 19 07:15:08 PM PDT 24 |
Peak memory | 382900 kb |
Host | smart-3cf88cba-71f4-482a-9361-5f4150fc7a87 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525838965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.3525838965 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3615256505 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 4259656028 ps |
CPU time | 25.09 seconds |
Started | Jul 19 06:13:50 PM PDT 24 |
Finished | Jul 19 06:14:15 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-f7c9923c-0f3e-4ca2-b9ff-870c3f1b3c71 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3615256505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3615256505 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3598005777 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 3325213456 ps |
CPU time | 223.44 seconds |
Started | Jul 19 06:13:47 PM PDT 24 |
Finished | Jul 19 06:17:31 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-91eb5392-dd43-475d-87ed-3c8011249504 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598005777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.3598005777 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2070957202 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 688354496 ps |
CPU time | 7.75 seconds |
Started | Jul 19 06:13:42 PM PDT 24 |
Finished | Jul 19 06:13:50 PM PDT 24 |
Peak memory | 219216 kb |
Host | smart-baec3209-f1ee-44f5-b0fc-1b726ac5fb2e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070957202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2070957202 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2779169718 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 44897582885 ps |
CPU time | 709.75 seconds |
Started | Jul 19 06:14:00 PM PDT 24 |
Finished | Jul 19 06:25:50 PM PDT 24 |
Peak memory | 373608 kb |
Host | smart-e3a4e738-a431-45b2-9c03-d739ff245065 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779169718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.2779169718 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.3890080328 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 28767105 ps |
CPU time | 0.64 seconds |
Started | Jul 19 06:14:05 PM PDT 24 |
Finished | Jul 19 06:14:06 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-7f7ab4b6-547f-4924-a114-cc0dffca683a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890080328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3890080328 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.1170479949 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 44937227258 ps |
CPU time | 845.51 seconds |
Started | Jul 19 06:13:52 PM PDT 24 |
Finished | Jul 19 06:27:58 PM PDT 24 |
Peak memory | 203472 kb |
Host | smart-53db39cd-a962-426e-aed1-20bb32dbd281 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170479949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .1170479949 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.4108579076 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 16106588932 ps |
CPU time | 361.25 seconds |
Started | Jul 19 06:14:06 PM PDT 24 |
Finished | Jul 19 06:20:08 PM PDT 24 |
Peak memory | 352112 kb |
Host | smart-375487a8-9828-4306-8d1c-2846d889d825 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108579076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.4108579076 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.3132957968 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 12402663255 ps |
CPU time | 72.43 seconds |
Started | Jul 19 06:13:57 PM PDT 24 |
Finished | Jul 19 06:15:10 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-bc33f91f-0c29-4028-8dd0-de1e13537199 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132957968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.3132957968 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.4172155568 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 1367936111 ps |
CPU time | 10.5 seconds |
Started | Jul 19 06:13:57 PM PDT 24 |
Finished | Jul 19 06:14:08 PM PDT 24 |
Peak memory | 235512 kb |
Host | smart-634be64b-48d0-45ee-8b57-808fb4bfde2c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172155568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.4172155568 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2162783729 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 32537736376 ps |
CPU time | 151.96 seconds |
Started | Jul 19 06:14:05 PM PDT 24 |
Finished | Jul 19 06:16:37 PM PDT 24 |
Peak memory | 211332 kb |
Host | smart-7ee2b4cc-fa4a-46f0-9566-6cee8383b339 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162783729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.2162783729 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.2931614368 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 5259957355 ps |
CPU time | 296.89 seconds |
Started | Jul 19 06:14:05 PM PDT 24 |
Finished | Jul 19 06:19:03 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-004c993e-f083-4a36-a672-7c0cd60521f9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931614368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.2931614368 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.65845477 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 135449039819 ps |
CPU time | 2284.51 seconds |
Started | Jul 19 06:13:50 PM PDT 24 |
Finished | Jul 19 06:51:55 PM PDT 24 |
Peak memory | 380812 kb |
Host | smart-8994de52-11f3-4f10-95ba-e973cf1ec447 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65845477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multipl e_keys.65845477 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.1790187005 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 610814024 ps |
CPU time | 15.33 seconds |
Started | Jul 19 06:13:57 PM PDT 24 |
Finished | Jul 19 06:14:13 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-b83ac597-3028-4605-b7fb-04896f81c229 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790187005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.1790187005 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3121636113 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 105896551511 ps |
CPU time | 272.96 seconds |
Started | Jul 19 06:13:56 PM PDT 24 |
Finished | Jul 19 06:18:30 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-7a78405b-ccbc-4eb6-8047-736d370a9f65 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121636113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.3121636113 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.131569769 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 709347220 ps |
CPU time | 3.21 seconds |
Started | Jul 19 06:14:04 PM PDT 24 |
Finished | Jul 19 06:14:08 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-1fe0b552-5a89-4327-b498-83167b47fce1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131569769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.131569769 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.191198056 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 6840525790 ps |
CPU time | 408.61 seconds |
Started | Jul 19 06:14:05 PM PDT 24 |
Finished | Jul 19 06:20:54 PM PDT 24 |
Peak memory | 374660 kb |
Host | smart-833b2037-7fc4-4d48-8cae-0e7c93379975 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191198056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.191198056 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.680195726 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 5510077690 ps |
CPU time | 15.42 seconds |
Started | Jul 19 06:13:48 PM PDT 24 |
Finished | Jul 19 06:14:04 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-7190a638-3534-4959-9743-2ebf67734835 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680195726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.680195726 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.525696214 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 40348448224 ps |
CPU time | 5109.15 seconds |
Started | Jul 19 06:14:04 PM PDT 24 |
Finished | Jul 19 07:39:14 PM PDT 24 |
Peak memory | 380832 kb |
Host | smart-1aa7be6d-3a04-441b-9286-a458a3507229 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525696214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_stress_all.525696214 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1335280991 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 679379024 ps |
CPU time | 9.76 seconds |
Started | Jul 19 06:14:04 PM PDT 24 |
Finished | Jul 19 06:14:14 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-d4725550-71ba-4297-b266-c7685b01adb9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1335280991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1335280991 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3851914167 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 36445351489 ps |
CPU time | 420.49 seconds |
Started | Jul 19 06:13:48 PM PDT 24 |
Finished | Jul 19 06:20:49 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-3675c6fb-0c7f-419c-997f-8dfdc6300ca8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851914167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.3851914167 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1522265165 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 13340721291 ps |
CPU time | 6.97 seconds |
Started | Jul 19 06:13:58 PM PDT 24 |
Finished | Jul 19 06:14:06 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-b32dbdcf-8c56-49ab-bd74-86c60eabe2ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522265165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1522265165 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3163017346 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 79068950370 ps |
CPU time | 852.04 seconds |
Started | Jul 19 06:14:12 PM PDT 24 |
Finished | Jul 19 06:28:25 PM PDT 24 |
Peak memory | 374652 kb |
Host | smart-0bf7c53a-84e9-4dcf-adaf-88058ae41916 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163017346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.3163017346 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.35705543 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 13929285 ps |
CPU time | 0.66 seconds |
Started | Jul 19 06:14:30 PM PDT 24 |
Finished | Jul 19 06:14:31 PM PDT 24 |
Peak memory | 202444 kb |
Host | smart-bf2ec86f-d3aa-46ef-89e5-e276f443b9c4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35705543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_alert_test.35705543 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.3700640671 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 141798611551 ps |
CPU time | 1747.69 seconds |
Started | Jul 19 06:14:11 PM PDT 24 |
Finished | Jul 19 06:43:20 PM PDT 24 |
Peak memory | 203668 kb |
Host | smart-ea2199fc-003b-439a-a3de-00d3c26b1fdc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700640671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .3700640671 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.2744277427 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 7201349861 ps |
CPU time | 233.02 seconds |
Started | Jul 19 06:14:12 PM PDT 24 |
Finished | Jul 19 06:18:06 PM PDT 24 |
Peak memory | 301092 kb |
Host | smart-cf37d2fe-a8b7-4533-8e31-2f7102056d63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744277427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2744277427 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.3954403985 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 14941652356 ps |
CPU time | 23.65 seconds |
Started | Jul 19 06:14:12 PM PDT 24 |
Finished | Jul 19 06:14:37 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-dfd3e225-6e2d-480c-96f3-57cb684da4c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954403985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.3954403985 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.1199201867 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 737515830 ps |
CPU time | 45.91 seconds |
Started | Jul 19 06:14:13 PM PDT 24 |
Finished | Jul 19 06:14:59 PM PDT 24 |
Peak memory | 300948 kb |
Host | smart-19c842ba-b0a6-4958-a84e-7a86a7544082 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199201867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.1199201867 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2208620247 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 1417581080 ps |
CPU time | 72.14 seconds |
Started | Jul 19 06:14:21 PM PDT 24 |
Finished | Jul 19 06:15:34 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-93aa90b1-0c0b-4b2d-a4ea-01dba9958729 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208620247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.2208620247 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.2586870809 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 15758131394 ps |
CPU time | 248.43 seconds |
Started | Jul 19 06:14:21 PM PDT 24 |
Finished | Jul 19 06:18:30 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-af8ce596-4415-422f-a077-8805590eace0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586870809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.2586870809 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.1602765477 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 26886514211 ps |
CPU time | 1445.95 seconds |
Started | Jul 19 06:14:13 PM PDT 24 |
Finished | Jul 19 06:38:20 PM PDT 24 |
Peak memory | 363444 kb |
Host | smart-e85f2e96-e763-4c7d-9e8a-a975c500f5b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602765477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.1602765477 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.2409233226 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 747970633 ps |
CPU time | 60.64 seconds |
Started | Jul 19 06:14:12 PM PDT 24 |
Finished | Jul 19 06:15:14 PM PDT 24 |
Peak memory | 303652 kb |
Host | smart-ae84131f-7293-4464-97e6-246ba5356b50 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409233226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.2409233226 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3639972972 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 23252153202 ps |
CPU time | 322.18 seconds |
Started | Jul 19 06:14:12 PM PDT 24 |
Finished | Jul 19 06:19:34 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-77c241d8-aaeb-4118-bf40-c638c8a8d187 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639972972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.3639972972 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.3375459538 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 1409282424 ps |
CPU time | 3.62 seconds |
Started | Jul 19 06:14:20 PM PDT 24 |
Finished | Jul 19 06:14:24 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-d7213d42-b959-4f15-a8b2-ffaa87115d69 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375459538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3375459538 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.708257278 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 3456161962 ps |
CPU time | 972.13 seconds |
Started | Jul 19 06:14:20 PM PDT 24 |
Finished | Jul 19 06:30:33 PM PDT 24 |
Peak memory | 379812 kb |
Host | smart-c6fdac76-6c39-4c70-89ce-6974f5b5d7b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708257278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.708257278 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.3149979948 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 808468279 ps |
CPU time | 142.47 seconds |
Started | Jul 19 06:14:13 PM PDT 24 |
Finished | Jul 19 06:16:36 PM PDT 24 |
Peak memory | 365288 kb |
Host | smart-bd63a4d1-bbbd-4a1c-b42f-475a452de476 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149979948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3149979948 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.3238007047 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 999189739370 ps |
CPU time | 6211.01 seconds |
Started | Jul 19 06:14:21 PM PDT 24 |
Finished | Jul 19 07:57:53 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-61aa47d4-e26f-4245-8cc6-f791ab5a481a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238007047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.3238007047 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3984030934 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 1695960821 ps |
CPU time | 44.1 seconds |
Started | Jul 19 06:14:22 PM PDT 24 |
Finished | Jul 19 06:15:06 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-31864784-e5ef-4530-b6e9-63ec6a96a6c0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3984030934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3984030934 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3385010592 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 3527192153 ps |
CPU time | 290.97 seconds |
Started | Jul 19 06:14:12 PM PDT 24 |
Finished | Jul 19 06:19:04 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-108514a4-2d7a-4681-8f90-9ad264eae7d6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385010592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.3385010592 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3973329652 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 820286092 ps |
CPU time | 146.54 seconds |
Started | Jul 19 06:14:12 PM PDT 24 |
Finished | Jul 19 06:16:39 PM PDT 24 |
Peak memory | 370552 kb |
Host | smart-fefb994d-f2f7-4b62-9d31-a6e72167cd39 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973329652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3973329652 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.96220687 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 140579381454 ps |
CPU time | 1022.01 seconds |
Started | Jul 19 06:14:28 PM PDT 24 |
Finished | Jul 19 06:31:31 PM PDT 24 |
Peak memory | 379808 kb |
Host | smart-c12873fa-771f-492b-8571-ef0464fcd822 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96220687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.sram_ctrl_access_during_key_req.96220687 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.1347480092 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 14320419 ps |
CPU time | 0.65 seconds |
Started | Jul 19 06:14:42 PM PDT 24 |
Finished | Jul 19 06:14:43 PM PDT 24 |
Peak memory | 202612 kb |
Host | smart-82d5f15a-47a0-419f-819b-e8df5cc00bbf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347480092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.1347480092 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.1617872162 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 488936767799 ps |
CPU time | 2259.05 seconds |
Started | Jul 19 06:14:28 PM PDT 24 |
Finished | Jul 19 06:52:08 PM PDT 24 |
Peak memory | 203480 kb |
Host | smart-6be095c5-f722-4c39-9107-c6744989275c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617872162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .1617872162 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.3525425132 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 100509646973 ps |
CPU time | 959.39 seconds |
Started | Jul 19 06:14:29 PM PDT 24 |
Finished | Jul 19 06:30:29 PM PDT 24 |
Peak memory | 378780 kb |
Host | smart-50679f5f-bfdc-4683-b999-0b5baaa5aa72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525425132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.3525425132 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.1698491050 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 44168334339 ps |
CPU time | 63.65 seconds |
Started | Jul 19 06:14:31 PM PDT 24 |
Finished | Jul 19 06:15:35 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-ac03929c-b6da-4817-a1bd-2286a279a6e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698491050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.1698491050 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.2532801583 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 2965648649 ps |
CPU time | 22.94 seconds |
Started | Jul 19 06:14:29 PM PDT 24 |
Finished | Jul 19 06:14:53 PM PDT 24 |
Peak memory | 279496 kb |
Host | smart-a91415c1-bffc-4110-bedc-a755c2fa7b7d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532801583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.2532801583 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2290273421 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 1448372928 ps |
CPU time | 65.8 seconds |
Started | Jul 19 06:14:35 PM PDT 24 |
Finished | Jul 19 06:15:42 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-e39e1a09-7e9e-44b5-94cb-38e4535c1b6f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290273421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.2290273421 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.964497430 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 74852024833 ps |
CPU time | 355.68 seconds |
Started | Jul 19 06:14:36 PM PDT 24 |
Finished | Jul 19 06:20:32 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-92b8ed92-811e-4340-992c-ae04d9adcb3f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964497430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl _mem_walk.964497430 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.3908287875 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 39357412671 ps |
CPU time | 1319.38 seconds |
Started | Jul 19 06:14:28 PM PDT 24 |
Finished | Jul 19 06:36:28 PM PDT 24 |
Peak memory | 377828 kb |
Host | smart-49b3722e-3da8-47e3-90be-8bca1a719861 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908287875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.3908287875 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.1460284349 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 2851508088 ps |
CPU time | 8.19 seconds |
Started | Jul 19 06:14:28 PM PDT 24 |
Finished | Jul 19 06:14:36 PM PDT 24 |
Peak memory | 208796 kb |
Host | smart-6a7c2d41-6b55-4925-844b-d352f58d1ab8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460284349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.1460284349 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2493582031 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 23881894827 ps |
CPU time | 270.39 seconds |
Started | Jul 19 06:14:32 PM PDT 24 |
Finished | Jul 19 06:19:02 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-28b2470a-5756-4e5f-a4c3-30eb14a90864 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493582031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.2493582031 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.1344916541 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 695182602 ps |
CPU time | 3.42 seconds |
Started | Jul 19 06:14:37 PM PDT 24 |
Finished | Jul 19 06:14:41 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-f83182a0-0651-4715-993c-2d811bcf4a2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344916541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1344916541 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.152554738 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 15139358398 ps |
CPU time | 1124.74 seconds |
Started | Jul 19 06:14:29 PM PDT 24 |
Finished | Jul 19 06:33:15 PM PDT 24 |
Peak memory | 380804 kb |
Host | smart-f6f56720-34be-4e97-b453-b8155520c9d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152554738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.152554738 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.244281260 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 980714415 ps |
CPU time | 6.81 seconds |
Started | Jul 19 06:14:29 PM PDT 24 |
Finished | Jul 19 06:14:36 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-cc39156e-68bb-4486-a39f-420992574b43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244281260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.244281260 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2418798490 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 487790920 ps |
CPU time | 19.39 seconds |
Started | Jul 19 06:14:35 PM PDT 24 |
Finished | Jul 19 06:14:55 PM PDT 24 |
Peak memory | 211192 kb |
Host | smart-c0ce85fb-8f72-4668-85e2-3fd5c6b656c8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2418798490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.2418798490 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3372065899 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 32823811562 ps |
CPU time | 274.02 seconds |
Started | Jul 19 06:14:29 PM PDT 24 |
Finished | Jul 19 06:19:04 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-525b2ed7-252f-40d0-828f-1788cd18f331 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372065899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.3372065899 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1006179525 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 1480311068 ps |
CPU time | 45.53 seconds |
Started | Jul 19 06:14:31 PM PDT 24 |
Finished | Jul 19 06:15:17 PM PDT 24 |
Peak memory | 292540 kb |
Host | smart-74f95d9f-7d79-47e4-81fe-57c21455cae1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006179525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1006179525 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.291480632 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 36197353750 ps |
CPU time | 1104.99 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:22:57 PM PDT 24 |
Peak memory | 374632 kb |
Host | smart-c4322f78-5dcf-49d2-8dc8-c094652fad2d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291480632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_access_during_key_req.291480632 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.2127370374 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 15919460 ps |
CPU time | 0.66 seconds |
Started | Jul 19 06:04:37 PM PDT 24 |
Finished | Jul 19 06:04:39 PM PDT 24 |
Peak memory | 202508 kb |
Host | smart-0cc250f7-12d0-4a68-ba53-813f6d1ef18f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127370374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2127370374 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.1288776147 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 522845570782 ps |
CPU time | 2942.69 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:53:35 PM PDT 24 |
Peak memory | 203464 kb |
Host | smart-32ca63ed-1222-4258-8367-eacd7daef17f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288776147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 1288776147 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.3876901790 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 16015174808 ps |
CPU time | 697.39 seconds |
Started | Jul 19 06:04:32 PM PDT 24 |
Finished | Jul 19 06:16:10 PM PDT 24 |
Peak memory | 351176 kb |
Host | smart-e876501b-6b35-42e8-abb8-dfce8e6469e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876901790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.3876901790 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.2276289139 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 19479376966 ps |
CPU time | 63.39 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:05:36 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-6186326a-41f4-469b-9cc0-ea6d337763ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276289139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.2276289139 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.465893008 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 849915177 ps |
CPU time | 151.2 seconds |
Started | Jul 19 06:04:29 PM PDT 24 |
Finished | Jul 19 06:07:01 PM PDT 24 |
Peak memory | 368448 kb |
Host | smart-39d0f1e5-b2ed-4c7a-a6f5-ac47c1fb09c0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465893008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.465893008 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.111996097 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 9701055409 ps |
CPU time | 149.66 seconds |
Started | Jul 19 06:04:36 PM PDT 24 |
Finished | Jul 19 06:07:07 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-6f3273de-2370-4486-b808-93afa736d381 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111996097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. sram_ctrl_mem_partial_access.111996097 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.2908676728 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 28766674155 ps |
CPU time | 340.51 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:10:13 PM PDT 24 |
Peak memory | 211748 kb |
Host | smart-f9f3c3d7-7ef3-4f2b-a8ae-015dfe52f4ee |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908676728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.2908676728 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.3461052490 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 6424610926 ps |
CPU time | 450.61 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:12:02 PM PDT 24 |
Peak memory | 359520 kb |
Host | smart-ae533eaa-4d03-4593-a073-f21f3a7c4d77 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461052490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.3461052490 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.2617168556 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 1680164420 ps |
CPU time | 22.37 seconds |
Started | Jul 19 06:04:32 PM PDT 24 |
Finished | Jul 19 06:04:55 PM PDT 24 |
Peak memory | 260588 kb |
Host | smart-dcc1eea1-e5d3-4b61-96fc-a30b9c80c091 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617168556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.2617168556 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2522519352 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 23090602518 ps |
CPU time | 321.19 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:09:53 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-f92040ae-0f08-4f7e-bd6e-fe0db6bb7933 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522519352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.2522519352 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.2981233544 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 365250627 ps |
CPU time | 3.32 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:04:35 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-c2d50525-0a2e-4da3-bd41-9a53d94f06a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981233544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2981233544 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.3297043458 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 3505796013 ps |
CPU time | 972.62 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:20:44 PM PDT 24 |
Peak memory | 368464 kb |
Host | smart-1cf60e41-4d62-487b-bed6-6c611d3eedb7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297043458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3297043458 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.3980151056 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 1524582001 ps |
CPU time | 160.5 seconds |
Started | Jul 19 06:04:23 PM PDT 24 |
Finished | Jul 19 06:07:04 PM PDT 24 |
Peak memory | 369448 kb |
Host | smart-00b9037e-5ce7-4434-968d-661e0bb90e30 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980151056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3980151056 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.15997969 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 823978559905 ps |
CPU time | 5320.32 seconds |
Started | Jul 19 06:04:36 PM PDT 24 |
Finished | Jul 19 07:33:18 PM PDT 24 |
Peak memory | 377784 kb |
Host | smart-bcb6456e-c0b2-4d9a-97d7-0c12a4015e55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15997969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.sram_ctrl_stress_all.15997969 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2877026236 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 8152881619 ps |
CPU time | 231.61 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:08:24 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-13ed997f-84e9-426d-bf64-192dc2bb97d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877026236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.2877026236 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1650765917 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 842952735 ps |
CPU time | 92.41 seconds |
Started | Jul 19 06:04:31 PM PDT 24 |
Finished | Jul 19 06:06:05 PM PDT 24 |
Peak memory | 370512 kb |
Host | smart-dc8b735f-6050-4b60-bb37-95b933fede13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650765917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.1650765917 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2291418874 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 14884535335 ps |
CPU time | 453.89 seconds |
Started | Jul 19 06:04:38 PM PDT 24 |
Finished | Jul 19 06:12:13 PM PDT 24 |
Peak memory | 370528 kb |
Host | smart-4abe4956-6463-4eca-a9fa-bc771f038871 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291418874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.2291418874 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.2743896736 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 40957869 ps |
CPU time | 0.67 seconds |
Started | Jul 19 06:04:45 PM PDT 24 |
Finished | Jul 19 06:04:47 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-16884810-dc9e-42a1-a9c2-6904a0472951 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743896736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.2743896736 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.2048581111 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 79241584197 ps |
CPU time | 1288.19 seconds |
Started | Jul 19 06:04:39 PM PDT 24 |
Finished | Jul 19 06:26:08 PM PDT 24 |
Peak memory | 203484 kb |
Host | smart-5a99a33e-740e-4953-8c4d-b722c3786b8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048581111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 2048581111 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.1114602406 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 3039124697 ps |
CPU time | 399.73 seconds |
Started | Jul 19 06:04:36 PM PDT 24 |
Finished | Jul 19 06:11:16 PM PDT 24 |
Peak memory | 367484 kb |
Host | smart-053c8ae7-e421-49b7-9efa-b90f64794a93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114602406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.1114602406 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.2846538512 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 107018044090 ps |
CPU time | 87.66 seconds |
Started | Jul 19 06:04:37 PM PDT 24 |
Finished | Jul 19 06:06:05 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-05031de6-4440-4439-8022-ce92afe2049d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846538512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.2846538512 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.2355048124 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 770770509 ps |
CPU time | 171.01 seconds |
Started | Jul 19 06:04:36 PM PDT 24 |
Finished | Jul 19 06:07:28 PM PDT 24 |
Peak memory | 370524 kb |
Host | smart-98712bb9-058f-44c4-8c88-53d793b90ef0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355048124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.2355048124 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.436237967 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 10020382984 ps |
CPU time | 168.98 seconds |
Started | Jul 19 06:04:46 PM PDT 24 |
Finished | Jul 19 06:07:36 PM PDT 24 |
Peak memory | 219264 kb |
Host | smart-2643787d-9932-4689-a092-5a8e498aeaab |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436237967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_mem_partial_access.436237967 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.2441134168 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 28863343484 ps |
CPU time | 168.38 seconds |
Started | Jul 19 06:04:54 PM PDT 24 |
Finished | Jul 19 06:07:44 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-01d32b46-2bc7-46cf-be19-59e592ca0a16 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441134168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.2441134168 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.2940378452 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 18143785705 ps |
CPU time | 306.44 seconds |
Started | Jul 19 06:04:40 PM PDT 24 |
Finished | Jul 19 06:09:47 PM PDT 24 |
Peak memory | 372592 kb |
Host | smart-fd0a4d11-8844-48d2-b441-172b942a6a38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940378452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.2940378452 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.2714983877 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 444535888 ps |
CPU time | 34.85 seconds |
Started | Jul 19 06:04:36 PM PDT 24 |
Finished | Jul 19 06:05:12 PM PDT 24 |
Peak memory | 275720 kb |
Host | smart-187cdb1d-d208-479b-aef2-83d2cc41b09b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714983877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.2714983877 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1353071224 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 6742708241 ps |
CPU time | 158.43 seconds |
Started | Jul 19 06:04:39 PM PDT 24 |
Finished | Jul 19 06:07:18 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-3563973e-ff08-4445-aae8-80d591b04670 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353071224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.1353071224 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.2055159855 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 370975440 ps |
CPU time | 2.99 seconds |
Started | Jul 19 06:04:38 PM PDT 24 |
Finished | Jul 19 06:04:42 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-81c60174-2dba-4261-8da1-1cb0aa418a7a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055159855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2055159855 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2712551449 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 13374306732 ps |
CPU time | 1068.45 seconds |
Started | Jul 19 06:04:37 PM PDT 24 |
Finished | Jul 19 06:22:27 PM PDT 24 |
Peak memory | 370620 kb |
Host | smart-40e51267-6474-4da9-a02e-d4591cf93128 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712551449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2712551449 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.763921935 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 3100674800 ps |
CPU time | 111.92 seconds |
Started | Jul 19 06:04:36 PM PDT 24 |
Finished | Jul 19 06:06:29 PM PDT 24 |
Peak memory | 368496 kb |
Host | smart-f391f6de-9e6b-466f-90c5-7e67e769d91a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763921935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.763921935 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.2707433223 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 142095534489 ps |
CPU time | 5884.03 seconds |
Started | Jul 19 06:04:43 PM PDT 24 |
Finished | Jul 19 07:42:50 PM PDT 24 |
Peak memory | 382868 kb |
Host | smart-cff10a25-6e0b-4da0-bdfe-167982a62303 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707433223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.2707433223 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.132442650 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 2700993666 ps |
CPU time | 9.26 seconds |
Started | Jul 19 06:04:46 PM PDT 24 |
Finished | Jul 19 06:04:57 PM PDT 24 |
Peak memory | 211232 kb |
Host | smart-da2f25b7-44de-4f6b-9efb-06cef69e5444 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=132442650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.132442650 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2943829646 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 21088650896 ps |
CPU time | 303.47 seconds |
Started | Jul 19 06:04:36 PM PDT 24 |
Finished | Jul 19 06:09:41 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-2eb707e2-dcc0-49dc-9ad9-abeb6b5ac2d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943829646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.2943829646 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3092952596 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 714988685 ps |
CPU time | 10.31 seconds |
Started | Jul 19 06:04:37 PM PDT 24 |
Finished | Jul 19 06:04:49 PM PDT 24 |
Peak memory | 235404 kb |
Host | smart-3e7d97ef-6291-442c-b0c2-8afb35c3100c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092952596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3092952596 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2209119475 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 25525980701 ps |
CPU time | 1096.24 seconds |
Started | Jul 19 06:04:44 PM PDT 24 |
Finished | Jul 19 06:23:02 PM PDT 24 |
Peak memory | 378968 kb |
Host | smart-39c61e9b-4635-497d-8315-5ece9899e0ae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209119475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.2209119475 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.3374455322 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 91121283 ps |
CPU time | 0.69 seconds |
Started | Jul 19 06:04:55 PM PDT 24 |
Finished | Jul 19 06:04:59 PM PDT 24 |
Peak memory | 202476 kb |
Host | smart-72590ef4-56ab-456c-90e4-937e063344a6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374455322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3374455322 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.743880152 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 323906418892 ps |
CPU time | 2780.68 seconds |
Started | Jul 19 06:04:47 PM PDT 24 |
Finished | Jul 19 06:51:10 PM PDT 24 |
Peak memory | 203564 kb |
Host | smart-14aeb388-67c2-401b-859a-3d594a5e95d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743880152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.743880152 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.1796316057 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 22521361145 ps |
CPU time | 909.82 seconds |
Started | Jul 19 06:04:54 PM PDT 24 |
Finished | Jul 19 06:20:05 PM PDT 24 |
Peak memory | 375656 kb |
Host | smart-705b4a3e-fce8-4c06-a1a7-17056aeba663 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796316057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.1796316057 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.1878901304 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 9842108523 ps |
CPU time | 57.75 seconds |
Started | Jul 19 06:04:54 PM PDT 24 |
Finished | Jul 19 06:05:53 PM PDT 24 |
Peak memory | 216212 kb |
Host | smart-b31b9d25-380c-4dcc-9b71-6da6e1a694b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878901304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.1878901304 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.984178004 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 778742171 ps |
CPU time | 96.22 seconds |
Started | Jul 19 06:04:46 PM PDT 24 |
Finished | Jul 19 06:06:24 PM PDT 24 |
Peak memory | 336980 kb |
Host | smart-dd6fda58-14bd-482a-abda-579e6d841648 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984178004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.sram_ctrl_max_throughput.984178004 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1280421606 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 5122621282 ps |
CPU time | 168.44 seconds |
Started | Jul 19 06:04:56 PM PDT 24 |
Finished | Jul 19 06:07:48 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-8b17496d-444e-45b2-9205-a83795d06a0f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280421606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.1280421606 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.3433870059 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 3377903341 ps |
CPU time | 160.94 seconds |
Started | Jul 19 06:04:53 PM PDT 24 |
Finished | Jul 19 06:07:36 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-e4438f93-2f69-4bdb-9dc7-02942361894e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433870059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.3433870059 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.3349450808 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 8952176880 ps |
CPU time | 850.44 seconds |
Started | Jul 19 06:04:44 PM PDT 24 |
Finished | Jul 19 06:18:56 PM PDT 24 |
Peak memory | 378472 kb |
Host | smart-efdc0501-3dc5-4c3e-883c-41c6a3f45479 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349450808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.3349450808 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.3769390869 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 7040248184 ps |
CPU time | 27.44 seconds |
Started | Jul 19 06:04:48 PM PDT 24 |
Finished | Jul 19 06:05:16 PM PDT 24 |
Peak memory | 277680 kb |
Host | smart-d4279648-ecd2-440d-9528-0114fe434672 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769390869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3769390869 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2995266027 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 3726931066 ps |
CPU time | 214.21 seconds |
Started | Jul 19 06:04:45 PM PDT 24 |
Finished | Jul 19 06:08:21 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-3aa735ca-2f37-4cd8-b410-c0fb1d3f32df |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995266027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.2995266027 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.4187721986 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 344555809 ps |
CPU time | 3.17 seconds |
Started | Jul 19 06:04:55 PM PDT 24 |
Finished | Jul 19 06:04:59 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-26d7166c-7578-4425-a2d7-c4e36ae973ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187721986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.4187721986 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.3555987238 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 26780202690 ps |
CPU time | 861.44 seconds |
Started | Jul 19 06:04:54 PM PDT 24 |
Finished | Jul 19 06:19:17 PM PDT 24 |
Peak memory | 381792 kb |
Host | smart-c6165b9f-6c82-4dcb-aa2e-fc73f4b0fffc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555987238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3555987238 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.723353110 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 827984427 ps |
CPU time | 49.11 seconds |
Started | Jul 19 06:04:45 PM PDT 24 |
Finished | Jul 19 06:05:36 PM PDT 24 |
Peak memory | 303512 kb |
Host | smart-d86fbc79-e2bb-4ebb-9003-c6bdbbc8447c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723353110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.723353110 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.1529295318 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 204040795632 ps |
CPU time | 9259.35 seconds |
Started | Jul 19 06:04:52 PM PDT 24 |
Finished | Jul 19 08:39:14 PM PDT 24 |
Peak memory | 383808 kb |
Host | smart-d00dc8cf-a12c-4fa4-9c7c-84a4633975dc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529295318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.1529295318 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2503346456 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 283622003 ps |
CPU time | 8.09 seconds |
Started | Jul 19 06:04:53 PM PDT 24 |
Finished | Jul 19 06:05:02 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-c715dff4-3d34-468c-8966-5e13ce7bc10b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2503346456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2503346456 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3466621562 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 5343099477 ps |
CPU time | 352.71 seconds |
Started | Jul 19 06:04:44 PM PDT 24 |
Finished | Jul 19 06:10:38 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-fa8d5b21-8c10-40c7-813b-880980868429 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466621562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.3466621562 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2927558343 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1539784347 ps |
CPU time | 83.64 seconds |
Started | Jul 19 06:04:54 PM PDT 24 |
Finished | Jul 19 06:06:19 PM PDT 24 |
Peak memory | 332652 kb |
Host | smart-5ca2ef49-42d9-4404-b89d-05a0e7b16d76 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927558343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2927558343 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1778584816 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 5162849731 ps |
CPU time | 108.57 seconds |
Started | Jul 19 06:05:07 PM PDT 24 |
Finished | Jul 19 06:06:57 PM PDT 24 |
Peak memory | 373652 kb |
Host | smart-a8906154-3739-4ece-9725-d3bc23da092b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778584816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.1778584816 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.926504714 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 23291498 ps |
CPU time | 0.65 seconds |
Started | Jul 19 06:05:07 PM PDT 24 |
Finished | Jul 19 06:05:11 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-8c52fd9b-723b-4f01-83a0-2e608b820d98 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926504714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.926504714 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.1140688196 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 55910399130 ps |
CPU time | 898.3 seconds |
Started | Jul 19 06:04:53 PM PDT 24 |
Finished | Jul 19 06:19:53 PM PDT 24 |
Peak memory | 203576 kb |
Host | smart-312a024f-df7e-474a-b48c-d1d59fdce340 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140688196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 1140688196 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.187072058 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 17798784578 ps |
CPU time | 762.52 seconds |
Started | Jul 19 06:05:06 PM PDT 24 |
Finished | Jul 19 06:17:51 PM PDT 24 |
Peak memory | 376692 kb |
Host | smart-7cf682ec-1721-4f8d-a5bd-a20f5b45c4a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187072058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable .187072058 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.1018303273 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 11102651924 ps |
CPU time | 62.82 seconds |
Started | Jul 19 06:05:09 PM PDT 24 |
Finished | Jul 19 06:06:16 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-4ca11f92-3cc9-4341-b879-28bda1a07a4c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018303273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.1018303273 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.3018168844 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 4442065313 ps |
CPU time | 36.82 seconds |
Started | Jul 19 06:05:07 PM PDT 24 |
Finished | Jul 19 06:05:46 PM PDT 24 |
Peak memory | 282056 kb |
Host | smart-52879d5c-2a78-4f41-9306-b96c1efa3948 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018168844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.3018168844 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1428896004 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 5086229509 ps |
CPU time | 161.64 seconds |
Started | Jul 19 06:05:06 PM PDT 24 |
Finished | Jul 19 06:07:50 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-b0414101-03b5-40ea-9e4e-1f1546a91e10 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428896004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1428896004 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.362401691 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 206659644053 ps |
CPU time | 254.86 seconds |
Started | Jul 19 06:05:09 PM PDT 24 |
Finished | Jul 19 06:09:29 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-39b7e30a-8aa0-437b-a531-92340ae0b475 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362401691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ mem_walk.362401691 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.1566149101 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 14220388029 ps |
CPU time | 1307.62 seconds |
Started | Jul 19 06:04:52 PM PDT 24 |
Finished | Jul 19 06:26:42 PM PDT 24 |
Peak memory | 378740 kb |
Host | smart-fe2fd571-43b6-4eb7-bbb3-ded5b5ff7760 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566149101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.1566149101 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.2259473630 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 778245054 ps |
CPU time | 13.1 seconds |
Started | Jul 19 06:05:06 PM PDT 24 |
Finished | Jul 19 06:05:22 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-dfc5a511-1cc9-4e59-86af-febc532546fd |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259473630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.2259473630 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2694713656 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 8126791082 ps |
CPU time | 499.99 seconds |
Started | Jul 19 06:05:05 PM PDT 24 |
Finished | Jul 19 06:13:28 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-96000807-9e9b-4c26-9995-d887565e5ecb |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694713656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.2694713656 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.1646642863 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 358057528 ps |
CPU time | 3.24 seconds |
Started | Jul 19 06:05:06 PM PDT 24 |
Finished | Jul 19 06:05:12 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-318facb0-519d-4fc8-adba-5f63c7c560c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646642863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1646642863 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.3081089624 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 9684020311 ps |
CPU time | 384.73 seconds |
Started | Jul 19 06:05:09 PM PDT 24 |
Finished | Jul 19 06:11:38 PM PDT 24 |
Peak memory | 374600 kb |
Host | smart-2da1534a-8b14-4927-b156-4728afb8ca90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081089624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3081089624 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.2529167695 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 1448531307 ps |
CPU time | 26.33 seconds |
Started | Jul 19 06:04:54 PM PDT 24 |
Finished | Jul 19 06:05:21 PM PDT 24 |
Peak memory | 274040 kb |
Host | smart-c26b2189-7a3b-4f93-948b-4cac4161cb33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529167695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2529167695 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.1002235727 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 22804545604 ps |
CPU time | 3743.12 seconds |
Started | Jul 19 06:05:08 PM PDT 24 |
Finished | Jul 19 07:07:36 PM PDT 24 |
Peak memory | 380856 kb |
Host | smart-032eb0e7-92c7-42f7-b2c6-3f5f05f02514 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002235727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.1002235727 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1296862434 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 772661819 ps |
CPU time | 8.6 seconds |
Started | Jul 19 06:05:05 PM PDT 24 |
Finished | Jul 19 06:05:15 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-282dea54-b0b5-44d2-be65-de12333b8a70 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1296862434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1296862434 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1174047721 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 8427572764 ps |
CPU time | 116.04 seconds |
Started | Jul 19 06:04:54 PM PDT 24 |
Finished | Jul 19 06:06:51 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-d17b9f62-a08f-4cf3-94f8-5a28c9159c61 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174047721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.1174047721 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4157142595 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 714003911 ps |
CPU time | 20.6 seconds |
Started | Jul 19 06:05:14 PM PDT 24 |
Finished | Jul 19 06:05:39 PM PDT 24 |
Peak memory | 258212 kb |
Host | smart-5842eaad-1052-47b6-a6bc-b6e123d82814 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157142595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.4157142595 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3503120669 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 110006488113 ps |
CPU time | 1087.08 seconds |
Started | Jul 19 06:05:08 PM PDT 24 |
Finished | Jul 19 06:23:18 PM PDT 24 |
Peak memory | 378800 kb |
Host | smart-92077898-60c2-4a83-9d51-2e04373558d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503120669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.3503120669 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.875330219 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 27146171 ps |
CPU time | 0.68 seconds |
Started | Jul 19 06:05:14 PM PDT 24 |
Finished | Jul 19 06:05:19 PM PDT 24 |
Peak memory | 202492 kb |
Host | smart-5ee7969f-a1aa-4be9-ba51-1dbce9092e5f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875330219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.875330219 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.2005390298 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 179644513097 ps |
CPU time | 1651.45 seconds |
Started | Jul 19 06:05:07 PM PDT 24 |
Finished | Jul 19 06:32:41 PM PDT 24 |
Peak memory | 203388 kb |
Host | smart-a5ac4e42-db6b-4652-baed-9aa6f4f9e0a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005390298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 2005390298 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.2345378635 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 7385074399 ps |
CPU time | 166.51 seconds |
Started | Jul 19 06:05:13 PM PDT 24 |
Finished | Jul 19 06:08:05 PM PDT 24 |
Peak memory | 316388 kb |
Host | smart-c53b1de1-9487-4297-92dc-ae7caaaf128e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345378635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.2345378635 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.1633711853 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 13529927865 ps |
CPU time | 78.44 seconds |
Started | Jul 19 06:05:08 PM PDT 24 |
Finished | Jul 19 06:06:31 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-c6b8b6ab-6278-4132-902b-4afb6c023ea9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633711853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.1633711853 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.570451561 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 1364244346 ps |
CPU time | 5.73 seconds |
Started | Jul 19 06:05:14 PM PDT 24 |
Finished | Jul 19 06:05:24 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-27917bb8-f332-4866-a9b7-baa6bae9aaaf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570451561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.sram_ctrl_max_throughput.570451561 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1782316595 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 2445929060 ps |
CPU time | 142.31 seconds |
Started | Jul 19 06:05:07 PM PDT 24 |
Finished | Jul 19 06:07:31 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-149e71b8-7761-44fe-aa73-77be620e9941 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782316595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.1782316595 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.1860250098 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 43089712323 ps |
CPU time | 184.21 seconds |
Started | Jul 19 06:05:09 PM PDT 24 |
Finished | Jul 19 06:08:18 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-3cecdca5-6b3a-4f08-904e-e9ee2f2e2ffd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860250098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl _mem_walk.1860250098 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.1515968128 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 26589055466 ps |
CPU time | 710.94 seconds |
Started | Jul 19 06:05:07 PM PDT 24 |
Finished | Jul 19 06:17:00 PM PDT 24 |
Peak memory | 375676 kb |
Host | smart-4e5289a8-d1d5-4f4b-afcf-b9ce2c593de6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515968128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.1515968128 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.913665673 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 1368060000 ps |
CPU time | 4.08 seconds |
Started | Jul 19 06:05:05 PM PDT 24 |
Finished | Jul 19 06:05:11 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-834895fd-08de-4331-b6cf-193e303bc948 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913665673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr am_ctrl_partial_access.913665673 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3327921690 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 53342164074 ps |
CPU time | 439.56 seconds |
Started | Jul 19 06:05:14 PM PDT 24 |
Finished | Jul 19 06:12:38 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-36edf590-32b5-44c0-aa71-856f12403792 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327921690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.3327921690 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.2236878332 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 2239655871 ps |
CPU time | 3.38 seconds |
Started | Jul 19 06:05:09 PM PDT 24 |
Finished | Jul 19 06:05:17 PM PDT 24 |
Peak memory | 202968 kb |
Host | smart-0bc59c47-6162-4509-9250-7f02e409f5f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236878332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2236878332 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.1478338946 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 49673727417 ps |
CPU time | 884.41 seconds |
Started | Jul 19 06:05:09 PM PDT 24 |
Finished | Jul 19 06:19:58 PM PDT 24 |
Peak memory | 380760 kb |
Host | smart-9b84713e-5359-40be-8154-b15ab3eb9ece |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478338946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1478338946 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.3142969936 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 855628562 ps |
CPU time | 13.44 seconds |
Started | Jul 19 06:05:06 PM PDT 24 |
Finished | Jul 19 06:05:22 PM PDT 24 |
Peak memory | 231632 kb |
Host | smart-1f52c0f3-b2ea-4427-a1e0-e1ffb2a9ab97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142969936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3142969936 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.2583051900 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 56060129297 ps |
CPU time | 5103.08 seconds |
Started | Jul 19 06:05:09 PM PDT 24 |
Finished | Jul 19 07:30:17 PM PDT 24 |
Peak memory | 382924 kb |
Host | smart-2b65f2e0-89f8-4b56-963c-0dc8e18a1834 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583051900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.2583051900 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.827547859 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 1286565959 ps |
CPU time | 355.6 seconds |
Started | Jul 19 06:05:13 PM PDT 24 |
Finished | Jul 19 06:11:14 PM PDT 24 |
Peak memory | 376444 kb |
Host | smart-8108feaf-caea-4cee-ad31-7902c633da5a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=827547859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.827547859 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3945093651 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 3648533361 ps |
CPU time | 273.48 seconds |
Started | Jul 19 06:05:09 PM PDT 24 |
Finished | Jul 19 06:09:46 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-7a3c8ecf-3669-4330-80a4-f568785b59b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945093651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3945093651 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.38005359 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 798641041 ps |
CPU time | 133.83 seconds |
Started | Jul 19 06:05:07 PM PDT 24 |
Finished | Jul 19 06:07:24 PM PDT 24 |
Peak memory | 370564 kb |
Host | smart-20a5d049-b1b3-4544-aebd-d95495133678 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38005359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.sram_ctrl_throughput_w_partial_write.38005359 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |