Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 16 0 16 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_exec_cp 3 0 3 100.00 100 1 1 0
en_sram_ifetch_cp 3 0 3 100.00 100 1 1 0
lc_hw_debug_en_cp 3 0 3 100.00 100 1 1 0


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
executable_cross 16 0 16 100.00 100 1 1 0


Summary for Variable csr_exec_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csr_exec_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
instr_invalid_dis 368756502 1 T2 285348 T3 275428 T4 75718
instr_valid_dis 324889783 1 T3 275428 T4 75718 T5 241636
instr_en 32622113 1 T2 285348 T11 45538 T29 129202



Summary for Variable en_sram_ifetch_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for en_sram_ifetch_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_ifetch_invalid_disable 15340484 1 T2 29014 T11 106488 T29 155568
sram_ifetch_valid_disable 323838664 1 T2 138512 T3 275428 T4 75718
sram_ifetch_enable 29577354 1 T2 117822 T11 66868 T29 123784



Summary for Variable lc_hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for lc_hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off 368756502 1 T2 285348 T3 275428 T4 75718
hw_debug_en_valid_off 324833813 1 T2 70156 T3 275428 T4 75718
hw_debug_en_on 29721616 1 T2 120338 T11 189948 T29 69200



Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 16 0 16 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for executable_cross

Bins
lc_hw_debug_en_cpen_sram_ifetch_cpcsr_exec_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_invalid_dis 323838664 1 T2 138512 T3 275428 T4 75718
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_valid_dis 309731947 1 T3 275428 T4 75718 T5 241636
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_en 9302685 1 T2 138512 T59 17224 T68 29408
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_invalid_dis 5498044 1 T29 19276 T59 530 T68 17112
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_valid_dis 2872532 1 T29 19276 T59 530 T139 1710
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_en 1915746 1 T68 17112 T70 31008 T143 14170
hw_debug_en_on sram_ifetch_invalid_disable instr_invalid_dis 7420810 1 T2 19310 T11 106488 T29 13508
hw_debug_en_on sram_ifetch_invalid_disable instr_valid_dis 1400582 1 T11 60950 T29 13508 T68 43020
hw_debug_en_on sram_ifetch_invalid_disable instr_en 5334604 1 T2 19310 T11 45538 T59 27962
hw_debug_en_on sram_ifetch_valid_disable instr_invalid_dis 8543474 1 T2 58268 T11 68118 T29 13378
hw_debug_en_on sram_ifetch_valid_disable instr_valid_dis 2962390 1 T11 68118 T68 51244 T143 38022
hw_debug_en_on sram_ifetch_valid_disable instr_en 3919368 1 T2 58268 T59 17224 T70 160040


User Defined Cross Bins for executable_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
csr_exec_en 15102242 1 T2 117822 T29 53548 T59 32548
lc_exec_en 13757332 1 T2 42760 T11 15342 T29 42314
valid_exec_dis 320601077 1 T2 28290 T3 275428 T4 75718
invalid_exec_dis 44917838 1 T2 146836 T11 173356 T29 279352

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