Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	154835301	1			T2	69495		T3	125312		T4	34434
triple_byte_access	2805192	1			T2	1416		T3	2449		T4	668
halfword_access	4304092	1			T2	2080		T3	3693		T4	1003
byte_access	6010935	1			T2	2781		T3	5006		T4	1410
zero_access	1811397	1			T2	703		T3	1254		T4	344

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84676867

1

T2

48018

T3

68894

T4

18921

auto[1]

85090050

1

T2

28457

T3

68820

T4

18938

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	77069167	1			T2	43634		T3	62640		T4	17244
auto[0]	triple_byte_access	1342208	1			T2	888		T3	1253		T4	335
auto[0]	halfword_access	2106300	1			T2	1302		T3	1862		T4	473
auto[0]	byte_access	3081368	1			T2	1761		T3	2492		T4	698
auto[0]	zero_access	1077824	1			T2	433		T3	647		T4	171
auto[1]	word_access	77766134	1			T2	25861		T3	62672		T4	17190
auto[1]	triple_byte_access	1462984	1			T2	528		T3	1196		T4	333
auto[1]	halfword_access	2197792	1			T2	778		T3	1831		T4	530
auto[1]	byte_access	2929567	1			T2	1020		T3	2514		T4	712
auto[1]	zero_access	733573	1			T2	270		T3	607		T4	173