Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16432873	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

158867030

1

T1

249387

T3

196606

T4

3399

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86302878	1			T1	136782		T3	65536		T4	2109
values[0x0]	42873218	1			T1	65853		T3	65417		T4	888
values[0x1]	46123807	1			T1	71579		T3	65653		T4	1096

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8353288	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166946615

1

T1

261798

T3

196606

T4

3752

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	637155	1			T1	1021		T4	18		T11	15
valid_sources[0x01]	590428	1			T1	1106		T4	14		T11	12
valid_sources[0x02]	599438	1			T1	1056		T4	14		T11	13
valid_sources[0x03]	2028762	1			T1	1022		T4	14		T11	13
valid_sources[0x04]	592317	1			T1	1080		T4	11		T11	12
valid_sources[0x05]	624693	1			T1	1039		T4	13		T11	13
valid_sources[0x06]	586460	1			T1	1073		T4	13		T11	19
valid_sources[0x07]	618602	1			T1	1087		T4	12		T11	30
valid_sources[0x08]	582089	1			T1	1035		T4	18		T11	19
valid_sources[0x09]	646341	1			T1	1140		T4	19		T11	10
valid_sources[0x0a]	593126	1			T1	1063		T4	13		T11	12
valid_sources[0x0b]	604491	1			T1	1057		T4	31		T11	11
valid_sources[0x0c]	601760	1			T1	1100		T4	17		T11	18
valid_sources[0x0d]	607248	1			T1	1021		T4	17		T11	13
valid_sources[0x0e]	647050	1			T1	1089		T4	7		T11	17
valid_sources[0x0f]	633285	1			T1	999		T4	28		T11	11
valid_sources[0x10]	597662	1			T1	1030		T4	16		T11	13
valid_sources[0x11]	641722	1			T1	1090		T4	19		T11	20
valid_sources[0x12]	659173	1			T1	1059		T4	24		T11	10
valid_sources[0x13]	601029	1			T1	1091		T4	20		T11	14
valid_sources[0x14]	609408	1			T1	1109		T4	17		T11	11
valid_sources[0x15]	586875	1			T1	1119		T4	22		T11	13
valid_sources[0x16]	673279	1			T1	1068		T4	14		T11	20
valid_sources[0x17]	592689	1			T1	1095		T4	9		T11	9
valid_sources[0x18]	637255	1			T1	1141		T4	23		T11	15
valid_sources[0x19]	600102	1			T1	1080		T4	13		T11	17
valid_sources[0x1a]	589360	1			T1	1114		T4	20		T11	12
valid_sources[0x1b]	622854	1			T1	1011		T4	6		T11	15
valid_sources[0x1c]	1383328	1			T1	1078		T4	8		T11	14
valid_sources[0x1d]	666661	1			T1	1144		T4	16		T11	14
valid_sources[0x1e]	623005	1			T1	1102		T4	23		T11	18
valid_sources[0x1f]	623466	1			T1	1075		T4	12		T11	19
valid_sources[0x20]	648111	1			T1	1104		T4	6		T11	14
valid_sources[0x21]	604239	1			T1	1015		T4	15		T11	18
valid_sources[0x22]	627508	1			T1	1061		T4	20		T11	16
valid_sources[0x23]	647173	1			T1	1089		T4	16		T11	15
valid_sources[0x24]	596272	1			T1	1067		T4	20		T11	14
valid_sources[0x25]	618002	1			T1	1146		T4	11		T11	18
valid_sources[0x26]	677494	1			T1	1056		T4	8		T11	17
valid_sources[0x27]	791205	1			T1	1055		T4	9		T11	14
valid_sources[0x28]	613411	1			T1	1103		T4	11		T11	13
valid_sources[0x29]	618890	1			T1	1086		T4	8		T11	17
valid_sources[0x2a]	612797	1			T1	1075		T4	18		T11	14
valid_sources[0x2b]	668118	1			T1	1098		T4	22		T11	10
valid_sources[0x2c]	618899	1			T1	1076		T4	13		T11	15
valid_sources[0x2d]	617292	1			T1	1028		T4	14		T5	2729
valid_sources[0x2e]	714187	1			T1	1044		T4	16		T11	10
valid_sources[0x2f]	608735	1			T1	1109		T4	12		T11	16
valid_sources[0x30]	622720	1			T1	1063		T4	10		T11	17
valid_sources[0x31]	606522	1			T1	1103		T4	22		T11	15
valid_sources[0x32]	1390627	1			T1	1062		T4	24		T11	15
valid_sources[0x33]	590745	1			T1	1049		T4	15		T11	22
valid_sources[0x34]	608919	1			T1	1054		T4	30		T11	21
valid_sources[0x35]	724791	1			T1	1095		T4	13		T11	22
valid_sources[0x36]	643418	1			T1	1038		T4	17		T11	26
valid_sources[0x37]	978947	1			T1	1071		T4	15		T11	26
valid_sources[0x38]	651801	1			T1	1066		T4	20		T5	14988
valid_sources[0x39]	634123	1			T1	1038		T4	32		T11	14
valid_sources[0x3a]	610407	1			T1	1028		T4	20		T11	13
valid_sources[0x3b]	586728	1			T1	1073		T4	21		T11	15
valid_sources[0x3c]	605058	1			T1	1159		T4	19		T11	13
valid_sources[0x3d]	663196	1			T1	1086		T4	20		T11	17
valid_sources[0x3e]	604307	1			T1	1078		T4	15		T11	12
valid_sources[0x3f]	583934	1			T1	1031		T4	21		T11	17
valid_sources[0x40]	809503	1			T1	1079		T4	16		T11	18
valid_sources[0x41]	590559	1			T1	1054		T4	18		T11	25
valid_sources[0x42]	660366	1			T1	1056		T4	22		T11	17
valid_sources[0x43]	592929	1			T1	1027		T4	26		T11	15
valid_sources[0x44]	652680	1			T1	1044		T4	26		T11	6
valid_sources[0x45]	1761584	1			T1	1111		T4	22		T11	15
valid_sources[0x46]	596936	1			T1	1052		T4	6		T11	22
valid_sources[0x47]	608225	1			T1	1110		T4	21		T11	13
valid_sources[0x48]	597340	1			T1	1027		T4	14		T11	23
valid_sources[0x49]	1193187	1			T1	1093		T4	10		T11	14
valid_sources[0x4a]	616945	1			T1	1094		T4	17		T11	13
valid_sources[0x4b]	594241	1			T1	1036		T4	15		T11	10
valid_sources[0x4c]	617609	1			T1	1111		T4	7		T11	15
valid_sources[0x4d]	592948	1			T1	1070		T4	23		T11	13
valid_sources[0x4e]	662525	1			T1	1102		T4	20		T11	10
valid_sources[0x4f]	587415	1			T1	1099		T4	19		T11	16
valid_sources[0x50]	602641	1			T1	1145		T4	14		T11	14
valid_sources[0x51]	590305	1			T1	1058		T4	12		T11	17
valid_sources[0x52]	617639	1			T1	1058		T4	11		T11	13
valid_sources[0x53]	604431	1			T1	1048		T4	8		T11	6
valid_sources[0x54]	643290	1			T1	1032		T4	20		T11	17
valid_sources[0x55]	611832	1			T1	1072		T4	11		T11	19
valid_sources[0x56]	585430	1			T1	1068		T4	13		T11	12
valid_sources[0x57]	637548	1			T1	1033		T4	19		T11	18
valid_sources[0x58]	616050	1			T1	1105		T4	11		T11	16
valid_sources[0x59]	589048	1			T1	1116		T4	11		T11	12
valid_sources[0x5a]	617192	1			T1	1073		T4	6		T11	13
valid_sources[0x5b]	595320	1			T1	1111		T4	9		T11	18
valid_sources[0x5c]	611850	1			T1	1053		T4	22		T11	27
valid_sources[0x5d]	812549	1			T1	1045		T4	20		T11	17
valid_sources[0x5e]	592052	1			T1	1105		T4	24		T11	13
valid_sources[0x5f]	636418	1			T1	1072		T4	19		T11	16
valid_sources[0x60]	587500	1			T1	1035		T4	23		T11	15
valid_sources[0x61]	592793	1			T1	1063		T4	16		T11	17
valid_sources[0x62]	597320	1			T1	1095		T4	19		T11	16
valid_sources[0x63]	615586	1			T1	1083		T4	6		T11	17
valid_sources[0x64]	601981	1			T1	1114		T4	15		T11	17
valid_sources[0x65]	708138	1			T1	1036		T4	20		T11	8
valid_sources[0x66]	633988	1			T1	1069		T4	23		T11	21
valid_sources[0x67]	592280	1			T1	1062		T4	19		T11	17
valid_sources[0x68]	595926	1			T1	1108		T4	17		T11	24
valid_sources[0x69]	609946	1			T1	1083		T4	16		T11	15
valid_sources[0x6a]	615552	1			T1	1117		T4	23		T11	18
valid_sources[0x6b]	603804	1			T1	1039		T4	16		T11	11
valid_sources[0x6c]	590279	1			T1	1036		T4	25		T11	13
valid_sources[0x6d]	600554	1			T1	1081		T4	13		T11	13
valid_sources[0x6e]	1202538	1			T1	1053		T4	8		T11	18
valid_sources[0x6f]	615845	1			T1	993		T4	18		T11	24
valid_sources[0x70]	687680	1			T1	1052		T4	14		T11	8
valid_sources[0x71]	674296	1			T1	958		T4	27		T11	15
valid_sources[0x72]	631056	1			T1	1119		T4	8		T11	11
valid_sources[0x73]	584651	1			T1	1088		T4	21		T11	16
valid_sources[0x74]	613553	1			T1	1005		T4	16		T11	16
valid_sources[0x75]	888266	1			T1	1108		T4	19		T11	15
valid_sources[0x76]	585779	1			T1	1100		T4	13		T11	17
valid_sources[0x77]	659380	1			T1	1112		T4	13		T11	11
valid_sources[0x78]	791205	1			T1	1094		T4	5		T11	19
valid_sources[0x79]	624867	1			T1	1075		T4	19		T11	14
valid_sources[0x7a]	662736	1			T1	1101		T4	17		T11	9
valid_sources[0x7b]	1309592	1			T1	1069		T4	9		T11	17
valid_sources[0x7c]	1884874	1			T1	1024		T4	15		T11	14
valid_sources[0x7d]	623363	1			T1	1004		T4	13		T11	21
valid_sources[0x7e]	610292	1			T1	1111		T4	18		T11	15
valid_sources[0x7f]	602752	1			T1	1066		T4	15		T11	21
valid_sources[0x80]	631677	1			T1	1033		T4	15		T11	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78044374

1

T1

124307

T3

65536

T4

1743

values[0x0]

all_enables

biggest_size

40421720

1

T1

62149

T3

65417

T4

798

values[0x1]

all_enables

biggest_size

40400936

1

T1

62931

T3

65653

T4

858

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46414	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

158056

1

T1

5

T3

73

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54942	1			T11	856		T15	15		T23	306
values[0x0]	72422	1			T1	14		T2	1		T3	137
values[0x1]	77106	1			T1	6		T3	136		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

168330

1

T1

5

T3

100

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	770	1			T11	9		T23	10		T16	1
valid_sources[0x01]	766	1			T11	13		T23	1		T24	6
valid_sources[0x02]	749	1			T11	12		T23	10		T24	10
valid_sources[0x03]	607	1			T11	14		T24	8		T10	1
valid_sources[0x04]	610	1			T11	13		T14	2		T23	4
valid_sources[0x05]	616	1			T11	10		T23	6		T24	9
valid_sources[0x06]	866	1			T11	9		T24	7		T50	1
valid_sources[0x07]	761	1			T11	8		T23	5		T24	8
valid_sources[0x08]	1442	1			T11	10		T23	11		T24	5
valid_sources[0x09]	724	1			T11	18		T23	1		T24	6
valid_sources[0x0a]	659	1			T11	11		T23	6		T24	8
valid_sources[0x0b]	791	1			T11	12		T14	1		T23	2
valid_sources[0x0c]	637	1			T11	13		T23	10		T24	4
valid_sources[0x0d]	664	1			T11	14		T23	1		T24	9
valid_sources[0x0e]	711	1			T11	8		T14	1		T23	3
valid_sources[0x0f]	1061	1			T11	12		T23	6		T24	8
valid_sources[0x10]	659	1			T11	9		T23	19		T24	5
valid_sources[0x11]	547	1			T11	16		T24	14		T7	2
valid_sources[0x12]	645	1			T11	12		T23	3		T24	15
valid_sources[0x13]	746	1			T11	14		T23	4		T24	5
valid_sources[0x14]	589	1			T11	7		T23	8		T24	1
valid_sources[0x15]	913	1			T11	4		T23	12		T24	10
valid_sources[0x16]	1035	1			T11	12		T23	4		T43	23
valid_sources[0x17]	758	1			T11	6		T23	2		T24	7
valid_sources[0x18]	544	1			T11	9		T23	1		T24	7
valid_sources[0x19]	741	1			T11	16		T23	4		T26	2
valid_sources[0x1a]	813	1			T11	13		T23	2		T26	1
valid_sources[0x1b]	730	1			T11	14		T24	5		T10	3
valid_sources[0x1c]	898	1			T11	12		T36	1		T23	10
valid_sources[0x1d]	669	1			T11	9		T23	3		T24	8
valid_sources[0x1e]	788	1			T11	8		T23	6		T24	10
valid_sources[0x1f]	580	1			T11	6		T23	1		T24	7
valid_sources[0x20]	699	1			T11	11		T39	2		T24	5
valid_sources[0x21]	973	1			T11	20		T24	9		T7	1
valid_sources[0x22]	948	1			T11	16		T23	2		T24	8
valid_sources[0x23]	878	1			T1	4		T11	13		T23	9
valid_sources[0x24]	1078	1			T11	11		T14	2		T23	6
valid_sources[0x25]	907	1			T11	11		T24	8		T46	5
valid_sources[0x26]	597	1			T11	4		T23	13		T24	7
valid_sources[0x27]	752	1			T11	20		T23	6		T25	2
valid_sources[0x28]	756	1			T11	16		T24	8		T10	2
valid_sources[0x29]	906	1			T11	13		T23	18		T24	10
valid_sources[0x2a]	623	1			T11	16		T14	1		T24	8
valid_sources[0x2b]	841	1			T11	11		T23	1		T9	1
valid_sources[0x2c]	762	1			T11	18		T23	16		T37	1
valid_sources[0x2d]	982	1			T11	11		T23	7		T24	6
valid_sources[0x2e]	716	1			T11	17		T23	4		T24	12
valid_sources[0x2f]	860	1			T11	12		T23	3		T24	8
valid_sources[0x30]	798	1			T11	9		T23	2		T24	5
valid_sources[0x31]	1418	1			T4	2		T11	13		T14	3
valid_sources[0x32]	646	1			T1	2		T11	22		T23	3
valid_sources[0x33]	680	1			T11	17		T23	7		T32	1
valid_sources[0x34]	579	1			T11	15		T23	3		T24	6
valid_sources[0x35]	910	1			T11	14		T14	2		T23	7
valid_sources[0x36]	1056	1			T11	15		T23	1		T24	10
valid_sources[0x37]	876	1			T11	13		T23	2		T24	17
valid_sources[0x38]	895	1			T11	8		T23	13		T24	9
valid_sources[0x39]	711	1			T11	14		T23	1		T24	9
valid_sources[0x3a]	1079	1			T11	13		T24	5		T51	1
valid_sources[0x3b]	1034	1			T11	14		T32	2		T24	8
valid_sources[0x3c]	607	1			T11	9		T23	3		T24	6
valid_sources[0x3d]	717	1			T11	9		T14	1		T23	3
valid_sources[0x3e]	614	1			T11	10		T23	14		T24	9
valid_sources[0x3f]	638	1			T11	10		T23	23		T24	5
valid_sources[0x40]	787	1			T11	6		T23	1		T24	7
valid_sources[0x41]	714	1			T11	9		T24	7		T50	7
valid_sources[0x42]	1018	1			T11	17		T24	10		T7	1
valid_sources[0x43]	700	1			T11	12		T15	26		T23	1
valid_sources[0x44]	644	1			T11	5		T23	1		T25	1
valid_sources[0x45]	981	1			T11	8		T23	4		T16	1
valid_sources[0x46]	779	1			T11	13		T25	3		T24	8
valid_sources[0x47]	516	1			T11	13		T24	8		T46	8
valid_sources[0x48]	544	1			T11	15		T23	5		T24	5
valid_sources[0x49]	621	1			T11	18		T23	3		T61	3
valid_sources[0x4a]	868	1			T11	17		T24	10		T51	1
valid_sources[0x4b]	623	1			T11	7		T23	3		T24	2
valid_sources[0x4c]	835	1			T11	16		T23	17		T24	5
valid_sources[0x4d]	1068	1			T11	7		T24	7		T7	2
valid_sources[0x4e]	722	1			T11	11		T14	4		T23	3
valid_sources[0x4f]	802	1			T11	10		T23	5		T24	5
valid_sources[0x50]	940	1			T11	17		T30	1		T24	10
valid_sources[0x51]	1010	1			T11	6		T23	5		T24	5
valid_sources[0x52]	672	1			T11	11		T24	7		T50	5
valid_sources[0x53]	560	1			T11	13		T24	6		T46	7
valid_sources[0x54]	812	1			T11	10		T23	15		T24	4
valid_sources[0x55]	632	1			T11	9		T23	5		T16	1
valid_sources[0x56]	1236	1			T11	20		T14	1		T23	2
valid_sources[0x57]	1180	1			T11	12		T24	5		T50	1
valid_sources[0x58]	831	1			T11	12		T14	4		T23	1
valid_sources[0x59]	1006	1			T11	10		T23	1		T24	4
valid_sources[0x5a]	947	1			T11	14		T23	6		T24	9
valid_sources[0x5b]	825	1			T11	18		T24	6		T51	1
valid_sources[0x5c]	810	1			T11	16		T23	15		T25	2
valid_sources[0x5d]	1412	1			T11	5		T23	9		T24	8
valid_sources[0x5e]	552	1			T11	14		T23	1		T24	9
valid_sources[0x5f]	946	1			T11	15		T23	2		T24	5
valid_sources[0x60]	622	1			T11	15		T23	10		T26	2
valid_sources[0x61]	714	1			T11	20		T23	1		T24	9
valid_sources[0x62]	762	1			T11	15		T14	1		T23	1
valid_sources[0x63]	585	1			T11	10		T24	5		T18	13
valid_sources[0x64]	825	1			T11	11		T23	15		T24	8
valid_sources[0x65]	830	1			T11	11		T23	10		T16	2
valid_sources[0x66]	856	1			T11	12		T23	11		T24	5
valid_sources[0x67]	787	1			T5	3		T11	17		T23	2
valid_sources[0x68]	687	1			T11	18		T23	1		T24	8
valid_sources[0x69]	696	1			T11	6		T14	8		T23	23
valid_sources[0x6a]	652	1			T11	14		T23	3		T24	6
valid_sources[0x6b]	797	1			T11	8		T23	1		T24	6
valid_sources[0x6c]	763	1			T11	15		T23	2		T24	7
valid_sources[0x6d]	1119	1			T11	14		T23	5		T24	3
valid_sources[0x6e]	1051	1			T11	14		T23	2		T24	7
valid_sources[0x6f]	619	1			T11	17		T24	7		T7	1
valid_sources[0x70]	975	1			T11	12		T23	2		T24	5
valid_sources[0x71]	811	1			T11	12		T26	1		T24	3
valid_sources[0x72]	691	1			T11	15		T23	2		T24	6
valid_sources[0x73]	631	1			T11	8		T23	1		T24	14
valid_sources[0x74]	785	1			T11	13		T23	2		T24	6
valid_sources[0x75]	855	1			T11	11		T23	9		T24	9
valid_sources[0x76]	862	1			T5	2		T11	10		T23	2
valid_sources[0x77]	718	1			T11	16		T23	6		T9	2
valid_sources[0x78]	1379	1			T11	12		T23	5		T9	8
valid_sources[0x79]	1006	1			T11	15		T23	5		T37	2
valid_sources[0x7a]	800	1			T11	8		T23	9		T24	12
valid_sources[0x7b]	639	1			T11	16		T14	2		T23	4
valid_sources[0x7c]	540	1			T11	9		T14	1		T23	2
valid_sources[0x7d]	1190	1			T11	12		T14	1		T23	14
valid_sources[0x7e]	558	1			T11	14		T24	5		T50	12
valid_sources[0x7f]	719	1			T11	14		T24	5		T51	1
valid_sources[0x80]	654	1			T11	12		T23	1		T24	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41787

1

T11

792

T15

6

T23

280

values[0x0]

all_enables

biggest_size

59794

1

T1

3

T3

47

T11

1108

values[0x1]

all_enables

biggest_size

56475

1

T1

2

T3

26

T4

1