Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16336246

1

T1

24827

T4

694

T5

5059

full_word

155722869

1

T1

249387

T3

196606

T4

3399

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	172058805	1			T1	274214		T3	196606		T4	4093
auto[TlIntgErrCmd]	98	1			T64	4		T65	2		T66	9
auto[TlIntgErrData]	103	1			T64	8		T65	5		T66	7
auto[TlIntgErrBoth]	109	1			T64	8		T65	3		T66	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82972381

1

T1

136782

T3

65536

T4

2109

auto[1]

89086734

1

T1

137432

T3

131070

T4

1984

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7994988	1			T1	12475		T4	366		T5	2493
auto[TlIntgErrNone]	partial	auto[1]	8340972	1			T1	12352		T4	328		T5	2566
auto[TlIntgErrNone]	full_word	auto[0]	74977260	1			T1	124307		T3	65536		T4	1743
auto[TlIntgErrNone]	full_word	auto[1]	80745585	1			T1	125080		T3	131070		T4	1656
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T64	2		T66	5		T137	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T64	1		T66	3		T138	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T64	1		T65	1		T66	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T65	1		T136	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T64	3		T65	1		T66	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T64	4		T65	2		T66	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T64	1		T65	1		T136	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T65	1		T138	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T64	3		T65	2		T66	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T64	5		T65	1		T66	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T66	1		T131	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T138	1		T134	2		T139	1