Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	816634	1			T1	8848		T37	3274		T30	4837
auto[1]	11481034	1			T1	6206		T4	2109		T5	11269
auto[2]	627947	1			T1	5664		T37	2423		T30	4364
auto[3]	11198225	1			T1	3182		T4	1983		T5	11188

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15305221	1			T1	18656		T4	2852		T5	18581
auto[1]	2264860	1			T1	2215		T4	546		T5	1816
auto[2]	2303003	1			T1	2739		T4	584		T5	1891
auto[3]	4250756	1			T1	290		T4	110		T5	169

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9753357

1

T1

23899

T4

4092

T5

22457

auto[1]

14370483

1

T1

1

T15

6

T37

24653

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	259969	1			T1	7315		T30	3987		T43	2150
auto[0]	auto[0]	auto[1]	27133	1			T1	724		T30	403		T60	10
auto[0]	auto[0]	auto[2]	27427	1			T1	748		T30	403		T60	10
auto[0]	auto[0]	auto[3]	46872	1			T1	61		T37	1		T30	44
auto[0]	auto[1]	auto[0]	3626730	1			T1	4778		T4	1476		T5	9362
auto[0]	auto[1]	auto[1]	372716	1			T1	854		T4	267		T5	874
auto[0]	auto[1]	auto[2]	384778	1			T1	486		T4	304		T5	949
auto[0]	auto[1]	auto[3]	289926	1			T1	87		T4	62		T5	84
auto[0]	auto[2]	auto[0]	175087	1			T1	4475		T30	3708		T43	1060
auto[0]	auto[2]	auto[1]	20815	1			T1	448		T30	373		T43	99
auto[0]	auto[2]	auto[2]	23616	1			T1	673		T30	256		T60	8
auto[0]	auto[2]	auto[3]	32930	1			T1	68		T30	27		T35	1
auto[0]	auto[3]	auto[0]	3461269	1			T1	2087		T4	1376		T5	9219
auto[0]	auto[3]	auto[1]	364789	1			T1	189		T4	279		T5	942
auto[0]	auto[3]	auto[2]	377079	1			T1	832		T4	280		T5	942
auto[0]	auto[3]	auto[3]	262221	1			T1	74		T4	48		T5	85
auto[1]	auto[0]	auto[0]	15208	1			T37	116		T128	1		T104	884
auto[1]	auto[0]	auto[1]	67521	1			T37	457		T43	1		T104	4027
auto[1]	auto[0]	auto[2]	67571	1			T37	485		T104	4112		T105	759
auto[1]	auto[0]	auto[3]	304933	1			T37	2215		T104	18668		T105	3418
auto[1]	auto[1]	auto[0]	3879618	1			T1	1		T15	1		T37	193
auto[1]	auto[1]	auto[1]	700589	1			T37	1551		T32	7034		T61	9551
auto[1]	auto[1]	auto[2]	675375	1			T37	935		T32	7684		T61	10331
auto[1]	auto[1]	auto[3]	1551302	1			T37	7165		T32	658		T61	43077
auto[1]	auto[2]	auto[0]	11797	1			T104	844		T140	1		T141	208
auto[1]	auto[2]	auto[1]	51780	1			T128	1		T104	3905		T141	809
auto[1]	auto[2]	auto[2]	56558	1			T37	425		T104	2703		T105	657
auto[1]	auto[2]	auto[3]	255364	1			T37	1998		T104	12555		T105	2991
auto[1]	auto[3]	auto[0]	3875543	1			T15	3		T37	101		T32	78621
auto[1]	auto[3]	auto[1]	659517	1			T15	1		T37	427		T32	7715
auto[1]	auto[3]	auto[2]	690599	1			T15	1		T37	1528		T32	7048
auto[1]	auto[3]	auto[3]	1507208	1			T37	7057		T32	693		T61	43582