Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1052530332	228711	0	0
ctrl_regwen_rd_A	1052530332	4358	0	0
exec_rd_A	1052530332	4263	0	0
exec_regwen_rd_A	1052530332	4550	0	0
readback_rd_A	1052530332	2417	0	0
readback_regwen_rd_A	1052530332	2394	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052530332	228711	0	0
T11	79898	3853	0	0
T12	75592	0	0	0
T13	41785	0	0	0
T14	690686	0	0	0
T15	494744	0	0	0
T16	917	0	0	0
T23	27453	1242	0	0
T24	0	2061	0	0
T36	106804	0	0	0
T37	110231	0	0	0
T38	72567	0	0	0
T46	0	3771	0	0
T49	0	2600	0	0
T70	0	1515	0	0
T71	0	7088	0	0
T72	0	1580	0	0
T73	0	8949	0	0
T74	0	3334	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052530332	4358	0	0
T18	916	0	0	0
T24	88835	258	0	0
T44	838375	0	0	0
T45	0	188	0	0
T49	0	93	0	0
T50	138501	0	0	0
T51	263466	0	0	0
T56	0	91	0	0
T62	73445	0	0	0
T63	38888	0	0	0
T71	0	508	0	0
T72	0	79	0	0
T123	0	196	0	0
T124	0	136	0	0
T125	0	253	0	0
T126	0	101	0	0
T127	807305	0	0	0
T128	168246	0	0	0
T129	72638	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052530332	4263	0	0
T18	916	0	0	0
T24	88835	234	0	0
T44	838375	0	0	0
T45	0	227	0	0
T49	0	130	0	0
T50	138501	0	0	0
T51	263466	0	0	0
T56	0	128	0	0
T62	73445	0	0	0
T63	38888	0	0	0
T71	0	444	0	0
T72	0	96	0	0
T123	0	206	0	0
T124	0	140	0	0
T125	0	199	0	0
T126	0	49	0	0
T127	807305	0	0	0
T128	168246	0	0	0
T129	72638	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052530332	4550	0	0
T18	916	0	0	0
T24	88835	274	0	0
T44	838375	0	0	0
T45	0	200	0	0
T49	0	129	0	0
T50	138501	0	0	0
T51	263466	0	0	0
T56	0	118	0	0
T62	73445	0	0	0
T63	38888	0	0	0
T71	0	551	0	0
T72	0	112	0	0
T123	0	272	0	0
T124	0	98	0	0
T125	0	283	0	0
T126	0	60	0	0
T127	807305	0	0	0
T128	168246	0	0	0
T129	72638	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052530332	2417	0	0
T18	916	0	0	0
T24	88835	225	0	0
T44	838375	0	0	0
T45	0	204	0	0
T49	0	46	0	0
T50	138501	0	0	0
T51	263466	0	0	0
T56	0	113	0	0
T62	73445	0	0	0
T63	38888	0	0	0
T71	0	467	0	0
T72	0	65	0	0
T123	0	187	0	0
T124	0	178	0	0
T125	0	226	0	0
T126	0	41	0	0
T127	807305	0	0	0
T128	168246	0	0	0
T129	72638	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052530332	2394	0	0
T18	916	0	0	0
T24	88835	230	0	0
T44	838375	0	0	0
T45	0	185	0	0
T49	0	84	0	0
T50	138501	0	0	0
T51	263466	0	0	0
T56	0	142	0	0
T62	73445	0	0	0
T63	38888	0	0	0
T71	0	443	0	0
T72	0	81	0	0
T123	0	101	0	0
T124	0	130	0	0
T125	0	210	0	0
T126	0	48	0	0
T127	807305	0	0	0
T128	168246	0	0	0
T129	72638	0	0	0