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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 99.19 94.27 99.72 100.00 96.03 99.12 97.44


Total test records in report: 1032
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T542 /workspace/coverage/default/14.sram_ctrl_mem_walk.332086515 Jul 21 07:07:31 PM PDT 24 Jul 21 07:11:02 PM PDT 24 114662642566 ps
T543 /workspace/coverage/default/1.sram_ctrl_multiple_keys.3215733926 Jul 21 07:06:43 PM PDT 24 Jul 21 07:21:59 PM PDT 24 32994122426 ps
T544 /workspace/coverage/default/10.sram_ctrl_bijection.3467836870 Jul 21 07:07:17 PM PDT 24 Jul 21 07:20:41 PM PDT 24 45095397853 ps
T545 /workspace/coverage/default/11.sram_ctrl_alert_test.3793069447 Jul 21 07:07:31 PM PDT 24 Jul 21 07:07:33 PM PDT 24 21507231 ps
T546 /workspace/coverage/default/13.sram_ctrl_multiple_keys.1387854724 Jul 21 07:07:18 PM PDT 24 Jul 21 07:19:04 PM PDT 24 18771903142 ps
T547 /workspace/coverage/default/4.sram_ctrl_alert_test.156511720 Jul 21 07:07:05 PM PDT 24 Jul 21 07:07:06 PM PDT 24 14473434 ps
T548 /workspace/coverage/default/45.sram_ctrl_partial_access.3221576786 Jul 21 07:10:19 PM PDT 24 Jul 21 07:10:37 PM PDT 24 6734190326 ps
T549 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.126945410 Jul 21 07:10:34 PM PDT 24 Jul 21 07:10:45 PM PDT 24 1377676631 ps
T550 /workspace/coverage/default/9.sram_ctrl_alert_test.4267999843 Jul 21 07:07:18 PM PDT 24 Jul 21 07:07:22 PM PDT 24 23735968 ps
T551 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3300438287 Jul 21 07:10:55 PM PDT 24 Jul 21 07:24:36 PM PDT 24 49674385564 ps
T552 /workspace/coverage/default/35.sram_ctrl_executable.3426263381 Jul 21 07:08:57 PM PDT 24 Jul 21 07:21:37 PM PDT 24 29812514380 ps
T553 /workspace/coverage/default/5.sram_ctrl_ram_cfg.3656221041 Jul 21 07:07:05 PM PDT 24 Jul 21 07:07:08 PM PDT 24 1401165254 ps
T554 /workspace/coverage/default/1.sram_ctrl_executable.106126010 Jul 21 07:06:44 PM PDT 24 Jul 21 07:18:31 PM PDT 24 3339531036 ps
T555 /workspace/coverage/default/39.sram_ctrl_regwen.360265722 Jul 21 07:09:28 PM PDT 24 Jul 21 07:22:42 PM PDT 24 24478292637 ps
T556 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1054384422 Jul 21 07:07:12 PM PDT 24 Jul 21 07:09:44 PM PDT 24 4755391515 ps
T557 /workspace/coverage/default/44.sram_ctrl_regwen.3506752399 Jul 21 07:10:16 PM PDT 24 Jul 21 07:22:14 PM PDT 24 2711532494 ps
T558 /workspace/coverage/default/0.sram_ctrl_stress_all.2550661796 Jul 21 07:06:40 PM PDT 24 Jul 21 08:05:38 PM PDT 24 1376238358274 ps
T559 /workspace/coverage/default/27.sram_ctrl_lc_escalation.1019595287 Jul 21 07:08:07 PM PDT 24 Jul 21 07:09:22 PM PDT 24 13384289654 ps
T560 /workspace/coverage/default/41.sram_ctrl_mem_walk.414035529 Jul 21 07:09:51 PM PDT 24 Jul 21 07:15:35 PM PDT 24 20715766842 ps
T561 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.4028363058 Jul 21 07:08:07 PM PDT 24 Jul 21 07:09:12 PM PDT 24 4358604365 ps
T562 /workspace/coverage/default/12.sram_ctrl_max_throughput.2989703632 Jul 21 07:07:17 PM PDT 24 Jul 21 07:07:58 PM PDT 24 752965544 ps
T563 /workspace/coverage/default/39.sram_ctrl_alert_test.3778946815 Jul 21 07:09:35 PM PDT 24 Jul 21 07:09:36 PM PDT 24 15500053 ps
T564 /workspace/coverage/default/34.sram_ctrl_stress_all.3858604110 Jul 21 07:08:52 PM PDT 24 Jul 21 07:34:01 PM PDT 24 53419746804 ps
T565 /workspace/coverage/default/20.sram_ctrl_partial_access.1620333223 Jul 21 07:07:27 PM PDT 24 Jul 21 07:07:51 PM PDT 24 6828961728 ps
T566 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1958764508 Jul 21 07:07:31 PM PDT 24 Jul 21 07:13:32 PM PDT 24 25081232002 ps
T567 /workspace/coverage/default/22.sram_ctrl_mem_walk.225525493 Jul 21 07:07:42 PM PDT 24 Jul 21 07:13:59 PM PDT 24 114964587536 ps
T568 /workspace/coverage/default/38.sram_ctrl_regwen.4110583204 Jul 21 07:09:18 PM PDT 24 Jul 21 07:40:25 PM PDT 24 4889889725 ps
T569 /workspace/coverage/default/42.sram_ctrl_mem_walk.2526128908 Jul 21 07:10:01 PM PDT 24 Jul 21 07:15:40 PM PDT 24 43315821913 ps
T570 /workspace/coverage/default/49.sram_ctrl_multiple_keys.23148573 Jul 21 07:10:55 PM PDT 24 Jul 21 07:13:29 PM PDT 24 4337695577 ps
T571 /workspace/coverage/default/40.sram_ctrl_multiple_keys.4207838405 Jul 21 07:09:32 PM PDT 24 Jul 21 07:20:09 PM PDT 24 9772946867 ps
T572 /workspace/coverage/default/45.sram_ctrl_max_throughput.1712957153 Jul 21 07:10:20 PM PDT 24 Jul 21 07:10:59 PM PDT 24 728739797 ps
T573 /workspace/coverage/default/47.sram_ctrl_ram_cfg.3133853049 Jul 21 07:10:38 PM PDT 24 Jul 21 07:10:41 PM PDT 24 1403677131 ps
T574 /workspace/coverage/default/46.sram_ctrl_ram_cfg.1493768655 Jul 21 07:10:30 PM PDT 24 Jul 21 07:10:34 PM PDT 24 391815564 ps
T575 /workspace/coverage/default/2.sram_ctrl_regwen.1673330139 Jul 21 07:07:01 PM PDT 24 Jul 21 07:26:41 PM PDT 24 13680069886 ps
T576 /workspace/coverage/default/15.sram_ctrl_executable.2431714114 Jul 21 07:07:19 PM PDT 24 Jul 21 07:22:49 PM PDT 24 80921991379 ps
T577 /workspace/coverage/default/35.sram_ctrl_regwen.143719246 Jul 21 07:09:00 PM PDT 24 Jul 21 07:15:22 PM PDT 24 6629408966 ps
T578 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.539560090 Jul 21 07:08:04 PM PDT 24 Jul 21 07:08:39 PM PDT 24 1138717795 ps
T579 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.760247942 Jul 21 07:08:47 PM PDT 24 Jul 21 07:12:09 PM PDT 24 31753587473 ps
T580 /workspace/coverage/default/8.sram_ctrl_ram_cfg.911839039 Jul 21 07:07:20 PM PDT 24 Jul 21 07:07:26 PM PDT 24 360555546 ps
T581 /workspace/coverage/default/42.sram_ctrl_regwen.1387454620 Jul 21 07:10:00 PM PDT 24 Jul 21 07:33:53 PM PDT 24 18712011753 ps
T582 /workspace/coverage/default/11.sram_ctrl_max_throughput.457355821 Jul 21 07:07:24 PM PDT 24 Jul 21 07:10:01 PM PDT 24 4239296153 ps
T583 /workspace/coverage/default/8.sram_ctrl_stress_all.840574144 Jul 21 07:07:07 PM PDT 24 Jul 21 08:35:30 PM PDT 24 124584294202 ps
T584 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.251465091 Jul 21 07:09:55 PM PDT 24 Jul 21 07:18:11 PM PDT 24 81188228896 ps
T585 /workspace/coverage/default/9.sram_ctrl_max_throughput.1676638972 Jul 21 07:07:22 PM PDT 24 Jul 21 07:08:34 PM PDT 24 2769104435 ps
T586 /workspace/coverage/default/25.sram_ctrl_alert_test.2930435809 Jul 21 07:08:03 PM PDT 24 Jul 21 07:08:04 PM PDT 24 43482211 ps
T587 /workspace/coverage/default/32.sram_ctrl_alert_test.2677768239 Jul 21 07:08:43 PM PDT 24 Jul 21 07:08:44 PM PDT 24 14271235 ps
T588 /workspace/coverage/default/47.sram_ctrl_max_throughput.630995644 Jul 21 07:10:35 PM PDT 24 Jul 21 07:13:01 PM PDT 24 780670386 ps
T589 /workspace/coverage/default/35.sram_ctrl_mem_walk.3611153917 Jul 21 07:08:57 PM PDT 24 Jul 21 07:14:42 PM PDT 24 21138196922 ps
T590 /workspace/coverage/default/35.sram_ctrl_ram_cfg.9587295 Jul 21 07:08:58 PM PDT 24 Jul 21 07:09:02 PM PDT 24 970172249 ps
T591 /workspace/coverage/default/42.sram_ctrl_smoke.379249181 Jul 21 07:10:00 PM PDT 24 Jul 21 07:10:11 PM PDT 24 1944177274 ps
T592 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.881707019 Jul 21 07:10:57 PM PDT 24 Jul 21 07:13:48 PM PDT 24 7799031555 ps
T593 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2038645239 Jul 21 07:10:31 PM PDT 24 Jul 21 07:12:40 PM PDT 24 3240149974 ps
T594 /workspace/coverage/default/14.sram_ctrl_max_throughput.1487662613 Jul 21 07:07:31 PM PDT 24 Jul 21 07:07:56 PM PDT 24 711001404 ps
T595 /workspace/coverage/default/11.sram_ctrl_regwen.3701650541 Jul 21 07:07:20 PM PDT 24 Jul 21 07:19:00 PM PDT 24 50338119287 ps
T596 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1402752719 Jul 21 07:09:41 PM PDT 24 Jul 21 07:10:01 PM PDT 24 707522120 ps
T597 /workspace/coverage/default/21.sram_ctrl_regwen.3898869075 Jul 21 07:07:40 PM PDT 24 Jul 21 07:10:45 PM PDT 24 14107195676 ps
T598 /workspace/coverage/default/3.sram_ctrl_stress_all.897957498 Jul 21 07:06:58 PM PDT 24 Jul 21 09:02:09 PM PDT 24 273585025418 ps
T599 /workspace/coverage/default/0.sram_ctrl_ram_cfg.2489551728 Jul 21 07:06:50 PM PDT 24 Jul 21 07:06:54 PM PDT 24 365302894 ps
T600 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.31128594 Jul 21 07:09:41 PM PDT 24 Jul 21 07:27:13 PM PDT 24 9683741091 ps
T601 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3622678172 Jul 21 07:07:15 PM PDT 24 Jul 21 07:09:29 PM PDT 24 817733169 ps
T602 /workspace/coverage/default/39.sram_ctrl_executable.2966672950 Jul 21 07:09:28 PM PDT 24 Jul 21 07:21:38 PM PDT 24 27777392751 ps
T603 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.885183451 Jul 21 07:06:54 PM PDT 24 Jul 21 07:19:36 PM PDT 24 36285234578 ps
T604 /workspace/coverage/default/42.sram_ctrl_partial_access.2606951617 Jul 21 07:09:56 PM PDT 24 Jul 21 07:10:15 PM PDT 24 1369863998 ps
T605 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3112293008 Jul 21 07:10:20 PM PDT 24 Jul 21 07:19:31 PM PDT 24 57158008851 ps
T606 /workspace/coverage/default/3.sram_ctrl_smoke.1449078906 Jul 21 07:07:10 PM PDT 24 Jul 21 07:08:12 PM PDT 24 1664193566 ps
T607 /workspace/coverage/default/13.sram_ctrl_regwen.1148854181 Jul 21 07:07:22 PM PDT 24 Jul 21 07:15:21 PM PDT 24 2718072155 ps
T28 /workspace/coverage/default/4.sram_ctrl_sec_cm.3161983665 Jul 21 07:07:00 PM PDT 24 Jul 21 07:07:04 PM PDT 24 259805193 ps
T608 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.172570548 Jul 21 07:10:26 PM PDT 24 Jul 21 07:12:34 PM PDT 24 5832428046 ps
T609 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2834287101 Jul 21 07:07:22 PM PDT 24 Jul 21 07:08:58 PM PDT 24 15287336903 ps
T610 /workspace/coverage/default/47.sram_ctrl_executable.926563457 Jul 21 07:10:36 PM PDT 24 Jul 21 07:13:24 PM PDT 24 15076584690 ps
T611 /workspace/coverage/default/30.sram_ctrl_executable.2996539661 Jul 21 07:08:25 PM PDT 24 Jul 21 07:28:26 PM PDT 24 92385176965 ps
T612 /workspace/coverage/default/6.sram_ctrl_multiple_keys.1473210180 Jul 21 07:07:00 PM PDT 24 Jul 21 07:22:26 PM PDT 24 12863569878 ps
T613 /workspace/coverage/default/0.sram_ctrl_bijection.2784121654 Jul 21 07:06:42 PM PDT 24 Jul 21 07:58:30 PM PDT 24 143642749706 ps
T614 /workspace/coverage/default/37.sram_ctrl_executable.1432768005 Jul 21 07:09:10 PM PDT 24 Jul 21 07:25:13 PM PDT 24 231977687072 ps
T615 /workspace/coverage/default/9.sram_ctrl_regwen.4176069309 Jul 21 07:07:15 PM PDT 24 Jul 21 07:18:55 PM PDT 24 19114061730 ps
T616 /workspace/coverage/default/39.sram_ctrl_ram_cfg.1284680175 Jul 21 07:09:29 PM PDT 24 Jul 21 07:09:33 PM PDT 24 353427438 ps
T617 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.702260563 Jul 21 07:07:34 PM PDT 24 Jul 21 07:11:42 PM PDT 24 12515871285 ps
T618 /workspace/coverage/default/30.sram_ctrl_mem_walk.95569421 Jul 21 07:08:26 PM PDT 24 Jul 21 07:13:36 PM PDT 24 20997018359 ps
T619 /workspace/coverage/default/1.sram_ctrl_max_throughput.3469877846 Jul 21 07:07:03 PM PDT 24 Jul 21 07:07:13 PM PDT 24 860092964 ps
T620 /workspace/coverage/default/23.sram_ctrl_partial_access.1515426147 Jul 21 07:07:45 PM PDT 24 Jul 21 07:08:11 PM PDT 24 12043996083 ps
T621 /workspace/coverage/default/4.sram_ctrl_smoke.4059689851 Jul 21 07:07:13 PM PDT 24 Jul 21 07:07:26 PM PDT 24 10389807329 ps
T622 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3078242016 Jul 21 07:07:22 PM PDT 24 Jul 21 07:13:18 PM PDT 24 50095286908 ps
T623 /workspace/coverage/default/32.sram_ctrl_bijection.3886312866 Jul 21 07:08:31 PM PDT 24 Jul 21 07:35:01 PM PDT 24 88794625405 ps
T624 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.1046166786 Jul 21 07:08:58 PM PDT 24 Jul 21 07:26:08 PM PDT 24 11968607853 ps
T625 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1828010974 Jul 21 07:08:06 PM PDT 24 Jul 21 07:08:09 PM PDT 24 358034280 ps
T626 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4264836579 Jul 21 07:09:18 PM PDT 24 Jul 21 07:11:52 PM PDT 24 3232060027 ps
T627 /workspace/coverage/default/46.sram_ctrl_executable.4116453774 Jul 21 07:10:30 PM PDT 24 Jul 21 07:15:35 PM PDT 24 1383697509 ps
T628 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3777818777 Jul 21 07:07:11 PM PDT 24 Jul 21 07:07:20 PM PDT 24 795244802 ps
T629 /workspace/coverage/default/21.sram_ctrl_alert_test.1517622326 Jul 21 07:07:39 PM PDT 24 Jul 21 07:07:40 PM PDT 24 12966172 ps
T630 /workspace/coverage/default/26.sram_ctrl_mem_walk.4282471894 Jul 21 07:08:06 PM PDT 24 Jul 21 07:14:15 PM PDT 24 38219319410 ps
T631 /workspace/coverage/default/13.sram_ctrl_partial_access.1784163285 Jul 21 07:07:20 PM PDT 24 Jul 21 07:07:33 PM PDT 24 758024686 ps
T632 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.4086969689 Jul 21 07:07:04 PM PDT 24 Jul 21 07:09:25 PM PDT 24 2914547754 ps
T633 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.939682293 Jul 21 07:10:16 PM PDT 24 Jul 21 07:17:44 PM PDT 24 237078177530 ps
T634 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3344430357 Jul 21 07:10:02 PM PDT 24 Jul 21 07:26:03 PM PDT 24 15344814316 ps
T635 /workspace/coverage/default/24.sram_ctrl_max_throughput.592273464 Jul 21 07:07:55 PM PDT 24 Jul 21 07:09:47 PM PDT 24 1486359008 ps
T636 /workspace/coverage/default/49.sram_ctrl_smoke.3493144890 Jul 21 07:10:56 PM PDT 24 Jul 21 07:11:25 PM PDT 24 1879795539 ps
T637 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2585804790 Jul 21 07:07:16 PM PDT 24 Jul 21 07:10:03 PM PDT 24 808172695 ps
T638 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4215223678 Jul 21 07:10:47 PM PDT 24 Jul 21 07:17:58 PM PDT 24 20673544143 ps
T639 /workspace/coverage/default/13.sram_ctrl_lc_escalation.140535003 Jul 21 07:07:25 PM PDT 24 Jul 21 07:08:44 PM PDT 24 12502925051 ps
T640 /workspace/coverage/default/19.sram_ctrl_regwen.2289346352 Jul 21 07:07:35 PM PDT 24 Jul 21 07:09:24 PM PDT 24 5519197445 ps
T641 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.68168326 Jul 21 07:09:33 PM PDT 24 Jul 21 07:14:33 PM PDT 24 17951020225 ps
T642 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2358556612 Jul 21 07:08:33 PM PDT 24 Jul 21 07:12:32 PM PDT 24 14847194928 ps
T643 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2296172328 Jul 21 07:09:16 PM PDT 24 Jul 21 07:13:31 PM PDT 24 3525945846 ps
T644 /workspace/coverage/default/33.sram_ctrl_multiple_keys.3380068019 Jul 21 07:08:42 PM PDT 24 Jul 21 07:35:27 PM PDT 24 140213861693 ps
T645 /workspace/coverage/default/24.sram_ctrl_executable.457325825 Jul 21 07:07:50 PM PDT 24 Jul 21 07:20:01 PM PDT 24 50594013317 ps
T646 /workspace/coverage/default/13.sram_ctrl_max_throughput.1525869775 Jul 21 07:07:25 PM PDT 24 Jul 21 07:08:13 PM PDT 24 1459522127 ps
T647 /workspace/coverage/default/38.sram_ctrl_mem_walk.1772419110 Jul 21 07:09:15 PM PDT 24 Jul 21 07:11:22 PM PDT 24 2017404367 ps
T648 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1721044789 Jul 21 07:08:48 PM PDT 24 Jul 21 07:10:00 PM PDT 24 991547332 ps
T649 /workspace/coverage/default/28.sram_ctrl_mem_walk.2427080270 Jul 21 07:08:14 PM PDT 24 Jul 21 07:13:40 PM PDT 24 27722852300 ps
T650 /workspace/coverage/default/0.sram_ctrl_max_throughput.282217377 Jul 21 07:06:39 PM PDT 24 Jul 21 07:07:16 PM PDT 24 2856494683 ps
T651 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1583733055 Jul 21 07:07:26 PM PDT 24 Jul 21 07:36:17 PM PDT 24 14638739636 ps
T652 /workspace/coverage/default/5.sram_ctrl_mem_walk.1907438195 Jul 21 07:07:13 PM PDT 24 Jul 21 07:09:44 PM PDT 24 4383974437 ps
T653 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2335893433 Jul 21 07:07:29 PM PDT 24 Jul 21 07:10:06 PM PDT 24 8623174629 ps
T125 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.590060560 Jul 21 07:07:16 PM PDT 24 Jul 21 07:07:48 PM PDT 24 2050753113 ps
T654 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3912489073 Jul 21 07:08:32 PM PDT 24 Jul 21 07:11:33 PM PDT 24 3388647923 ps
T655 /workspace/coverage/default/23.sram_ctrl_stress_all.3457900497 Jul 21 07:07:51 PM PDT 24 Jul 21 07:28:21 PM PDT 24 158588059276 ps
T656 /workspace/coverage/default/45.sram_ctrl_ram_cfg.2180195018 Jul 21 07:10:25 PM PDT 24 Jul 21 07:10:29 PM PDT 24 3076244110 ps
T657 /workspace/coverage/default/8.sram_ctrl_partial_access.2377600567 Jul 21 07:07:15 PM PDT 24 Jul 21 07:07:21 PM PDT 24 1400111717 ps
T658 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2781091621 Jul 21 07:10:49 PM PDT 24 Jul 21 07:38:14 PM PDT 24 15077624119 ps
T659 /workspace/coverage/default/44.sram_ctrl_max_throughput.387661129 Jul 21 07:10:17 PM PDT 24 Jul 21 07:10:39 PM PDT 24 5012072700 ps
T660 /workspace/coverage/default/48.sram_ctrl_mem_walk.3926579116 Jul 21 07:10:49 PM PDT 24 Jul 21 07:13:39 PM PDT 24 21132023135 ps
T661 /workspace/coverage/default/46.sram_ctrl_alert_test.2058975467 Jul 21 07:10:36 PM PDT 24 Jul 21 07:10:37 PM PDT 24 33168692 ps
T662 /workspace/coverage/default/22.sram_ctrl_lc_escalation.1322331671 Jul 21 07:07:44 PM PDT 24 Jul 21 07:08:45 PM PDT 24 38619515024 ps
T663 /workspace/coverage/default/42.sram_ctrl_ram_cfg.2352742373 Jul 21 07:10:02 PM PDT 24 Jul 21 07:10:06 PM PDT 24 509116250 ps
T664 /workspace/coverage/default/5.sram_ctrl_max_throughput.1653782527 Jul 21 07:07:08 PM PDT 24 Jul 21 07:09:08 PM PDT 24 789590117 ps
T665 /workspace/coverage/default/21.sram_ctrl_multiple_keys.2711656566 Jul 21 07:07:28 PM PDT 24 Jul 21 07:33:13 PM PDT 24 43125164308 ps
T666 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2968657172 Jul 21 07:07:11 PM PDT 24 Jul 21 07:07:37 PM PDT 24 1364984023 ps
T667 /workspace/coverage/default/46.sram_ctrl_multiple_keys.160887392 Jul 21 07:10:27 PM PDT 24 Jul 21 07:28:48 PM PDT 24 95493649921 ps
T668 /workspace/coverage/default/34.sram_ctrl_alert_test.2333118702 Jul 21 07:08:52 PM PDT 24 Jul 21 07:08:53 PM PDT 24 41249773 ps
T669 /workspace/coverage/default/34.sram_ctrl_lc_escalation.3241114554 Jul 21 07:08:49 PM PDT 24 Jul 21 07:09:55 PM PDT 24 36299423582 ps
T670 /workspace/coverage/default/33.sram_ctrl_bijection.3270767388 Jul 21 07:08:43 PM PDT 24 Jul 21 07:49:25 PM PDT 24 776154761646 ps
T29 /workspace/coverage/default/0.sram_ctrl_sec_cm.1461254768 Jul 21 07:06:41 PM PDT 24 Jul 21 07:06:43 PM PDT 24 121653578 ps
T671 /workspace/coverage/default/26.sram_ctrl_smoke.4226707208 Jul 21 07:08:02 PM PDT 24 Jul 21 07:09:21 PM PDT 24 2861438834 ps
T672 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.302239794 Jul 21 07:08:31 PM PDT 24 Jul 21 07:10:01 PM PDT 24 818563518 ps
T673 /workspace/coverage/default/19.sram_ctrl_mem_partial_access.3351397967 Jul 21 07:07:21 PM PDT 24 Jul 21 07:10:01 PM PDT 24 9161129313 ps
T674 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3603175131 Jul 21 07:09:29 PM PDT 24 Jul 21 07:10:35 PM PDT 24 992256438 ps
T675 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3266949124 Jul 21 07:09:42 PM PDT 24 Jul 21 07:17:44 PM PDT 24 36848960209 ps
T676 /workspace/coverage/default/22.sram_ctrl_ram_cfg.151789313 Jul 21 07:07:51 PM PDT 24 Jul 21 07:07:55 PM PDT 24 355199441 ps
T677 /workspace/coverage/default/13.sram_ctrl_mem_walk.199150526 Jul 21 07:07:28 PM PDT 24 Jul 21 07:10:09 PM PDT 24 31429315419 ps
T678 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1071680798 Jul 21 07:11:01 PM PDT 24 Jul 21 07:12:24 PM PDT 24 1469747050 ps
T679 /workspace/coverage/default/33.sram_ctrl_stress_all.1300602234 Jul 21 07:08:48 PM PDT 24 Jul 21 08:42:51 PM PDT 24 813355283514 ps
T680 /workspace/coverage/default/49.sram_ctrl_regwen.959288285 Jul 21 07:10:54 PM PDT 24 Jul 21 07:35:44 PM PDT 24 31503240705 ps
T681 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3722679700 Jul 21 07:08:01 PM PDT 24 Jul 21 07:09:48 PM PDT 24 1590610597 ps
T682 /workspace/coverage/default/32.sram_ctrl_multiple_keys.1514900626 Jul 21 07:08:31 PM PDT 24 Jul 21 07:09:55 PM PDT 24 3875534009 ps
T683 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1796038595 Jul 21 07:08:02 PM PDT 24 Jul 21 07:09:45 PM PDT 24 4025106268 ps
T684 /workspace/coverage/default/17.sram_ctrl_ram_cfg.963118166 Jul 21 07:07:25 PM PDT 24 Jul 21 07:07:31 PM PDT 24 713558018 ps
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T688 /workspace/coverage/default/49.sram_ctrl_stress_all.150195168 Jul 21 07:10:58 PM PDT 24 Jul 21 08:58:32 PM PDT 24 31748323891 ps
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T692 /workspace/coverage/default/39.sram_ctrl_max_throughput.1051670646 Jul 21 07:09:21 PM PDT 24 Jul 21 07:09:33 PM PDT 24 2716864394 ps
T693 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3155893455 Jul 21 07:10:48 PM PDT 24 Jul 21 07:12:06 PM PDT 24 11781844028 ps
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T696 /workspace/coverage/default/49.sram_ctrl_ram_cfg.52516184 Jul 21 07:10:54 PM PDT 24 Jul 21 07:10:58 PM PDT 24 652982885 ps
T697 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3449734909 Jul 21 07:10:19 PM PDT 24 Jul 21 07:11:16 PM PDT 24 2974574501 ps
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T699 /workspace/coverage/default/8.sram_ctrl_max_throughput.3092686052 Jul 21 07:07:16 PM PDT 24 Jul 21 07:08:06 PM PDT 24 2918779198 ps
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T701 /workspace/coverage/default/18.sram_ctrl_partial_access.3967342178 Jul 21 07:07:29 PM PDT 24 Jul 21 07:07:35 PM PDT 24 757843195 ps
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T703 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3380943096 Jul 21 07:06:41 PM PDT 24 Jul 21 07:32:49 PM PDT 24 20741842809 ps
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T705 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1458896798 Jul 21 07:07:17 PM PDT 24 Jul 21 07:15:06 PM PDT 24 10072389937 ps
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T713 /workspace/coverage/default/40.sram_ctrl_ram_cfg.3069493369 Jul 21 07:09:39 PM PDT 24 Jul 21 07:09:43 PM PDT 24 5587411205 ps
T714 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2062410569 Jul 21 07:07:45 PM PDT 24 Jul 21 07:08:26 PM PDT 24 731669841 ps
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T716 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.4273117165 Jul 21 07:07:29 PM PDT 24 Jul 21 07:14:45 PM PDT 24 68817721405 ps
T717 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2899611905 Jul 21 07:07:17 PM PDT 24 Jul 21 07:10:10 PM PDT 24 23164288215 ps
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T719 /workspace/coverage/default/24.sram_ctrl_lc_escalation.387170927 Jul 21 07:07:50 PM PDT 24 Jul 21 07:08:42 PM PDT 24 16070091333 ps
T720 /workspace/coverage/default/28.sram_ctrl_alert_test.3176520301 Jul 21 07:08:12 PM PDT 24 Jul 21 07:08:13 PM PDT 24 12765579 ps
T721 /workspace/coverage/default/44.sram_ctrl_stress_all.1779159759 Jul 21 07:10:19 PM PDT 24 Jul 21 08:04:53 PM PDT 24 229209400637 ps
T722 /workspace/coverage/default/26.sram_ctrl_max_throughput.3771576877 Jul 21 07:08:03 PM PDT 24 Jul 21 07:08:22 PM PDT 24 1786948609 ps
T723 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3573675782 Jul 21 07:09:05 PM PDT 24 Jul 21 07:10:17 PM PDT 24 2016892794 ps
T724 /workspace/coverage/default/9.sram_ctrl_lc_escalation.2831858684 Jul 21 07:07:22 PM PDT 24 Jul 21 07:08:27 PM PDT 24 19422020158 ps
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T729 /workspace/coverage/default/29.sram_ctrl_partial_access.3991558887 Jul 21 07:08:12 PM PDT 24 Jul 21 07:08:38 PM PDT 24 5851566125 ps
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T731 /workspace/coverage/default/6.sram_ctrl_regwen.2955399479 Jul 21 07:07:13 PM PDT 24 Jul 21 07:20:24 PM PDT 24 52983307370 ps
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T733 /workspace/coverage/default/19.sram_ctrl_mem_walk.2666041837 Jul 21 07:07:41 PM PDT 24 Jul 21 07:10:31 PM PDT 24 10768805732 ps
T734 /workspace/coverage/default/30.sram_ctrl_partial_access.1527352372 Jul 21 07:08:17 PM PDT 24 Jul 21 07:09:39 PM PDT 24 8065940251 ps
T735 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.175942172 Jul 21 07:07:06 PM PDT 24 Jul 21 07:07:14 PM PDT 24 395138745 ps
T736 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2133013698 Jul 21 07:10:54 PM PDT 24 Jul 21 07:11:35 PM PDT 24 5150302319 ps
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T738 /workspace/coverage/default/18.sram_ctrl_lc_escalation.2363500299 Jul 21 07:07:33 PM PDT 24 Jul 21 07:09:09 PM PDT 24 22386005775 ps
T739 /workspace/coverage/default/28.sram_ctrl_stress_all.3887498328 Jul 21 07:08:13 PM PDT 24 Jul 21 07:47:09 PM PDT 24 89920974649 ps
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T741 /workspace/coverage/default/40.sram_ctrl_mem_walk.3840823637 Jul 21 07:09:38 PM PDT 24 Jul 21 07:12:11 PM PDT 24 5372443250 ps
T742 /workspace/coverage/default/43.sram_ctrl_max_throughput.212385265 Jul 21 07:10:09 PM PDT 24 Jul 21 07:12:44 PM PDT 24 3046388862 ps
T743 /workspace/coverage/default/32.sram_ctrl_lc_escalation.2266408857 Jul 21 07:08:32 PM PDT 24 Jul 21 07:09:09 PM PDT 24 5903288777 ps
T744 /workspace/coverage/default/33.sram_ctrl_lc_escalation.2071842285 Jul 21 07:08:43 PM PDT 24 Jul 21 07:10:08 PM PDT 24 130605424015 ps
T745 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.4274135189 Jul 21 07:06:59 PM PDT 24 Jul 21 07:08:19 PM PDT 24 9404976748 ps
T746 /workspace/coverage/default/44.sram_ctrl_lc_escalation.3903146166 Jul 21 07:10:18 PM PDT 24 Jul 21 07:11:00 PM PDT 24 6875127404 ps
T747 /workspace/coverage/default/22.sram_ctrl_partial_access.2333743291 Jul 21 07:07:41 PM PDT 24 Jul 21 07:07:55 PM PDT 24 520161842 ps
T748 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2061546697 Jul 21 07:07:39 PM PDT 24 Jul 21 07:12:40 PM PDT 24 14361169062 ps
T749 /workspace/coverage/default/35.sram_ctrl_bijection.85213742 Jul 21 07:08:52 PM PDT 24 Jul 21 07:47:18 PM PDT 24 39808197617 ps
T750 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.411667683 Jul 21 07:06:56 PM PDT 24 Jul 21 07:12:43 PM PDT 24 11616424074 ps
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T752 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.5410937 Jul 21 07:07:18 PM PDT 24 Jul 21 07:13:15 PM PDT 24 11796120056 ps
T753 /workspace/coverage/default/6.sram_ctrl_lc_escalation.3172551345 Jul 21 07:07:14 PM PDT 24 Jul 21 07:07:52 PM PDT 24 15556187664 ps
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T757 /workspace/coverage/default/2.sram_ctrl_ram_cfg.3461212257 Jul 21 07:06:51 PM PDT 24 Jul 21 07:06:55 PM PDT 24 358232175 ps
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T759 /workspace/coverage/default/21.sram_ctrl_lc_escalation.3376664736 Jul 21 07:07:39 PM PDT 24 Jul 21 07:08:41 PM PDT 24 10666226901 ps
T760 /workspace/coverage/default/31.sram_ctrl_executable.281574869 Jul 21 07:08:31 PM PDT 24 Jul 21 07:25:46 PM PDT 24 18872375301 ps
T761 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.616879776 Jul 21 07:07:27 PM PDT 24 Jul 21 07:07:55 PM PDT 24 744296181 ps
T762 /workspace/coverage/default/0.sram_ctrl_regwen.2645466270 Jul 21 07:06:51 PM PDT 24 Jul 21 07:23:29 PM PDT 24 11703478783 ps
T763 /workspace/coverage/default/36.sram_ctrl_partial_access.1737012123 Jul 21 07:09:04 PM PDT 24 Jul 21 07:10:21 PM PDT 24 870339273 ps
T764 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.366688131 Jul 21 07:07:23 PM PDT 24 Jul 21 07:12:46 PM PDT 24 17647598921 ps
T765 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.357276903 Jul 21 07:08:40 PM PDT 24 Jul 21 07:32:24 PM PDT 24 13266300226 ps
T766 /workspace/coverage/default/41.sram_ctrl_lc_escalation.524004858 Jul 21 07:09:49 PM PDT 24 Jul 21 07:10:57 PM PDT 24 21412802944 ps
T767 /workspace/coverage/default/5.sram_ctrl_regwen.1512284116 Jul 21 07:07:01 PM PDT 24 Jul 21 07:18:33 PM PDT 24 19753917546 ps
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T769 /workspace/coverage/default/12.sram_ctrl_lc_escalation.2281376766 Jul 21 07:07:18 PM PDT 24 Jul 21 07:07:57 PM PDT 24 8937370011 ps
T770 /workspace/coverage/default/43.sram_ctrl_partial_access.4234316981 Jul 21 07:10:07 PM PDT 24 Jul 21 07:10:32 PM PDT 24 3116146811 ps
T771 /workspace/coverage/default/11.sram_ctrl_mem_walk.2861038997 Jul 21 07:07:17 PM PDT 24 Jul 21 07:09:54 PM PDT 24 10963375607 ps
T772 /workspace/coverage/default/9.sram_ctrl_multiple_keys.227551740 Jul 21 07:07:02 PM PDT 24 Jul 21 07:16:43 PM PDT 24 10897387618 ps
T773 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1072104041 Jul 21 07:07:51 PM PDT 24 Jul 21 07:15:31 PM PDT 24 5750355976 ps
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T775 /workspace/coverage/default/48.sram_ctrl_max_throughput.3442040590 Jul 21 07:10:47 PM PDT 24 Jul 21 07:11:21 PM PDT 24 7133497309 ps
T776 /workspace/coverage/default/29.sram_ctrl_max_throughput.499078519 Jul 21 07:08:12 PM PDT 24 Jul 21 07:09:53 PM PDT 24 10619322822 ps
T777 /workspace/coverage/default/11.sram_ctrl_partial_access.3883239389 Jul 21 07:07:23 PM PDT 24 Jul 21 07:08:28 PM PDT 24 456756522 ps
T778 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.881834767 Jul 21 07:07:10 PM PDT 24 Jul 21 07:08:25 PM PDT 24 2403472797 ps
T779 /workspace/coverage/default/21.sram_ctrl_mem_walk.503924909 Jul 21 07:07:47 PM PDT 24 Jul 21 07:13:32 PM PDT 24 18006062652 ps
T780 /workspace/coverage/default/19.sram_ctrl_partial_access.918773720 Jul 21 07:07:33 PM PDT 24 Jul 21 07:07:55 PM PDT 24 2937106560 ps
T781 /workspace/coverage/default/7.sram_ctrl_lc_escalation.1204336821 Jul 21 07:06:59 PM PDT 24 Jul 21 07:08:12 PM PDT 24 23475628766 ps
T782 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2306246964 Jul 21 07:07:24 PM PDT 24 Jul 21 07:08:28 PM PDT 24 18686529760 ps
T783 /workspace/coverage/default/27.sram_ctrl_max_throughput.221864178 Jul 21 07:08:07 PM PDT 24 Jul 21 07:08:25 PM PDT 24 768145349 ps
T784 /workspace/coverage/default/9.sram_ctrl_mem_walk.3556707141 Jul 21 07:07:24 PM PDT 24 Jul 21 07:09:54 PM PDT 24 2772778327 ps
T785 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1201339263 Jul 21 07:08:41 PM PDT 24 Jul 21 07:16:40 PM PDT 24 7874262741 ps
T786 /workspace/coverage/default/37.sram_ctrl_multiple_keys.213735957 Jul 21 07:09:10 PM PDT 24 Jul 21 07:35:41 PM PDT 24 30105430593 ps
T787 /workspace/coverage/default/40.sram_ctrl_regwen.4122453042 Jul 21 07:09:38 PM PDT 24 Jul 21 07:24:08 PM PDT 24 24112859446 ps
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