| T788 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2724559332 |
|
|
Jul 21 07:08:04 PM PDT 24 |
Jul 21 07:08:37 PM PDT 24 |
5310563303 ps |
| T789 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1486584692 |
|
|
Jul 21 07:07:24 PM PDT 24 |
Jul 21 07:07:30 PM PDT 24 |
704881735 ps |
| T790 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.1776144844 |
|
|
Jul 21 07:07:25 PM PDT 24 |
Jul 21 07:31:20 PM PDT 24 |
12150508498 ps |
| T791 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1497213420 |
|
|
Jul 21 07:07:13 PM PDT 24 |
Jul 21 07:07:50 PM PDT 24 |
6635088098 ps |
| T792 |
/workspace/coverage/default/46.sram_ctrl_regwen.2670866944 |
|
|
Jul 21 07:10:30 PM PDT 24 |
Jul 21 07:19:24 PM PDT 24 |
4976443769 ps |
| T793 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3126089363 |
|
|
Jul 21 07:07:04 PM PDT 24 |
Jul 21 07:09:36 PM PDT 24 |
895059939 ps |
| T794 |
/workspace/coverage/default/2.sram_ctrl_partial_access.4237052556 |
|
|
Jul 21 07:07:18 PM PDT 24 |
Jul 21 07:07:41 PM PDT 24 |
3922510585 ps |
| T795 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.2954952486 |
|
|
Jul 21 07:09:20 PM PDT 24 |
Jul 21 07:25:57 PM PDT 24 |
37086039586 ps |
| T796 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.31383688 |
|
|
Jul 21 07:09:05 PM PDT 24 |
Jul 21 07:11:27 PM PDT 24 |
2799705991 ps |
| T797 |
/workspace/coverage/default/38.sram_ctrl_alert_test.3576910571 |
|
|
Jul 21 07:09:21 PM PDT 24 |
Jul 21 07:09:24 PM PDT 24 |
18673047 ps |
| T798 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2907407810 |
|
|
Jul 21 07:09:49 PM PDT 24 |
Jul 21 07:10:03 PM PDT 24 |
1735250773 ps |
| T799 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1038436849 |
|
|
Jul 21 07:10:09 PM PDT 24 |
Jul 21 07:33:38 PM PDT 24 |
9855458838 ps |
| T800 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2610866338 |
|
|
Jul 21 07:08:52 PM PDT 24 |
Jul 21 07:08:59 PM PDT 24 |
3028822913 ps |
| T801 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3625068458 |
|
|
Jul 21 07:07:15 PM PDT 24 |
Jul 21 07:08:45 PM PDT 24 |
1234719356 ps |
| T802 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1102562968 |
|
|
Jul 21 07:10:22 PM PDT 24 |
Jul 21 07:25:31 PM PDT 24 |
9867391953 ps |
| T803 |
/workspace/coverage/default/12.sram_ctrl_bijection.3308128057 |
|
|
Jul 21 07:07:12 PM PDT 24 |
Jul 21 07:18:36 PM PDT 24 |
38081865442 ps |
| T804 |
/workspace/coverage/default/1.sram_ctrl_alert_test.653503506 |
|
|
Jul 21 07:06:43 PM PDT 24 |
Jul 21 07:06:44 PM PDT 24 |
12836143 ps |
| T805 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.904222864 |
|
|
Jul 21 07:10:15 PM PDT 24 |
Jul 21 07:12:13 PM PDT 24 |
780836109 ps |
| T806 |
/workspace/coverage/default/32.sram_ctrl_partial_access.3939025015 |
|
|
Jul 21 07:08:32 PM PDT 24 |
Jul 21 07:08:45 PM PDT 24 |
3105680634 ps |
| T807 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.101916015 |
|
|
Jul 21 07:10:30 PM PDT 24 |
Jul 21 07:15:44 PM PDT 24 |
55421907803 ps |
| T808 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3206572686 |
|
|
Jul 21 07:09:38 PM PDT 24 |
Jul 21 07:09:50 PM PDT 24 |
544531139 ps |
| T809 |
/workspace/coverage/default/47.sram_ctrl_alert_test.4089920977 |
|
|
Jul 21 07:10:39 PM PDT 24 |
Jul 21 07:10:40 PM PDT 24 |
23404340 ps |
| T810 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3785772714 |
|
|
Jul 21 07:10:25 PM PDT 24 |
Jul 21 07:10:26 PM PDT 24 |
30455427 ps |
| T811 |
/workspace/coverage/default/35.sram_ctrl_alert_test.849331117 |
|
|
Jul 21 07:08:57 PM PDT 24 |
Jul 21 07:08:59 PM PDT 24 |
22111198 ps |
| T812 |
/workspace/coverage/default/4.sram_ctrl_stress_all.208802133 |
|
|
Jul 21 07:07:11 PM PDT 24 |
Jul 21 08:11:53 PM PDT 24 |
118228550590 ps |
| T813 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1026810444 |
|
|
Jul 21 07:07:51 PM PDT 24 |
Jul 21 07:13:51 PM PDT 24 |
11733987645 ps |
| T814 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.949646854 |
|
|
Jul 21 07:09:06 PM PDT 24 |
Jul 21 07:13:05 PM PDT 24 |
13930907040 ps |
| T815 |
/workspace/coverage/default/45.sram_ctrl_smoke.3054711018 |
|
|
Jul 21 07:10:19 PM PDT 24 |
Jul 21 07:10:30 PM PDT 24 |
598753002 ps |
| T816 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2783577003 |
|
|
Jul 21 07:10:40 PM PDT 24 |
Jul 21 07:12:00 PM PDT 24 |
10978543495 ps |
| T817 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.4242709640 |
|
|
Jul 21 07:07:38 PM PDT 24 |
Jul 21 07:07:55 PM PDT 24 |
717224384 ps |
| T818 |
/workspace/coverage/default/41.sram_ctrl_alert_test.811679919 |
|
|
Jul 21 07:10:00 PM PDT 24 |
Jul 21 07:10:01 PM PDT 24 |
17295649 ps |
| T819 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.684799113 |
|
|
Jul 21 07:07:24 PM PDT 24 |
Jul 21 07:08:28 PM PDT 24 |
38368485141 ps |
| T820 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.3103066442 |
|
|
Jul 21 07:09:44 PM PDT 24 |
Jul 21 07:27:13 PM PDT 24 |
60093228443 ps |
| T821 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.93129221 |
|
|
Jul 21 07:07:25 PM PDT 24 |
Jul 21 07:09:02 PM PDT 24 |
12779024144 ps |
| T822 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.392364677 |
|
|
Jul 21 07:07:11 PM PDT 24 |
Jul 21 07:08:18 PM PDT 24 |
10683538227 ps |
| T823 |
/workspace/coverage/default/22.sram_ctrl_smoke.1303913254 |
|
|
Jul 21 07:07:37 PM PDT 24 |
Jul 21 07:08:05 PM PDT 24 |
4720253544 ps |
| T824 |
/workspace/coverage/default/10.sram_ctrl_smoke.702616550 |
|
|
Jul 21 07:07:23 PM PDT 24 |
Jul 21 07:07:36 PM PDT 24 |
2907411828 ps |
| T825 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1322418689 |
|
|
Jul 21 07:06:56 PM PDT 24 |
Jul 21 07:12:56 PM PDT 24 |
15799780986 ps |
| T826 |
/workspace/coverage/default/14.sram_ctrl_stress_all.60333640 |
|
|
Jul 21 07:07:31 PM PDT 24 |
Jul 21 09:02:58 PM PDT 24 |
91400813476 ps |
| T827 |
/workspace/coverage/default/39.sram_ctrl_bijection.3124498815 |
|
|
Jul 21 07:09:21 PM PDT 24 |
Jul 21 07:35:13 PM PDT 24 |
82849905877 ps |
| T828 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.255868265 |
|
|
Jul 21 07:07:57 PM PDT 24 |
Jul 21 07:12:16 PM PDT 24 |
4183902717 ps |
| T829 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3417708912 |
|
|
Jul 21 07:07:41 PM PDT 24 |
Jul 21 07:07:49 PM PDT 24 |
711808592 ps |
| T830 |
/workspace/coverage/default/22.sram_ctrl_stress_all.1592937086 |
|
|
Jul 21 07:07:40 PM PDT 24 |
Jul 21 08:20:36 PM PDT 24 |
243470903528 ps |
| T831 |
/workspace/coverage/default/48.sram_ctrl_stress_all.4018781811 |
|
|
Jul 21 07:10:55 PM PDT 24 |
Jul 21 08:05:34 PM PDT 24 |
156542814876 ps |
| T94 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1236226090 |
|
|
Jul 21 07:07:45 PM PDT 24 |
Jul 21 07:09:01 PM PDT 24 |
5539956430 ps |
| T832 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3479613181 |
|
|
Jul 21 07:08:02 PM PDT 24 |
Jul 21 07:08:06 PM PDT 24 |
695166733 ps |
| T833 |
/workspace/coverage/default/20.sram_ctrl_bijection.3726784780 |
|
|
Jul 21 07:07:35 PM PDT 24 |
Jul 21 07:39:53 PM PDT 24 |
315560088451 ps |
| T834 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.973427621 |
|
|
Jul 21 07:09:11 PM PDT 24 |
Jul 21 07:14:17 PM PDT 24 |
10939659405 ps |
| T835 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.998861201 |
|
|
Jul 21 07:09:28 PM PDT 24 |
Jul 21 07:10:08 PM PDT 24 |
838796013 ps |
| T836 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3250928636 |
|
|
Jul 21 07:06:55 PM PDT 24 |
Jul 21 07:07:20 PM PDT 24 |
4298488157 ps |
| T837 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.3668735019 |
|
|
Jul 21 07:07:24 PM PDT 24 |
Jul 21 07:24:03 PM PDT 24 |
227369356087 ps |
| T838 |
/workspace/coverage/default/40.sram_ctrl_partial_access.1456987020 |
|
|
Jul 21 07:09:41 PM PDT 24 |
Jul 21 07:09:53 PM PDT 24 |
735290752 ps |
| T839 |
/workspace/coverage/default/12.sram_ctrl_smoke.1641373263 |
|
|
Jul 21 07:07:25 PM PDT 24 |
Jul 21 07:08:35 PM PDT 24 |
1037807123 ps |
| T840 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.224659803 |
|
|
Jul 21 07:08:47 PM PDT 24 |
Jul 21 07:29:48 PM PDT 24 |
49685467078 ps |
| T841 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.4008647953 |
|
|
Jul 21 07:07:44 PM PDT 24 |
Jul 21 07:10:12 PM PDT 24 |
4995706895 ps |
| T842 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3142093891 |
|
|
Jul 21 07:07:48 PM PDT 24 |
Jul 21 07:08:29 PM PDT 24 |
766934974 ps |
| T843 |
/workspace/coverage/default/8.sram_ctrl_bijection.1701265581 |
|
|
Jul 21 07:07:13 PM PDT 24 |
Jul 21 07:41:06 PM PDT 24 |
116107054086 ps |
| T844 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3901354127 |
|
|
Jul 21 07:07:53 PM PDT 24 |
Jul 21 07:07:54 PM PDT 24 |
22380835 ps |
| T845 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.4073278144 |
|
|
Jul 21 07:08:31 PM PDT 24 |
Jul 21 07:08:45 PM PDT 24 |
711767137 ps |
| T846 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2332351502 |
|
|
Jul 21 07:07:02 PM PDT 24 |
Jul 21 07:14:44 PM PDT 24 |
30613897575 ps |
| T847 |
/workspace/coverage/default/36.sram_ctrl_alert_test.2734667562 |
|
|
Jul 21 07:09:06 PM PDT 24 |
Jul 21 07:09:08 PM PDT 24 |
32539699 ps |
| T848 |
/workspace/coverage/default/17.sram_ctrl_bijection.1010149055 |
|
|
Jul 21 07:07:24 PM PDT 24 |
Jul 21 07:30:47 PM PDT 24 |
124980502160 ps |
| T849 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.3536200669 |
|
|
Jul 21 07:07:43 PM PDT 24 |
Jul 21 07:08:57 PM PDT 24 |
1395488629 ps |
| T850 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1547339869 |
|
|
Jul 21 07:07:33 PM PDT 24 |
Jul 21 07:57:53 PM PDT 24 |
90614832110 ps |
| T851 |
/workspace/coverage/default/15.sram_ctrl_regwen.2125392599 |
|
|
Jul 21 07:07:18 PM PDT 24 |
Jul 21 07:29:57 PM PDT 24 |
5665319941 ps |
| T852 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2593843255 |
|
|
Jul 21 07:07:25 PM PDT 24 |
Jul 21 07:07:54 PM PDT 24 |
754523537 ps |
| T853 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2166766356 |
|
|
Jul 21 07:06:40 PM PDT 24 |
Jul 21 07:09:41 PM PDT 24 |
9592746031 ps |
| T854 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.291424051 |
|
|
Jul 21 07:10:19 PM PDT 24 |
Jul 21 07:10:28 PM PDT 24 |
515725382 ps |
| T855 |
/workspace/coverage/default/3.sram_ctrl_regwen.1484004477 |
|
|
Jul 21 07:06:53 PM PDT 24 |
Jul 21 07:17:17 PM PDT 24 |
3537837782 ps |
| T856 |
/workspace/coverage/default/18.sram_ctrl_regwen.2696375561 |
|
|
Jul 21 07:07:32 PM PDT 24 |
Jul 21 07:08:35 PM PDT 24 |
1995552595 ps |
| T857 |
/workspace/coverage/default/9.sram_ctrl_smoke.289791936 |
|
|
Jul 21 07:07:20 PM PDT 24 |
Jul 21 07:07:36 PM PDT 24 |
3018147914 ps |
| T858 |
/workspace/coverage/default/13.sram_ctrl_bijection.1188505907 |
|
|
Jul 21 07:07:29 PM PDT 24 |
Jul 21 07:26:58 PM PDT 24 |
64296092519 ps |
| T859 |
/workspace/coverage/default/20.sram_ctrl_regwen.3698115235 |
|
|
Jul 21 07:07:24 PM PDT 24 |
Jul 21 07:15:00 PM PDT 24 |
2442096962 ps |
| T860 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1650082610 |
|
|
Jul 21 07:07:41 PM PDT 24 |
Jul 21 08:47:27 PM PDT 24 |
95585005858 ps |
| T861 |
/workspace/coverage/default/7.sram_ctrl_stress_all.853588779 |
|
|
Jul 21 07:07:15 PM PDT 24 |
Jul 21 07:52:57 PM PDT 24 |
132535787946 ps |
| T862 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.901152808 |
|
|
Jul 21 07:08:30 PM PDT 24 |
Jul 21 07:14:05 PM PDT 24 |
5577734997 ps |
| T863 |
/workspace/coverage/default/18.sram_ctrl_executable.1895885628 |
|
|
Jul 21 07:07:36 PM PDT 24 |
Jul 21 07:16:29 PM PDT 24 |
23766462763 ps |
| T864 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.741950398 |
|
|
Jul 21 07:09:34 PM PDT 24 |
Jul 21 07:29:25 PM PDT 24 |
125727214531 ps |
| T865 |
/workspace/coverage/default/43.sram_ctrl_regwen.1094801029 |
|
|
Jul 21 07:10:07 PM PDT 24 |
Jul 21 07:24:05 PM PDT 24 |
95713446528 ps |
| T866 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2600400755 |
|
|
Jul 21 07:07:59 PM PDT 24 |
Jul 21 07:22:56 PM PDT 24 |
9305032699 ps |
| T867 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2735907600 |
|
|
Jul 21 07:08:58 PM PDT 24 |
Jul 21 07:11:33 PM PDT 24 |
5273285903 ps |
| T868 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1419642979 |
|
|
Jul 21 07:06:43 PM PDT 24 |
Jul 21 07:08:28 PM PDT 24 |
16093370962 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.753568937 |
|
|
Jul 21 07:10:48 PM PDT 24 |
Jul 21 07:11:08 PM PDT 24 |
10796119095 ps |
| T870 |
/workspace/coverage/default/17.sram_ctrl_smoke.1889094961 |
|
|
Jul 21 07:07:29 PM PDT 24 |
Jul 21 07:07:50 PM PDT 24 |
1255482491 ps |
| T871 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2426715830 |
|
|
Jul 21 07:07:50 PM PDT 24 |
Jul 21 07:08:42 PM PDT 24 |
772204340 ps |
| T872 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.509269017 |
|
|
Jul 21 07:09:15 PM PDT 24 |
Jul 21 07:21:29 PM PDT 24 |
15786019186 ps |
| T873 |
/workspace/coverage/default/23.sram_ctrl_smoke.1838460902 |
|
|
Jul 21 07:07:51 PM PDT 24 |
Jul 21 07:08:01 PM PDT 24 |
1431320326 ps |
| T874 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.297334916 |
|
|
Jul 21 07:07:17 PM PDT 24 |
Jul 21 07:19:05 PM PDT 24 |
58207281176 ps |
| T875 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2837452977 |
|
|
Jul 21 07:07:18 PM PDT 24 |
Jul 21 07:12:40 PM PDT 24 |
14122170839 ps |
| T876 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2902478232 |
|
|
Jul 21 07:07:25 PM PDT 24 |
Jul 21 07:08:17 PM PDT 24 |
1504397468 ps |
| T877 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1193554721 |
|
|
Jul 21 07:10:14 PM PDT 24 |
Jul 21 07:14:40 PM PDT 24 |
4108903323 ps |
| T878 |
/workspace/coverage/default/45.sram_ctrl_bijection.1033311011 |
|
|
Jul 21 07:10:19 PM PDT 24 |
Jul 21 07:26:01 PM PDT 24 |
13889997588 ps |
| T879 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.4186859180 |
|
|
Jul 21 07:06:51 PM PDT 24 |
Jul 21 07:30:31 PM PDT 24 |
23909187227 ps |
| T880 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.927697342 |
|
|
Jul 21 07:08:58 PM PDT 24 |
Jul 21 07:11:12 PM PDT 24 |
83092154528 ps |
| T881 |
/workspace/coverage/default/33.sram_ctrl_executable.4062551174 |
|
|
Jul 21 07:08:42 PM PDT 24 |
Jul 21 07:26:38 PM PDT 24 |
20775270591 ps |
| T882 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3582903136 |
|
|
Jul 21 07:07:54 PM PDT 24 |
Jul 21 07:16:02 PM PDT 24 |
43163304409 ps |
| T883 |
/workspace/coverage/default/34.sram_ctrl_executable.778195132 |
|
|
Jul 21 07:08:47 PM PDT 24 |
Jul 21 07:23:23 PM PDT 24 |
33704407764 ps |
| T884 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2347443476 |
|
|
Jul 21 07:07:08 PM PDT 24 |
Jul 21 07:08:14 PM PDT 24 |
780840348 ps |
| T885 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1855702036 |
|
|
Jul 21 07:08:17 PM PDT 24 |
Jul 21 07:08:34 PM PDT 24 |
845701052 ps |
| T886 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2013975886 |
|
|
Jul 21 07:09:38 PM PDT 24 |
Jul 21 07:09:39 PM PDT 24 |
33425520 ps |
| T887 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1635088165 |
|
|
Jul 21 07:08:58 PM PDT 24 |
Jul 21 07:10:20 PM PDT 24 |
19888952083 ps |
| T888 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2322966321 |
|
|
Jul 21 07:08:25 PM PDT 24 |
Jul 21 07:09:29 PM PDT 24 |
1878284200 ps |
| T889 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1133685244 |
|
|
Jul 21 07:07:13 PM PDT 24 |
Jul 21 07:07:40 PM PDT 24 |
1914304332 ps |
| T890 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.43797982 |
|
|
Jul 21 07:10:15 PM PDT 24 |
Jul 21 07:10:19 PM PDT 24 |
735141544 ps |
| T891 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1067079423 |
|
|
Jul 21 07:07:34 PM PDT 24 |
Jul 21 07:15:47 PM PDT 24 |
30578542707 ps |
| T892 |
/workspace/coverage/default/31.sram_ctrl_regwen.1278575543 |
|
|
Jul 21 07:08:32 PM PDT 24 |
Jul 21 07:36:33 PM PDT 24 |
71929684927 ps |
| T893 |
/workspace/coverage/default/29.sram_ctrl_smoke.2048079960 |
|
|
Jul 21 07:08:16 PM PDT 24 |
Jul 21 07:09:53 PM PDT 24 |
957101764 ps |
| T894 |
/workspace/coverage/default/25.sram_ctrl_partial_access.437491753 |
|
|
Jul 21 07:08:04 PM PDT 24 |
Jul 21 07:08:13 PM PDT 24 |
1811000703 ps |
| T895 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1227941213 |
|
|
Jul 21 07:08:17 PM PDT 24 |
Jul 21 07:13:29 PM PDT 24 |
55329970185 ps |
| T896 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2183913988 |
|
|
Jul 21 07:07:01 PM PDT 24 |
Jul 21 07:08:08 PM PDT 24 |
1084833142 ps |
| T897 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2000980967 |
|
|
Jul 21 07:07:04 PM PDT 24 |
Jul 21 07:08:03 PM PDT 24 |
2932333185 ps |
| T898 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1204153026 |
|
|
Jul 21 07:07:20 PM PDT 24 |
Jul 21 07:12:18 PM PDT 24 |
4879069256 ps |
| T899 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1144543733 |
|
|
Jul 21 07:07:24 PM PDT 24 |
Jul 21 07:08:21 PM PDT 24 |
1343010753 ps |
| T900 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1722249037 |
|
|
Jul 21 07:07:38 PM PDT 24 |
Jul 21 07:08:10 PM PDT 24 |
2244707718 ps |
| T901 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.839558222 |
|
|
Jul 21 07:07:07 PM PDT 24 |
Jul 21 07:22:01 PM PDT 24 |
13845075593 ps |
| T902 |
/workspace/coverage/default/48.sram_ctrl_alert_test.2057398541 |
|
|
Jul 21 07:10:55 PM PDT 24 |
Jul 21 07:10:56 PM PDT 24 |
26449900 ps |
| T903 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.92502969 |
|
|
Jul 21 07:07:28 PM PDT 24 |
Jul 21 07:07:53 PM PDT 24 |
1390475865 ps |
| T904 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.1293236982 |
|
|
Jul 21 07:07:48 PM PDT 24 |
Jul 21 07:10:42 PM PDT 24 |
1868283051 ps |
| T905 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.4195321117 |
|
|
Jul 21 07:09:51 PM PDT 24 |
Jul 21 07:10:05 PM PDT 24 |
803064047 ps |
| T906 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1673594017 |
|
|
Jul 21 07:07:45 PM PDT 24 |
Jul 21 07:10:09 PM PDT 24 |
4153692597 ps |
| T907 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.130871820 |
|
|
Jul 21 07:09:20 PM PDT 24 |
Jul 21 07:14:22 PM PDT 24 |
19809641843 ps |
| T908 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2469051031 |
|
|
Jul 21 07:07:03 PM PDT 24 |
Jul 21 07:10:59 PM PDT 24 |
3679351080 ps |
| T909 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.892494957 |
|
|
Jul 21 07:08:58 PM PDT 24 |
Jul 21 07:09:06 PM PDT 24 |
2788335694 ps |
| T910 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1127906890 |
|
|
Jul 21 07:07:49 PM PDT 24 |
Jul 21 07:07:50 PM PDT 24 |
11857304 ps |
| T911 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2062086685 |
|
|
Jul 21 07:08:01 PM PDT 24 |
Jul 21 07:12:56 PM PDT 24 |
4953768294 ps |
| T912 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2789309108 |
|
|
Jul 21 07:08:42 PM PDT 24 |
Jul 21 07:10:27 PM PDT 24 |
11905343283 ps |
| T913 |
/workspace/coverage/default/7.sram_ctrl_regwen.2229352113 |
|
|
Jul 21 07:07:28 PM PDT 24 |
Jul 21 07:10:57 PM PDT 24 |
5588445448 ps |
| T914 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.834204933 |
|
|
Jul 21 07:10:08 PM PDT 24 |
Jul 21 07:18:34 PM PDT 24 |
8313215007 ps |
| T915 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1199226961 |
|
|
Jul 21 07:08:31 PM PDT 24 |
Jul 21 08:20:39 PM PDT 24 |
44736536311 ps |
| T916 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.920760786 |
|
|
Jul 21 07:08:47 PM PDT 24 |
Jul 21 07:25:57 PM PDT 24 |
62587490044 ps |
| T917 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2375631783 |
|
|
Jul 21 07:07:23 PM PDT 24 |
Jul 21 07:08:44 PM PDT 24 |
808878937 ps |
| T918 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1828435002 |
|
|
Jul 21 07:07:02 PM PDT 24 |
Jul 21 07:13:56 PM PDT 24 |
5944428550 ps |
| T919 |
/workspace/coverage/default/4.sram_ctrl_bijection.3770764599 |
|
|
Jul 21 07:07:12 PM PDT 24 |
Jul 21 07:43:47 PM PDT 24 |
116768968907 ps |
| T920 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.939262191 |
|
|
Jul 21 07:08:09 PM PDT 24 |
Jul 21 07:13:49 PM PDT 24 |
95266210339 ps |
| T921 |
/workspace/coverage/default/37.sram_ctrl_regwen.2362997318 |
|
|
Jul 21 07:09:11 PM PDT 24 |
Jul 21 07:31:11 PM PDT 24 |
17602026121 ps |
| T922 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1068364760 |
|
|
Jul 21 07:07:26 PM PDT 24 |
Jul 21 08:59:13 PM PDT 24 |
121344444424 ps |
| T923 |
/workspace/coverage/default/40.sram_ctrl_bijection.1761736488 |
|
|
Jul 21 07:09:42 PM PDT 24 |
Jul 21 07:28:01 PM PDT 24 |
216118478628 ps |
| T924 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.897038291 |
|
|
Jul 21 07:08:31 PM PDT 24 |
Jul 21 07:08:35 PM PDT 24 |
691769756 ps |
| T925 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.105980586 |
|
|
Jul 21 07:08:52 PM PDT 24 |
Jul 21 07:17:30 PM PDT 24 |
47202817513 ps |
| T926 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3899093157 |
|
|
Jul 21 07:07:29 PM PDT 24 |
Jul 21 07:10:44 PM PDT 24 |
1158828376 ps |
| T927 |
/workspace/coverage/default/23.sram_ctrl_regwen.2052614995 |
|
|
Jul 21 07:07:52 PM PDT 24 |
Jul 21 07:16:02 PM PDT 24 |
6001206142 ps |
| T928 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3847186264 |
|
|
Jul 21 07:07:08 PM PDT 24 |
Jul 21 07:11:05 PM PDT 24 |
3294925980 ps |
| T929 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2150643140 |
|
|
Jul 21 07:07:16 PM PDT 24 |
Jul 21 07:09:30 PM PDT 24 |
1111116053 ps |
| T930 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2601987737 |
|
|
Jul 21 07:09:20 PM PDT 24 |
Jul 21 07:09:29 PM PDT 24 |
581837115 ps |
| T931 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.510503814 |
|
|
Jul 21 07:06:44 PM PDT 24 |
Jul 21 07:06:48 PM PDT 24 |
1861392497 ps |
| T932 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3061781946 |
|
|
Jul 21 07:08:08 PM PDT 24 |
Jul 21 07:08:09 PM PDT 24 |
14170739 ps |
| T933 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1828224661 |
|
|
Jul 21 07:07:27 PM PDT 24 |
Jul 21 07:10:24 PM PDT 24 |
5232204708 ps |
| T67 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.418866312 |
|
|
Jul 21 06:40:15 PM PDT 24 |
Jul 21 06:41:15 PM PDT 24 |
64151396973 ps |
| T68 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2330949025 |
|
|
Jul 21 06:40:20 PM PDT 24 |
Jul 21 06:40:22 PM PDT 24 |
30951359 ps |
| T934 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.444755148 |
|
|
Jul 21 06:40:11 PM PDT 24 |
Jul 21 06:40:15 PM PDT 24 |
389129971 ps |
| T69 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.922368460 |
|
|
Jul 21 06:40:30 PM PDT 24 |
Jul 21 06:40:57 PM PDT 24 |
3695665737 ps |
| T76 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2728884557 |
|
|
Jul 21 06:40:16 PM PDT 24 |
Jul 21 06:40:18 PM PDT 24 |
102488142 ps |
| T935 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1003958462 |
|
|
Jul 21 06:40:26 PM PDT 24 |
Jul 21 06:40:30 PM PDT 24 |
373914896 ps |
| T100 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.783497574 |
|
|
Jul 21 06:40:26 PM PDT 24 |
Jul 21 06:40:28 PM PDT 24 |
17132639 ps |
| T120 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.97154031 |
|
|
Jul 21 06:40:13 PM PDT 24 |
Jul 21 06:40:16 PM PDT 24 |
339807168 ps |
| T101 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.394494545 |
|
|
Jul 21 06:40:26 PM PDT 24 |
Jul 21 06:40:27 PM PDT 24 |
181741165 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3491978395 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:40:29 PM PDT 24 |
43671959 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.165181222 |
|
|
Jul 21 06:40:12 PM PDT 24 |
Jul 21 06:40:14 PM PDT 24 |
80152922 ps |
| T936 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1159394624 |
|
|
Jul 21 06:40:20 PM PDT 24 |
Jul 21 06:40:24 PM PDT 24 |
351233084 ps |
| T64 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4102663786 |
|
|
Jul 21 06:40:10 PM PDT 24 |
Jul 21 06:40:13 PM PDT 24 |
602673788 ps |
| T937 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3162568245 |
|
|
Jul 21 06:40:18 PM PDT 24 |
Jul 21 06:40:21 PM PDT 24 |
513399903 ps |
| T122 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2505420298 |
|
|
Jul 21 06:40:17 PM PDT 24 |
Jul 21 06:40:18 PM PDT 24 |
113567264 ps |
| T938 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3504452524 |
|
|
Jul 21 06:40:10 PM PDT 24 |
Jul 21 06:40:12 PM PDT 24 |
14537500 ps |
| T939 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3823043023 |
|
|
Jul 21 06:40:28 PM PDT 24 |
Jul 21 06:40:32 PM PDT 24 |
717458406 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2109372468 |
|
|
Jul 21 06:40:21 PM PDT 24 |
Jul 21 06:40:23 PM PDT 24 |
103093990 ps |
| T940 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3991418576 |
|
|
Jul 21 06:40:36 PM PDT 24 |
Jul 21 06:40:37 PM PDT 24 |
13136968 ps |
| T65 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3620951240 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:25 PM PDT 24 |
406926670 ps |
| T66 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1363399629 |
|
|
Jul 21 06:40:20 PM PDT 24 |
Jul 21 06:40:23 PM PDT 24 |
653794643 ps |
| T941 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2836707501 |
|
|
Jul 21 06:40:16 PM PDT 24 |
Jul 21 06:40:17 PM PDT 24 |
17348407 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3368758680 |
|
|
Jul 21 06:40:13 PM PDT 24 |
Jul 21 06:40:15 PM PDT 24 |
69624422 ps |
| T78 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3528880160 |
|
|
Jul 21 06:40:26 PM PDT 24 |
Jul 21 06:40:27 PM PDT 24 |
22609720 ps |
| T942 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3770689815 |
|
|
Jul 21 06:40:24 PM PDT 24 |
Jul 21 06:40:27 PM PDT 24 |
365994459 ps |
| T943 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2345223256 |
|
|
Jul 21 06:40:36 PM PDT 24 |
Jul 21 06:40:38 PM PDT 24 |
107848509 ps |
| T79 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.432754830 |
|
|
Jul 21 06:40:20 PM PDT 24 |
Jul 21 06:41:13 PM PDT 24 |
7230227872 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3465639487 |
|
|
Jul 21 06:40:16 PM PDT 24 |
Jul 21 06:40:20 PM PDT 24 |
701750243 ps |
| T945 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4120983985 |
|
|
Jul 21 06:40:34 PM PDT 24 |
Jul 21 06:40:35 PM PDT 24 |
14724670 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.334687575 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:40:33 PM PDT 24 |
732421184 ps |
| T947 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1454535948 |
|
|
Jul 21 06:40:20 PM PDT 24 |
Jul 21 06:40:25 PM PDT 24 |
520545990 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1041769320 |
|
|
Jul 21 06:40:17 PM PDT 24 |
Jul 21 06:40:21 PM PDT 24 |
365396003 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2273254672 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:55 PM PDT 24 |
19398289581 ps |
| T81 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.4062476172 |
|
|
Jul 21 06:40:21 PM PDT 24 |
Jul 21 06:41:15 PM PDT 24 |
14357156380 ps |
| T949 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3456515816 |
|
|
Jul 21 06:40:26 PM PDT 24 |
Jul 21 06:40:29 PM PDT 24 |
84831192 ps |
| T82 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3709097976 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:41:31 PM PDT 24 |
29351582490 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1279135400 |
|
|
Jul 21 06:40:20 PM PDT 24 |
Jul 21 06:40:23 PM PDT 24 |
49862735 ps |
| T83 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3098502450 |
|
|
Jul 21 06:40:38 PM PDT 24 |
Jul 21 06:41:10 PM PDT 24 |
16745535864 ps |
| T138 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3311919720 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:40:30 PM PDT 24 |
244608974 ps |
| T84 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3825952394 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:24 PM PDT 24 |
16096397 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3024271762 |
|
|
Jul 21 06:40:33 PM PDT 24 |
Jul 21 06:40:37 PM PDT 24 |
717864234 ps |
| T952 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.191726752 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:28 PM PDT 24 |
700738989 ps |
| T85 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.818471583 |
|
|
Jul 21 06:40:33 PM PDT 24 |
Jul 21 06:41:26 PM PDT 24 |
7056079579 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3503806988 |
|
|
Jul 21 06:40:31 PM PDT 24 |
Jul 21 06:40:33 PM PDT 24 |
57667760 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2566592092 |
|
|
Jul 21 06:40:13 PM PDT 24 |
Jul 21 06:40:14 PM PDT 24 |
17100929 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.33696551 |
|
|
Jul 21 06:40:32 PM PDT 24 |
Jul 21 06:41:22 PM PDT 24 |
7131585252 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1478065037 |
|
|
Jul 21 06:40:28 PM PDT 24 |
Jul 21 06:40:57 PM PDT 24 |
7538846087 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.446357113 |
|
|
Jul 21 06:40:21 PM PDT 24 |
Jul 21 06:40:23 PM PDT 24 |
264257202 ps |
| T956 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4214164417 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:26 PM PDT 24 |
86027722 ps |
| T957 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1411122134 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:24 PM PDT 24 |
41088238 ps |
| T137 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2058219633 |
|
|
Jul 21 06:40:33 PM PDT 24 |
Jul 21 06:40:36 PM PDT 24 |
335241754 ps |
| T96 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.159185711 |
|
|
Jul 21 06:40:28 PM PDT 24 |
Jul 21 06:40:58 PM PDT 24 |
15419260092 ps |
| T958 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1009467507 |
|
|
Jul 21 06:40:32 PM PDT 24 |
Jul 21 06:40:33 PM PDT 24 |
53667025 ps |
| T959 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2113672320 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:40:32 PM PDT 24 |
1369367475 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3636044080 |
|
|
Jul 21 06:40:32 PM PDT 24 |
Jul 21 06:40:37 PM PDT 24 |
206708856 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4167098068 |
|
|
Jul 21 06:40:14 PM PDT 24 |
Jul 21 06:40:18 PM PDT 24 |
2308426728 ps |
| T962 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1092962456 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:40:29 PM PDT 24 |
12696448 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.411661624 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:23 PM PDT 24 |
67949951 ps |
| T964 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.752733019 |
|
|
Jul 21 06:40:36 PM PDT 24 |
Jul 21 06:40:40 PM PDT 24 |
72229828 ps |
| T97 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1280949553 |
|
|
Jul 21 06:40:11 PM PDT 24 |
Jul 21 06:40:39 PM PDT 24 |
9757764593 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2088441930 |
|
|
Jul 21 06:40:33 PM PDT 24 |
Jul 21 06:41:10 PM PDT 24 |
26432123508 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1415309051 |
|
|
Jul 21 06:40:24 PM PDT 24 |
Jul 21 06:40:29 PM PDT 24 |
4396794493 ps |
| T967 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1301457618 |
|
|
Jul 21 06:40:11 PM PDT 24 |
Jul 21 06:40:12 PM PDT 24 |
39357973 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.745807915 |
|
|
Jul 21 06:40:36 PM PDT 24 |
Jul 21 06:40:40 PM PDT 24 |
71291731 ps |
| T131 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3470057673 |
|
|
Jul 21 06:40:16 PM PDT 24 |
Jul 21 06:40:19 PM PDT 24 |
454893802 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2998183626 |
|
|
Jul 21 06:40:12 PM PDT 24 |
Jul 21 06:40:14 PM PDT 24 |
62705287 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3636153159 |
|
|
Jul 21 06:40:19 PM PDT 24 |
Jul 21 06:40:20 PM PDT 24 |
68247650 ps |
| T971 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3504536583 |
|
|
Jul 21 06:40:32 PM PDT 24 |
Jul 21 06:40:36 PM PDT 24 |
350741055 ps |
| T972 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3865836523 |
|
|
Jul 21 06:40:16 PM PDT 24 |
Jul 21 06:40:17 PM PDT 24 |
16875469 ps |
| T973 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2177061933 |
|
|
Jul 21 06:40:23 PM PDT 24 |
Jul 21 06:40:28 PM PDT 24 |
362262050 ps |
| T974 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.301322344 |
|
|
Jul 21 06:40:29 PM PDT 24 |
Jul 21 06:40:30 PM PDT 24 |
25576632 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3909717888 |
|
|
Jul 21 06:40:18 PM PDT 24 |
Jul 21 06:40:44 PM PDT 24 |
3878846517 ps |
| T133 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3214557502 |
|
|
Jul 21 06:40:28 PM PDT 24 |
Jul 21 06:40:31 PM PDT 24 |
1035469693 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1635995021 |
|
|
Jul 21 06:40:20 PM PDT 24 |
Jul 21 06:40:21 PM PDT 24 |
47836662 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3101262974 |
|
|
Jul 21 06:40:23 PM PDT 24 |
Jul 21 06:40:27 PM PDT 24 |
373402230 ps |
| T978 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1830165311 |
|
|
Jul 21 06:40:36 PM PDT 24 |
Jul 21 06:40:39 PM PDT 24 |
554009354 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.32142952 |
|
|
Jul 21 06:40:18 PM PDT 24 |
Jul 21 06:40:20 PM PDT 24 |
19075004 ps |
| T980 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1469114101 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:26 PM PDT 24 |
41257236 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1578475476 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:40:33 PM PDT 24 |
544802199 ps |
| T135 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1003359359 |
|
|
Jul 21 06:40:10 PM PDT 24 |
Jul 21 06:40:13 PM PDT 24 |
835416624 ps |
| T982 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1658320773 |
|
|
Jul 21 06:40:35 PM PDT 24 |
Jul 21 06:40:40 PM PDT 24 |
363153472 ps |
| T983 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3588626173 |
|
|
Jul 21 06:40:21 PM PDT 24 |
Jul 21 06:40:24 PM PDT 24 |
100789348 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.268542929 |
|
|
Jul 21 06:40:10 PM PDT 24 |
Jul 21 06:40:13 PM PDT 24 |
21035368 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.32219715 |
|
|
Jul 21 06:40:15 PM PDT 24 |
Jul 21 06:41:11 PM PDT 24 |
54186790492 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2933579011 |
|
|
Jul 21 06:40:10 PM PDT 24 |
Jul 21 06:40:11 PM PDT 24 |
26991938 ps |
| T987 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.16198981 |
|
|
Jul 21 06:40:32 PM PDT 24 |
Jul 21 06:40:33 PM PDT 24 |
59813339 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1306669906 |
|
|
Jul 21 06:40:18 PM PDT 24 |
Jul 21 06:40:20 PM PDT 24 |
21461761 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2324991156 |
|
|
Jul 21 06:40:32 PM PDT 24 |
Jul 21 06:40:36 PM PDT 24 |
1171941479 ps |
| T134 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3331199233 |
|
|
Jul 21 06:40:10 PM PDT 24 |
Jul 21 06:40:13 PM PDT 24 |
185960757 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1989971734 |
|
|
Jul 21 06:40:18 PM PDT 24 |
Jul 21 06:40:19 PM PDT 24 |
85122166 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.351076928 |
|
|
Jul 21 06:40:37 PM PDT 24 |
Jul 21 06:40:39 PM PDT 24 |
134573556 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3803245001 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:40:31 PM PDT 24 |
352054556 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2546068757 |
|
|
Jul 21 06:40:13 PM PDT 24 |
Jul 21 06:40:15 PM PDT 24 |
23633543 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1547823669 |
|
|
Jul 21 06:40:13 PM PDT 24 |
Jul 21 06:40:17 PM PDT 24 |
594776366 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2138877535 |
|
|
Jul 21 06:40:22 PM PDT 24 |
Jul 21 06:40:24 PM PDT 24 |
31956709 ps |
| T996 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.204714134 |
|
|
Jul 21 06:40:16 PM PDT 24 |
Jul 21 06:40:18 PM PDT 24 |
33709388 ps |
| T139 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2524110524 |
|
|
Jul 21 06:40:27 PM PDT 24 |
Jul 21 06:40:30 PM PDT 24 |
341605004 ps |
| T997 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1666028977 |
|
|
Jul 21 06:40:19 PM PDT 24 |
Jul 21 06:40:20 PM PDT 24 |
134881298 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2339631404 |
|
|
Jul 21 06:40:19 PM PDT 24 |
Jul 21 06:40:20 PM PDT 24 |
14513932 ps |
| T999 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2644775428 |
|
|
Jul 21 06:40:34 PM PDT 24 |
Jul 21 06:40:35 PM PDT 24 |
80372278 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3513620225 |
|
|
Jul 21 06:40:13 PM PDT 24 |
Jul 21 06:40:46 PM PDT 24 |
26428290724 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3919353108 |
|
|
Jul 21 06:40:09 PM PDT 24 |
Jul 21 06:40:12 PM PDT 24 |
154209100 ps |
| T1002 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4136661741 |
|
|
Jul 21 06:40:26 PM PDT 24 |
Jul 21 06:41:24 PM PDT 24 |
29365887990 ps |