Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	346744206	1			T1	567212		T2	361030		T3	252
instr_valid_dis	309302426	1			T1	567212		T2	129098		T3	252
instr_en	21969716	1			T2	99068		T6	211590		T22	211876

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	14540070	1			T2	76164		T4	142454		T6	171560
sram_ifetch_valid_disable	304077088	1			T1	567212		T2	229522		T3	252
sram_ifetch_enable	28127048	1			T2	55344		T4	175248		T6	202593

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	346744206	1			T1	567212		T2	361030		T3	252
hw_debug_en_valid_off	303242808	1			T1	567212		T2	78864		T3	252
hw_debug_en_on	29815100	1			T2	187580		T4	123052		T6	207332

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	304077088	1			T1	567212		T2	229522		T3	252
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	288878072	1			T1	567212		T2	46624		T3	252
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9771352	1			T2	77152		T6	103434		T22	36928
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4344558	1			T2	17280		T4	58374		T6	93594
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1735788	1			T2	6040		T6	47996		T7	52644
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1533880	1			T6	45598		T22	19858		T23	33024
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7061808	1			T2	45398		T4	33354		T6	77966
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	4900124	1			T2	25884		T6	67320		T23	26182
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1503486	1			T2	19514		T6	10646		T22	51714
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11520732	1			T2	89240		T4	19220		T6	34036
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3333980	1			T6	20748		T7	30456		T21	44912
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5673576	1			T2	53644		T6	12076		T22	15672

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8626644	1			T2	2402		T6	51912		T22	103376
lc_exec_en	11232560	1			T2	52942		T4	70478		T6	196132
valid_exec_dis	299223060	1			T1	567212		T2	96246		T3	252
invalid_exec_dis	42667118	1			T2	131508		T4	317702		T6	219749