Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	143310156	1			T1	257784		T2	78369		T3	126
triple_byte_access	2852247	1			T1	5196		T2	1565		T4	1859
halfword_access	4365741	1			T1	7725		T2	2291		T4	2764
byte_access	6073412	1			T1	10292		T2	3149		T4	3674
zero_access	1811388	1			T1	2609		T2	831		T4	902

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78958103

1

T1

141653

T2

49941

T3

74

auto[1]

79454841

1

T1

141953

T2

36264

T3

52

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	71271425	1			T1	128793		T2	45453		T3	74
auto[0]	triple_byte_access	1368986	1			T1	2627		T2	926		T4	951
auto[0]	halfword_access	2140096	1			T1	3824		T2	1293		T4	1491
auto[0]	byte_access	3108704	1			T1	5142		T2	1794		T4	1923
auto[0]	zero_access	1068892	1			T1	1267		T2	475		T4	454
auto[1]	word_access	72038731	1			T1	128991		T2	32916		T3	52
auto[1]	triple_byte_access	1483261	1			T1	2569		T2	639		T4	908
auto[1]	halfword_access	2225645	1			T1	3901		T2	998		T4	1273
auto[1]	byte_access	2964708	1			T1	5150		T2	1355		T4	1751
auto[1]	zero_access	742496	1			T1	1342		T2	356		T4	448