| T800 |
/workspace/coverage/default/48.sram_ctrl_bijection.2477307652 |
|
|
Jul 22 07:39:54 PM PDT 24 |
Jul 22 07:53:04 PM PDT 24 |
49553704928 ps |
| T801 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2037790626 |
|
|
Jul 22 07:32:03 PM PDT 24 |
Jul 22 07:32:34 PM PDT 24 |
1714555371 ps |
| T802 |
/workspace/coverage/default/45.sram_ctrl_regwen.2499378051 |
|
|
Jul 22 07:39:18 PM PDT 24 |
Jul 22 07:59:03 PM PDT 24 |
60696219023 ps |
| T803 |
/workspace/coverage/default/38.sram_ctrl_executable.356345006 |
|
|
Jul 22 07:37:37 PM PDT 24 |
Jul 22 07:54:10 PM PDT 24 |
21873342646 ps |
| T804 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2006343315 |
|
|
Jul 22 07:40:30 PM PDT 24 |
Jul 22 09:46:31 PM PDT 24 |
670369587034 ps |
| T805 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2421449174 |
|
|
Jul 22 07:38:44 PM PDT 24 |
Jul 22 07:44:45 PM PDT 24 |
10238118218 ps |
| T806 |
/workspace/coverage/default/6.sram_ctrl_partial_access.98202120 |
|
|
Jul 22 07:32:09 PM PDT 24 |
Jul 22 07:33:22 PM PDT 24 |
3678766626 ps |
| T807 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2786087889 |
|
|
Jul 22 07:37:39 PM PDT 24 |
Jul 22 07:39:38 PM PDT 24 |
82203444764 ps |
| T808 |
/workspace/coverage/default/48.sram_ctrl_smoke.3598840752 |
|
|
Jul 22 07:40:00 PM PDT 24 |
Jul 22 07:41:48 PM PDT 24 |
803594076 ps |
| T809 |
/workspace/coverage/default/43.sram_ctrl_alert_test.4276931691 |
|
|
Jul 22 07:38:51 PM PDT 24 |
Jul 22 07:38:53 PM PDT 24 |
21501716 ps |
| T810 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2974915860 |
|
|
Jul 22 07:33:22 PM PDT 24 |
Jul 22 07:35:28 PM PDT 24 |
9244759835 ps |
| T811 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3138474726 |
|
|
Jul 22 07:32:55 PM PDT 24 |
Jul 22 07:38:56 PM PDT 24 |
29780397846 ps |
| T812 |
/workspace/coverage/default/6.sram_ctrl_bijection.2923398884 |
|
|
Jul 22 07:32:11 PM PDT 24 |
Jul 22 08:16:32 PM PDT 24 |
301796576231 ps |
| T813 |
/workspace/coverage/default/19.sram_ctrl_executable.2050621772 |
|
|
Jul 22 07:33:34 PM PDT 24 |
Jul 22 08:00:24 PM PDT 24 |
22989740371 ps |
| T814 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.773579154 |
|
|
Jul 22 07:33:58 PM PDT 24 |
Jul 22 07:34:06 PM PDT 24 |
712463139 ps |
| T815 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2655000658 |
|
|
Jul 22 07:38:17 PM PDT 24 |
Jul 22 07:43:52 PM PDT 24 |
30037574858 ps |
| T816 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.855765526 |
|
|
Jul 22 07:32:39 PM PDT 24 |
Jul 22 07:32:51 PM PDT 24 |
1789850523 ps |
| T817 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3521364819 |
|
|
Jul 22 07:35:25 PM PDT 24 |
Jul 22 07:35:30 PM PDT 24 |
366306134 ps |
| T18 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.3392275827 |
|
|
Jul 22 07:32:06 PM PDT 24 |
Jul 22 07:32:14 PM PDT 24 |
344537270 ps |
| T818 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.793116952 |
|
|
Jul 22 07:37:22 PM PDT 24 |
Jul 22 07:38:07 PM PDT 24 |
12237592593 ps |
| T819 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.3373498318 |
|
|
Jul 22 07:32:09 PM PDT 24 |
Jul 22 07:44:42 PM PDT 24 |
20600113804 ps |
| T820 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2106125195 |
|
|
Jul 22 07:35:41 PM PDT 24 |
Jul 22 07:57:36 PM PDT 24 |
41826547440 ps |
| T821 |
/workspace/coverage/default/49.sram_ctrl_executable.816164177 |
|
|
Jul 22 07:40:13 PM PDT 24 |
Jul 22 07:52:52 PM PDT 24 |
7725452126 ps |
| T822 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2398040542 |
|
|
Jul 22 07:32:12 PM PDT 24 |
Jul 22 07:32:21 PM PDT 24 |
405486988 ps |
| T823 |
/workspace/coverage/default/47.sram_ctrl_alert_test.4135646683 |
|
|
Jul 22 07:39:53 PM PDT 24 |
Jul 22 07:39:55 PM PDT 24 |
26982257 ps |
| T824 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3766897377 |
|
|
Jul 22 07:32:12 PM PDT 24 |
Jul 22 07:33:27 PM PDT 24 |
5850119911 ps |
| T825 |
/workspace/coverage/default/27.sram_ctrl_bijection.923878126 |
|
|
Jul 22 07:34:52 PM PDT 24 |
Jul 22 08:20:35 PM PDT 24 |
377629162930 ps |
| T826 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2219163721 |
|
|
Jul 22 07:33:52 PM PDT 24 |
Jul 22 07:34:22 PM PDT 24 |
17244765283 ps |
| T827 |
/workspace/coverage/default/23.sram_ctrl_regwen.4264027904 |
|
|
Jul 22 07:34:15 PM PDT 24 |
Jul 22 07:57:46 PM PDT 24 |
62161827267 ps |
| T828 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2296786386 |
|
|
Jul 22 07:36:54 PM PDT 24 |
Jul 22 07:48:59 PM PDT 24 |
118235230861 ps |
| T829 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.842116065 |
|
|
Jul 22 07:39:23 PM PDT 24 |
Jul 22 07:42:09 PM PDT 24 |
19716743855 ps |
| T830 |
/workspace/coverage/default/10.sram_ctrl_regwen.435626766 |
|
|
Jul 22 07:32:31 PM PDT 24 |
Jul 22 07:42:14 PM PDT 24 |
10546271209 ps |
| T831 |
/workspace/coverage/default/29.sram_ctrl_smoke.3684478903 |
|
|
Jul 22 07:35:25 PM PDT 24 |
Jul 22 07:35:47 PM PDT 24 |
1882828540 ps |
| T832 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.4000207999 |
|
|
Jul 22 07:34:56 PM PDT 24 |
Jul 22 07:36:19 PM PDT 24 |
3063683292 ps |
| T833 |
/workspace/coverage/default/26.sram_ctrl_bijection.4260681689 |
|
|
Jul 22 07:34:39 PM PDT 24 |
Jul 22 07:54:14 PM PDT 24 |
50881883104 ps |
| T834 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1993463508 |
|
|
Jul 22 07:39:32 PM PDT 24 |
Jul 22 07:47:01 PM PDT 24 |
174423845500 ps |
| T835 |
/workspace/coverage/default/27.sram_ctrl_partial_access.4232173138 |
|
|
Jul 22 07:34:52 PM PDT 24 |
Jul 22 07:35:11 PM PDT 24 |
1271854166 ps |
| T836 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3697858154 |
|
|
Jul 22 07:35:41 PM PDT 24 |
Jul 22 08:03:18 PM PDT 24 |
9272071335 ps |
| T837 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3762818381 |
|
|
Jul 22 07:36:15 PM PDT 24 |
Jul 22 07:37:02 PM PDT 24 |
13357057461 ps |
| T838 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2558613127 |
|
|
Jul 22 07:34:01 PM PDT 24 |
Jul 22 07:34:07 PM PDT 24 |
4781700209 ps |
| T839 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2535254203 |
|
|
Jul 22 07:38:53 PM PDT 24 |
Jul 22 07:38:57 PM PDT 24 |
5608467127 ps |
| T840 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1523539268 |
|
|
Jul 22 07:36:16 PM PDT 24 |
Jul 22 07:39:56 PM PDT 24 |
8731471845 ps |
| T841 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.636980718 |
|
|
Jul 22 07:32:50 PM PDT 24 |
Jul 22 07:35:22 PM PDT 24 |
76553676444 ps |
| T842 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1383629534 |
|
|
Jul 22 07:36:03 PM PDT 24 |
Jul 22 07:42:01 PM PDT 24 |
15585529673 ps |
| T843 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3727519439 |
|
|
Jul 22 07:37:54 PM PDT 24 |
Jul 22 07:38:32 PM PDT 24 |
5813852414 ps |
| T844 |
/workspace/coverage/default/2.sram_ctrl_stress_all.368214893 |
|
|
Jul 22 07:32:09 PM PDT 24 |
Jul 22 08:28:52 PM PDT 24 |
95398688389 ps |
| T845 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1888798066 |
|
|
Jul 22 07:40:12 PM PDT 24 |
Jul 22 07:45:42 PM PDT 24 |
149631843173 ps |
| T846 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3429239059 |
|
|
Jul 22 07:35:53 PM PDT 24 |
Jul 22 07:47:02 PM PDT 24 |
51378001958 ps |
| T847 |
/workspace/coverage/default/41.sram_ctrl_smoke.3229250924 |
|
|
Jul 22 07:38:19 PM PDT 24 |
Jul 22 07:38:41 PM PDT 24 |
1285519169 ps |
| T848 |
/workspace/coverage/default/15.sram_ctrl_regwen.1438858132 |
|
|
Jul 22 07:32:49 PM PDT 24 |
Jul 22 08:02:38 PM PDT 24 |
18770524365 ps |
| T849 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2402985009 |
|
|
Jul 22 07:36:05 PM PDT 24 |
Jul 22 07:36:44 PM PDT 24 |
5670500358 ps |
| T850 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.1155040568 |
|
|
Jul 22 07:36:04 PM PDT 24 |
Jul 22 07:36:10 PM PDT 24 |
4197081331 ps |
| T851 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3070632195 |
|
|
Jul 22 07:40:18 PM PDT 24 |
Jul 22 09:09:12 PM PDT 24 |
115746770028 ps |
| T852 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2693322408 |
|
|
Jul 22 07:38:51 PM PDT 24 |
Jul 22 07:39:57 PM PDT 24 |
14379268917 ps |
| T853 |
/workspace/coverage/default/42.sram_ctrl_executable.2433553560 |
|
|
Jul 22 07:38:45 PM PDT 24 |
Jul 22 07:52:35 PM PDT 24 |
18215137415 ps |
| T854 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3477223974 |
|
|
Jul 22 07:32:13 PM PDT 24 |
Jul 22 07:33:38 PM PDT 24 |
3136567857 ps |
| T855 |
/workspace/coverage/default/43.sram_ctrl_bijection.3194008925 |
|
|
Jul 22 07:38:45 PM PDT 24 |
Jul 22 07:48:25 PM PDT 24 |
31562144126 ps |
| T856 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.3923029379 |
|
|
Jul 22 07:37:06 PM PDT 24 |
Jul 22 07:37:57 PM PDT 24 |
32221694390 ps |
| T857 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.3805040052 |
|
|
Jul 22 07:34:29 PM PDT 24 |
Jul 22 08:13:10 PM PDT 24 |
267927623203 ps |
| T858 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.627574647 |
|
|
Jul 22 07:40:30 PM PDT 24 |
Jul 22 07:58:26 PM PDT 24 |
202666073346 ps |
| T859 |
/workspace/coverage/default/37.sram_ctrl_bijection.1566811433 |
|
|
Jul 22 07:37:07 PM PDT 24 |
Jul 22 08:13:37 PM PDT 24 |
414531553297 ps |
| T860 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1630973511 |
|
|
Jul 22 07:32:26 PM PDT 24 |
Jul 22 07:41:55 PM PDT 24 |
8867541101 ps |
| T861 |
/workspace/coverage/default/26.sram_ctrl_smoke.1159843305 |
|
|
Jul 22 07:34:41 PM PDT 24 |
Jul 22 07:34:53 PM PDT 24 |
639939580 ps |
| T862 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1668005189 |
|
|
Jul 22 07:32:17 PM PDT 24 |
Jul 22 08:25:22 PM PDT 24 |
28182341527 ps |
| T863 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1531109052 |
|
|
Jul 22 07:38:30 PM PDT 24 |
Jul 22 07:45:17 PM PDT 24 |
18698128184 ps |
| T864 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2422313651 |
|
|
Jul 22 07:32:37 PM PDT 24 |
Jul 22 07:34:54 PM PDT 24 |
10124403044 ps |
| T865 |
/workspace/coverage/default/12.sram_ctrl_smoke.932447720 |
|
|
Jul 22 07:32:37 PM PDT 24 |
Jul 22 07:33:34 PM PDT 24 |
710197361 ps |
| T866 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.2958449279 |
|
|
Jul 22 07:37:53 PM PDT 24 |
Jul 22 07:38:43 PM PDT 24 |
2743886860 ps |
| T867 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2311072524 |
|
|
Jul 22 07:34:39 PM PDT 24 |
Jul 22 07:37:33 PM PDT 24 |
20718695338 ps |
| T868 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.418374422 |
|
|
Jul 22 07:38:18 PM PDT 24 |
Jul 22 07:39:29 PM PDT 24 |
748226852 ps |
| T869 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.906439067 |
|
|
Jul 22 07:34:02 PM PDT 24 |
Jul 22 07:34:15 PM PDT 24 |
2730308632 ps |
| T870 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1329044619 |
|
|
Jul 22 07:34:03 PM PDT 24 |
Jul 22 07:36:10 PM PDT 24 |
2058813574 ps |
| T871 |
/workspace/coverage/default/3.sram_ctrl_bijection.1314711098 |
|
|
Jul 22 07:32:11 PM PDT 24 |
Jul 22 08:10:28 PM PDT 24 |
66246154587 ps |
| T872 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2612242809 |
|
|
Jul 22 07:32:27 PM PDT 24 |
Jul 22 07:34:04 PM PDT 24 |
20168879519 ps |
| T873 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2399538613 |
|
|
Jul 22 07:39:09 PM PDT 24 |
Jul 22 07:40:43 PM PDT 24 |
14838819114 ps |
| T874 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1384723606 |
|
|
Jul 22 07:33:36 PM PDT 24 |
Jul 22 07:34:59 PM PDT 24 |
5549042469 ps |
| T875 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2479046129 |
|
|
Jul 22 07:32:40 PM PDT 24 |
Jul 22 07:49:45 PM PDT 24 |
18817951795 ps |
| T876 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.465595358 |
|
|
Jul 22 07:40:02 PM PDT 24 |
Jul 22 07:41:17 PM PDT 24 |
1406742334 ps |
| T877 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3911735794 |
|
|
Jul 22 07:40:21 PM PDT 24 |
Jul 22 07:41:47 PM PDT 24 |
5441289234 ps |
| T878 |
/workspace/coverage/default/23.sram_ctrl_alert_test.3438573344 |
|
|
Jul 22 07:34:14 PM PDT 24 |
Jul 22 07:34:15 PM PDT 24 |
13702733 ps |
| T101 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.524845215 |
|
|
Jul 22 07:32:49 PM PDT 24 |
Jul 22 07:34:09 PM PDT 24 |
2908118559 ps |
| T879 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.1233900562 |
|
|
Jul 22 07:37:51 PM PDT 24 |
Jul 22 07:40:21 PM PDT 24 |
2532209036 ps |
| T880 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2580931090 |
|
|
Jul 22 07:32:49 PM PDT 24 |
Jul 22 07:35:15 PM PDT 24 |
2946249663 ps |
| T881 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.432399322 |
|
|
Jul 22 07:32:03 PM PDT 24 |
Jul 22 07:36:36 PM PDT 24 |
8695618068 ps |
| T882 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1931252724 |
|
|
Jul 22 07:34:28 PM PDT 24 |
Jul 22 07:34:34 PM PDT 24 |
585245013 ps |
| T883 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1861534147 |
|
|
Jul 22 07:35:05 PM PDT 24 |
Jul 22 07:35:14 PM PDT 24 |
716924459 ps |
| T884 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3953643032 |
|
|
Jul 22 07:32:04 PM PDT 24 |
Jul 22 07:40:24 PM PDT 24 |
9898334346 ps |
| T885 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.3504817524 |
|
|
Jul 22 07:34:56 PM PDT 24 |
Jul 22 07:36:13 PM PDT 24 |
11099124321 ps |
| T886 |
/workspace/coverage/default/26.sram_ctrl_stress_all.494707489 |
|
|
Jul 22 07:35:05 PM PDT 24 |
Jul 22 08:53:17 PM PDT 24 |
71755207923 ps |
| T887 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1472351195 |
|
|
Jul 22 07:32:27 PM PDT 24 |
Jul 22 07:48:25 PM PDT 24 |
11012558868 ps |
| T888 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1681279580 |
|
|
Jul 22 07:36:55 PM PDT 24 |
Jul 22 07:42:20 PM PDT 24 |
5078724442 ps |
| T889 |
/workspace/coverage/default/33.sram_ctrl_regwen.3887087403 |
|
|
Jul 22 07:36:18 PM PDT 24 |
Jul 22 07:43:57 PM PDT 24 |
12247216747 ps |
| T890 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.951266849 |
|
|
Jul 22 07:37:51 PM PDT 24 |
Jul 22 07:43:32 PM PDT 24 |
18488055187 ps |
| T891 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.280152739 |
|
|
Jul 22 07:33:48 PM PDT 24 |
Jul 22 07:36:43 PM PDT 24 |
41373421027 ps |
| T892 |
/workspace/coverage/default/41.sram_ctrl_regwen.514620536 |
|
|
Jul 22 07:38:18 PM PDT 24 |
Jul 22 07:42:00 PM PDT 24 |
3996281418 ps |
| T893 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1510358313 |
|
|
Jul 22 07:34:04 PM PDT 24 |
Jul 22 07:34:40 PM PDT 24 |
735595568 ps |
| T894 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.4269446532 |
|
|
Jul 22 07:34:55 PM PDT 24 |
Jul 22 08:01:32 PM PDT 24 |
26989939096 ps |
| T895 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2610646852 |
|
|
Jul 22 07:35:40 PM PDT 24 |
Jul 22 07:35:48 PM PDT 24 |
2887826741 ps |
| T896 |
/workspace/coverage/default/17.sram_ctrl_smoke.3378186308 |
|
|
Jul 22 07:32:59 PM PDT 24 |
Jul 22 07:33:24 PM PDT 24 |
17171322517 ps |
| T897 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.470838328 |
|
|
Jul 22 07:32:27 PM PDT 24 |
Jul 22 07:34:05 PM PDT 24 |
1575432102 ps |
| T898 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2976388121 |
|
|
Jul 22 07:38:19 PM PDT 24 |
Jul 22 07:42:02 PM PDT 24 |
5203583003 ps |
| T30 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.821149725 |
|
|
Jul 22 07:32:11 PM PDT 24 |
Jul 22 07:32:18 PM PDT 24 |
411468301 ps |
| T31 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.1225715268 |
|
|
Jul 22 07:32:01 PM PDT 24 |
Jul 22 07:32:10 PM PDT 24 |
829771651 ps |
| T899 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3821920291 |
|
|
Jul 22 07:32:09 PM PDT 24 |
Jul 22 07:32:30 PM PDT 24 |
1475298990 ps |
| T900 |
/workspace/coverage/default/36.sram_ctrl_partial_access.3326851849 |
|
|
Jul 22 07:36:54 PM PDT 24 |
Jul 22 07:38:02 PM PDT 24 |
4979440004 ps |
| T901 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1377541811 |
|
|
Jul 22 07:35:52 PM PDT 24 |
Jul 22 07:36:10 PM PDT 24 |
1203105383 ps |
| T902 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3124898843 |
|
|
Jul 22 07:38:18 PM PDT 24 |
Jul 22 07:52:35 PM PDT 24 |
30520049440 ps |
| T903 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.3536640378 |
|
|
Jul 22 07:32:09 PM PDT 24 |
Jul 22 07:32:35 PM PDT 24 |
707373152 ps |
| T904 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2229706937 |
|
|
Jul 22 07:32:48 PM PDT 24 |
Jul 22 07:39:55 PM PDT 24 |
66418196084 ps |
| T905 |
/workspace/coverage/default/8.sram_ctrl_executable.3279540720 |
|
|
Jul 22 07:32:21 PM PDT 24 |
Jul 22 07:44:20 PM PDT 24 |
6758712531 ps |
| T906 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2139530859 |
|
|
Jul 22 07:34:10 PM PDT 24 |
Jul 22 07:35:42 PM PDT 24 |
6388032241 ps |
| T907 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3182681102 |
|
|
Jul 22 07:33:59 PM PDT 24 |
Jul 22 07:38:51 PM PDT 24 |
13524969125 ps |
| T908 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2650237258 |
|
|
Jul 22 07:32:08 PM PDT 24 |
Jul 22 07:33:24 PM PDT 24 |
792549880 ps |
| T909 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1990024696 |
|
|
Jul 22 07:34:02 PM PDT 24 |
Jul 22 07:40:51 PM PDT 24 |
50551460026 ps |
| T910 |
/workspace/coverage/default/19.sram_ctrl_regwen.3421891471 |
|
|
Jul 22 07:33:37 PM PDT 24 |
Jul 22 07:40:14 PM PDT 24 |
2561276401 ps |
| T911 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.1354324604 |
|
|
Jul 22 07:32:17 PM PDT 24 |
Jul 22 07:37:25 PM PDT 24 |
21012896515 ps |
| T912 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.4102871672 |
|
|
Jul 22 07:32:09 PM PDT 24 |
Jul 22 07:38:13 PM PDT 24 |
13451350769 ps |
| T913 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.26525850 |
|
|
Jul 22 07:36:54 PM PDT 24 |
Jul 22 07:38:24 PM PDT 24 |
2998506902 ps |
| T914 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1197322414 |
|
|
Jul 22 07:32:27 PM PDT 24 |
Jul 22 09:14:06 PM PDT 24 |
521605202919 ps |
| T915 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2363499337 |
|
|
Jul 22 07:34:39 PM PDT 24 |
Jul 22 08:05:14 PM PDT 24 |
83180769543 ps |
| T916 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3762946942 |
|
|
Jul 22 07:38:19 PM PDT 24 |
Jul 22 07:38:21 PM PDT 24 |
44734903 ps |
| T917 |
/workspace/coverage/default/34.sram_ctrl_alert_test.2813593553 |
|
|
Jul 22 07:36:42 PM PDT 24 |
Jul 22 07:36:44 PM PDT 24 |
14182959 ps |
| T918 |
/workspace/coverage/default/31.sram_ctrl_alert_test.140978601 |
|
|
Jul 22 07:36:02 PM PDT 24 |
Jul 22 07:36:03 PM PDT 24 |
35533621 ps |
| T919 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.252439417 |
|
|
Jul 22 07:39:33 PM PDT 24 |
Jul 22 07:40:20 PM PDT 24 |
3047045124 ps |
| T920 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1409032565 |
|
|
Jul 22 07:32:33 PM PDT 24 |
Jul 22 07:54:01 PM PDT 24 |
22429610795 ps |
| T921 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1029274722 |
|
|
Jul 22 07:32:58 PM PDT 24 |
Jul 22 08:01:02 PM PDT 24 |
22589255511 ps |
| T922 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2489622735 |
|
|
Jul 22 07:40:30 PM PDT 24 |
Jul 22 07:44:57 PM PDT 24 |
8284532633 ps |
| T923 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3873391469 |
|
|
Jul 22 07:40:18 PM PDT 24 |
Jul 22 07:59:08 PM PDT 24 |
56284094187 ps |
| T924 |
/workspace/coverage/default/46.sram_ctrl_executable.2816552463 |
|
|
Jul 22 07:39:33 PM PDT 24 |
Jul 22 08:09:35 PM PDT 24 |
18389700267 ps |
| T925 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2138053672 |
|
|
Jul 22 07:33:49 PM PDT 24 |
Jul 22 07:34:16 PM PDT 24 |
715489627 ps |
| T926 |
/workspace/coverage/default/23.sram_ctrl_partial_access.3631019843 |
|
|
Jul 22 07:34:17 PM PDT 24 |
Jul 22 07:34:25 PM PDT 24 |
697798506 ps |
| T927 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.2798988552 |
|
|
Jul 22 07:37:08 PM PDT 24 |
Jul 22 07:37:13 PM PDT 24 |
1407204588 ps |
| T928 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3735554035 |
|
|
Jul 22 07:39:09 PM PDT 24 |
Jul 22 07:44:08 PM PDT 24 |
4591479124 ps |
| T929 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1267816889 |
|
|
Jul 22 07:37:40 PM PDT 24 |
Jul 22 07:39:35 PM PDT 24 |
1668710706 ps |
| T930 |
/workspace/coverage/default/45.sram_ctrl_executable.2950856813 |
|
|
Jul 22 07:39:08 PM PDT 24 |
Jul 22 08:14:18 PM PDT 24 |
9181744838 ps |
| T931 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2380824772 |
|
|
Jul 22 07:34:26 PM PDT 24 |
Jul 22 07:34:32 PM PDT 24 |
4199670481 ps |
| T932 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.290632806 |
|
|
Jul 22 07:33:20 PM PDT 24 |
Jul 22 07:35:17 PM PDT 24 |
1520398384 ps |
| T933 |
/workspace/coverage/default/31.sram_ctrl_bijection.2750378440 |
|
|
Jul 22 07:35:52 PM PDT 24 |
Jul 22 07:57:08 PM PDT 24 |
78999197129 ps |
| T934 |
/workspace/coverage/default/2.sram_ctrl_alert_test.1229986211 |
|
|
Jul 22 07:32:12 PM PDT 24 |
Jul 22 07:32:17 PM PDT 24 |
21150182 ps |
| T935 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1280355142 |
|
|
Jul 22 07:32:02 PM PDT 24 |
Jul 22 07:50:48 PM PDT 24 |
38507142405 ps |
| T936 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3518414262 |
|
|
Jul 22 07:35:42 PM PDT 24 |
Jul 22 07:38:16 PM PDT 24 |
6478300699 ps |
| T937 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2517884931 |
|
|
Jul 22 07:36:55 PM PDT 24 |
Jul 22 07:45:37 PM PDT 24 |
2860824115 ps |
| T938 |
/workspace/coverage/default/35.sram_ctrl_bijection.3727326886 |
|
|
Jul 22 07:36:41 PM PDT 24 |
Jul 22 07:44:58 PM PDT 24 |
27561328541 ps |
| T939 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3471497399 |
|
|
Jul 22 07:32:50 PM PDT 24 |
Jul 22 07:39:26 PM PDT 24 |
25180633521 ps |
| T940 |
/workspace/coverage/default/5.sram_ctrl_executable.490496988 |
|
|
Jul 22 07:32:49 PM PDT 24 |
Jul 22 07:50:45 PM PDT 24 |
17850647197 ps |
| T941 |
/workspace/coverage/default/7.sram_ctrl_regwen.3058646989 |
|
|
Jul 22 07:32:27 PM PDT 24 |
Jul 22 07:58:50 PM PDT 24 |
21784973485 ps |
| T942 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2973674951 |
|
|
Jul 22 07:38:52 PM PDT 24 |
Jul 22 07:41:18 PM PDT 24 |
7131070860 ps |
| T943 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.497078681 |
|
|
Jul 22 07:32:24 PM PDT 24 |
Jul 22 07:47:03 PM PDT 24 |
30901394392 ps |
| T944 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1405040046 |
|
|
Jul 22 07:38:50 PM PDT 24 |
Jul 22 08:41:03 PM PDT 24 |
646466955372 ps |
| T67 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3903450841 |
|
|
Jul 22 07:27:42 PM PDT 24 |
Jul 22 07:28:51 PM PDT 24 |
119710226 ps |
| T71 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.220306759 |
|
|
Jul 22 07:27:30 PM PDT 24 |
Jul 22 07:29:41 PM PDT 24 |
27079040458 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.824744749 |
|
|
Jul 22 07:26:38 PM PDT 24 |
Jul 22 07:27:59 PM PDT 24 |
25849940 ps |
| T946 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.23843700 |
|
|
Jul 22 07:27:02 PM PDT 24 |
Jul 22 07:28:23 PM PDT 24 |
506955838 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1996125390 |
|
|
Jul 22 07:26:51 PM PDT 24 |
Jul 22 07:28:58 PM PDT 24 |
7720582883 ps |
| T947 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.365740450 |
|
|
Jul 22 07:26:53 PM PDT 24 |
Jul 22 07:28:16 PM PDT 24 |
1029100445 ps |
| T110 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.810890940 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:21 PM PDT 24 |
27664810 ps |
| T948 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1019394208 |
|
|
Jul 22 07:27:12 PM PDT 24 |
Jul 22 07:28:28 PM PDT 24 |
606504903 ps |
| T111 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3481192043 |
|
|
Jul 22 07:27:11 PM PDT 24 |
Jul 22 07:28:25 PM PDT 24 |
26531721 ps |
| T112 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4011166735 |
|
|
Jul 22 07:27:10 PM PDT 24 |
Jul 22 07:28:24 PM PDT 24 |
26997225 ps |
| T84 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.754495801 |
|
|
Jul 22 07:27:08 PM PDT 24 |
Jul 22 07:28:23 PM PDT 24 |
15639393 ps |
| T949 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2158390090 |
|
|
Jul 22 07:27:13 PM PDT 24 |
Jul 22 07:28:29 PM PDT 24 |
359363702 ps |
| T119 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3630329557 |
|
|
Jul 22 07:27:02 PM PDT 24 |
Jul 22 07:28:20 PM PDT 24 |
44741167 ps |
| T68 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.432040924 |
|
|
Jul 22 07:27:11 PM PDT 24 |
Jul 22 07:28:26 PM PDT 24 |
283165823 ps |
| T69 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1122047768 |
|
|
Jul 22 07:27:25 PM PDT 24 |
Jul 22 07:28:38 PM PDT 24 |
95296070 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3841332122 |
|
|
Jul 22 07:26:52 PM PDT 24 |
Jul 22 07:28:11 PM PDT 24 |
126295594 ps |
| T120 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2265167705 |
|
|
Jul 22 07:26:43 PM PDT 24 |
Jul 22 07:27:59 PM PDT 24 |
18151300 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2769028830 |
|
|
Jul 22 07:26:39 PM PDT 24 |
Jul 22 07:28:50 PM PDT 24 |
26084721526 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2502164061 |
|
|
Jul 22 07:26:42 PM PDT 24 |
Jul 22 07:29:00 PM PDT 24 |
28292224032 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3573029148 |
|
|
Jul 22 07:26:28 PM PDT 24 |
Jul 22 07:27:51 PM PDT 24 |
38632693 ps |
| T113 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.184858334 |
|
|
Jul 22 07:27:06 PM PDT 24 |
Jul 22 07:28:21 PM PDT 24 |
14833249 ps |
| T951 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2199776770 |
|
|
Jul 22 07:27:23 PM PDT 24 |
Jul 22 07:28:38 PM PDT 24 |
301519275 ps |
| T114 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3706563800 |
|
|
Jul 22 07:26:38 PM PDT 24 |
Jul 22 07:27:57 PM PDT 24 |
72642507 ps |
| T137 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1775212883 |
|
|
Jul 22 07:27:40 PM PDT 24 |
Jul 22 07:28:50 PM PDT 24 |
1250023252 ps |
| T952 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.386496476 |
|
|
Jul 22 07:27:12 PM PDT 24 |
Jul 22 07:28:26 PM PDT 24 |
11252869 ps |
| T139 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1797070009 |
|
|
Jul 22 07:28:03 PM PDT 24 |
Jul 22 07:29:06 PM PDT 24 |
602544679 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3098659109 |
|
|
Jul 22 07:27:02 PM PDT 24 |
Jul 22 07:28:23 PM PDT 24 |
135011188 ps |
| T88 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3628000761 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:20 PM PDT 24 |
23879456 ps |
| T89 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4155160772 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:48 PM PDT 24 |
3814164364 ps |
| T138 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3323199949 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:21 PM PDT 24 |
158774779 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1255436987 |
|
|
Jul 22 07:27:08 PM PDT 24 |
Jul 22 07:28:26 PM PDT 24 |
1312940570 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.27509012 |
|
|
Jul 22 07:26:29 PM PDT 24 |
Jul 22 07:27:53 PM PDT 24 |
44946511 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3225733123 |
|
|
Jul 22 07:26:54 PM PDT 24 |
Jul 22 07:28:16 PM PDT 24 |
2286949634 ps |
| T957 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1265145624 |
|
|
Jul 22 07:27:06 PM PDT 24 |
Jul 22 07:29:14 PM PDT 24 |
25321952204 ps |
| T142 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1337694244 |
|
|
Jul 22 07:26:53 PM PDT 24 |
Jul 22 07:28:13 PM PDT 24 |
327591785 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2568157432 |
|
|
Jul 22 07:26:27 PM PDT 24 |
Jul 22 07:27:48 PM PDT 24 |
12524644 ps |
| T144 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.215808048 |
|
|
Jul 22 07:27:22 PM PDT 24 |
Jul 22 07:28:37 PM PDT 24 |
375941925 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2047887180 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:20 PM PDT 24 |
34278863 ps |
| T960 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.920701296 |
|
|
Jul 22 07:27:09 PM PDT 24 |
Jul 22 07:28:26 PM PDT 24 |
356707089 ps |
| T148 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4293958849 |
|
|
Jul 22 07:27:25 PM PDT 24 |
Jul 22 07:28:38 PM PDT 24 |
76161762 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2026277455 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:57 PM PDT 24 |
36943153429 ps |
| T962 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.509497135 |
|
|
Jul 22 07:27:29 PM PDT 24 |
Jul 22 07:28:39 PM PDT 24 |
69064580 ps |
| T90 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2372049553 |
|
|
Jul 22 07:26:49 PM PDT 24 |
Jul 22 07:28:06 PM PDT 24 |
15360619 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4099632589 |
|
|
Jul 22 07:27:42 PM PDT 24 |
Jul 22 07:28:50 PM PDT 24 |
22011283 ps |
| T964 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2895452253 |
|
|
Jul 22 07:27:35 PM PDT 24 |
Jul 22 07:28:43 PM PDT 24 |
33732094 ps |
| T965 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3968882519 |
|
|
Jul 22 07:27:30 PM PDT 24 |
Jul 22 07:28:43 PM PDT 24 |
127601503 ps |
| T966 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4256611953 |
|
|
Jul 22 07:27:19 PM PDT 24 |
Jul 22 07:28:36 PM PDT 24 |
347436499 ps |
| T91 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1111055600 |
|
|
Jul 22 07:26:51 PM PDT 24 |
Jul 22 07:28:10 PM PDT 24 |
11642303 ps |
| T967 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2950430111 |
|
|
Jul 22 07:27:23 PM PDT 24 |
Jul 22 07:28:36 PM PDT 24 |
23792901 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4060639415 |
|
|
Jul 22 07:26:52 PM PDT 24 |
Jul 22 07:28:10 PM PDT 24 |
17775797 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1406066235 |
|
|
Jul 22 07:27:50 PM PDT 24 |
Jul 22 07:28:56 PM PDT 24 |
455497522 ps |
| T93 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3124715207 |
|
|
Jul 22 07:27:31 PM PDT 24 |
Jul 22 07:29:11 PM PDT 24 |
15351432125 ps |
| T970 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1480498169 |
|
|
Jul 22 07:27:30 PM PDT 24 |
Jul 22 07:28:43 PM PDT 24 |
443392794 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.756365834 |
|
|
Jul 22 07:26:52 PM PDT 24 |
Jul 22 07:28:14 PM PDT 24 |
129781858 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3462981867 |
|
|
Jul 22 07:27:32 PM PDT 24 |
Jul 22 07:28:43 PM PDT 24 |
54624109 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.599585083 |
|
|
Jul 22 07:26:40 PM PDT 24 |
Jul 22 07:27:59 PM PDT 24 |
48727686 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3804412099 |
|
|
Jul 22 07:26:39 PM PDT 24 |
Jul 22 07:27:59 PM PDT 24 |
61946706 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3429895287 |
|
|
Jul 22 07:26:52 PM PDT 24 |
Jul 22 07:28:11 PM PDT 24 |
33084101 ps |
| T94 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1648622109 |
|
|
Jul 22 07:26:51 PM PDT 24 |
Jul 22 07:28:09 PM PDT 24 |
14492399 ps |
| T141 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3134777648 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:21 PM PDT 24 |
173479165 ps |
| T976 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1186542857 |
|
|
Jul 22 07:27:21 PM PDT 24 |
Jul 22 07:28:35 PM PDT 24 |
31087265 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2452616746 |
|
|
Jul 22 07:26:41 PM PDT 24 |
Jul 22 07:28:00 PM PDT 24 |
159263406 ps |
| T978 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2959957940 |
|
|
Jul 22 07:27:32 PM PDT 24 |
Jul 22 07:28:41 PM PDT 24 |
39115227 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.114640609 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:22 PM PDT 24 |
97815787 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1445092 |
|
|
Jul 22 07:26:38 PM PDT 24 |
Jul 22 07:27:57 PM PDT 24 |
47977468 ps |
| T981 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1552020019 |
|
|
Jul 22 07:26:52 PM PDT 24 |
Jul 22 07:28:13 PM PDT 24 |
244840810 ps |
| T95 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.767557594 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:46 PM PDT 24 |
14769797540 ps |
| T96 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3720858825 |
|
|
Jul 22 07:27:24 PM PDT 24 |
Jul 22 07:29:03 PM PDT 24 |
14751416517 ps |
| T108 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3480691684 |
|
|
Jul 22 07:26:52 PM PDT 24 |
Jul 22 07:28:38 PM PDT 24 |
3939991821 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2438118967 |
|
|
Jul 22 07:26:51 PM PDT 24 |
Jul 22 07:28:09 PM PDT 24 |
21636335 ps |
| T149 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3281527245 |
|
|
Jul 22 07:27:08 PM PDT 24 |
Jul 22 07:28:24 PM PDT 24 |
78859591 ps |
| T109 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1727614083 |
|
|
Jul 22 07:27:31 PM PDT 24 |
Jul 22 07:28:41 PM PDT 24 |
43313248 ps |
| T983 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1734989240 |
|
|
Jul 22 07:26:52 PM PDT 24 |
Jul 22 07:28:11 PM PDT 24 |
27919053 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2716993525 |
|
|
Jul 22 07:27:31 PM PDT 24 |
Jul 22 07:28:44 PM PDT 24 |
756139291 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1605272648 |
|
|
Jul 22 07:26:28 PM PDT 24 |
Jul 22 07:27:51 PM PDT 24 |
14813560 ps |
| T985 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2595996504 |
|
|
Jul 22 07:27:02 PM PDT 24 |
Jul 22 07:28:23 PM PDT 24 |
366652975 ps |
| T986 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3825323087 |
|
|
Jul 22 07:27:04 PM PDT 24 |
Jul 22 07:28:24 PM PDT 24 |
387859318 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3499523605 |
|
|
Jul 22 07:27:25 PM PDT 24 |
Jul 22 07:28:38 PM PDT 24 |
23752520 ps |
| T988 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.438017503 |
|
|
Jul 22 07:27:08 PM PDT 24 |
Jul 22 07:28:25 PM PDT 24 |
31216334 ps |
| T103 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1076542445 |
|
|
Jul 22 07:27:05 PM PDT 24 |
Jul 22 07:28:21 PM PDT 24 |
62576063 ps |
| T989 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2779521429 |
|
|
Jul 22 07:26:39 PM PDT 24 |
Jul 22 07:28:01 PM PDT 24 |
212967321 ps |
| T990 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1200944721 |
|
|
Jul 22 07:27:20 PM PDT 24 |
Jul 22 07:28:33 PM PDT 24 |
14191963 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1088191738 |
|
|
Jul 22 07:26:29 PM PDT 24 |
Jul 22 07:27:56 PM PDT 24 |
179262610 ps |
| T992 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2718152730 |
|
|
Jul 22 07:27:31 PM PDT 24 |
Jul 22 07:28:40 PM PDT 24 |
30652421 ps |
| T993 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2555939460 |
|
|
Jul 22 07:27:19 PM PDT 24 |
Jul 22 07:28:33 PM PDT 24 |
17417407 ps |
| T994 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1859035005 |
|
|
Jul 22 07:27:31 PM PDT 24 |
Jul 22 07:28:41 PM PDT 24 |
21090659 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3502102863 |
|
|
Jul 22 07:27:14 PM PDT 24 |
Jul 22 07:29:17 PM PDT 24 |
7121227767 ps |
| T104 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4285181334 |
|
|
Jul 22 07:27:39 PM PDT 24 |
Jul 22 07:29:17 PM PDT 24 |
15363198950 ps |
| T996 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3400759255 |
|
|
Jul 22 07:27:07 PM PDT 24 |
Jul 22 07:28:24 PM PDT 24 |
268531758 ps |
| T145 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.97490 |
|
|
Jul 22 07:27:05 PM PDT 24 |
Jul 22 07:28:23 PM PDT 24 |
443977414 ps |
| T105 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2452064256 |
|
|
Jul 22 07:27:30 PM PDT 24 |
Jul 22 07:28:39 PM PDT 24 |
39191396 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4087313808 |
|
|
Jul 22 07:27:11 PM PDT 24 |
Jul 22 07:28:29 PM PDT 24 |
365088555 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2446550848 |
|
|
Jul 22 07:27:49 PM PDT 24 |
Jul 22 07:28:53 PM PDT 24 |
86555834 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1842399803 |
|
|
Jul 22 07:26:28 PM PDT 24 |
Jul 22 07:27:52 PM PDT 24 |
201768113 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.61421759 |
|
|
Jul 22 07:26:43 PM PDT 24 |
Jul 22 07:27:59 PM PDT 24 |
30174634 ps |
| T1001 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2766588453 |
|
|
Jul 22 07:27:16 PM PDT 24 |
Jul 22 07:28:32 PM PDT 24 |
355200989 ps |
| T1002 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.359588892 |
|
|
Jul 22 07:27:03 PM PDT 24 |
Jul 22 07:28:23 PM PDT 24 |
371319274 ps |
| T1003 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3276423992 |
|
|
Jul 22 07:26:52 PM PDT 24 |
Jul 22 07:28:37 PM PDT 24 |
15329238376 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1235395461 |
|
|
Jul 22 07:26:50 PM PDT 24 |
Jul 22 07:28:09 PM PDT 24 |
1891462150 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3454907033 |
|
|
Jul 22 07:26:39 PM PDT 24 |
Jul 22 07:28:03 PM PDT 24 |
3198474843 ps |
| T1006 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1070285857 |
|
|
Jul 22 07:27:31 PM PDT 24 |
Jul 22 07:28:43 PM PDT 24 |
748013043 ps |