Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	342353478	1			T1	2834		T2	242940		T3	722545
instr_valid_dis	306462649	1			T1	2834		T2	242940		T3	702586
instr_en	25402352	1			T3	101686		T9	2262		T25	44972

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13630298	1			T3	83022		T26	20284		T17	434936
sram_ifetch_valid_disable	300697165	1			T1	2834		T2	242940		T3	705818
sram_ifetch_enable	28026015	1			T3	84254		T25	103498		T26	221164

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	342353478	1			T1	2834		T2	242940		T3	722545
hw_debug_en_valid_off	302624899	1			T1	2834		T2	242940		T3	707209
hw_debug_en_on	27817298	1			T3	50682		T9	2262		T25	122866

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	300697165	1			T1	2834		T2	242940		T3	705818
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	286648575	1			T1	2834		T2	242940		T3	697400
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10499081	1			T3	64180		T9	2262		T25	34290
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6474430	1			T3	9288		T17	136760		T18	143168
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3678890	1			T3	9288		T18	143168		T78	56420
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2116624	1			T17	136760		T33	12354		T147	21278
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4234980	1			T26	5680		T17	145008		T18	154568
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2045188	1			T17	87972		T18	154568		T78	18020
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1470774	1			T26	5680		T17	57036		T78	43304
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11743740	1			T3	50682		T9	2262		T25	104228
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6327884	1			T3	7770		T25	53506		T17	395098
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4151948	1			T3	42912		T9	2262		T25	34290

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9638717	1			T3	24642		T25	10682		T26	193622
lc_exec_en	11838578	1			T25	18638		T26	26616		T17	127942
valid_exec_dis	297456917	1			T1	2834		T2	242940		T3	705007
invalid_exec_dis	41656313	1			T3	167276		T25	103498		T26	241448