Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	140791649	1			T1	1289		T2	110375		T3	353004
triple_byte_access	2860031	1			T1	26		T2	2230		T3	1111
halfword_access	4386052	1			T1	37		T2	3309		T3	1701
byte_access	6140213	1			T1	46		T2	4447		T3	2390
zero_access	1859010	1			T1	19		T2	1109		T3	594

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77799519

1

T1

736

T2

60520

T3

177169

auto[1]

78237436

1

T1

681

T2

60950

T3

176414

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70037765	1			T1	681		T2	54945		T3	176849
auto[0]	triple_byte_access	1362669	1			T1	8		T2	1117		T3	608
auto[0]	halfword_access	2141984	1			T1	20		T2	1665		T3	939
auto[0]	byte_access	3147026	1			T1	20		T2	2218		T3	1310
auto[0]	zero_access	1110075	1			T1	7		T2	575		T3	346
auto[1]	word_access	70753884	1			T1	608		T2	55430		T3	176154
auto[1]	triple_byte_access	1497362	1			T1	18		T2	1113		T3	503
auto[1]	halfword_access	2244068	1			T1	17		T2	1644		T3	762
auto[1]	byte_access	2993187	1			T1	26		T2	2229		T3	1080
auto[1]	zero_access	748935	1			T1	12		T2	534		T3	248