| T793 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3675262487 |
|
|
Jul 23 06:10:19 PM PDT 24 |
Jul 23 06:18:05 PM PDT 24 |
26320041019 ps |
| T794 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.19570977 |
|
|
Jul 23 06:13:33 PM PDT 24 |
Jul 23 06:20:22 PM PDT 24 |
11579720589 ps |
| T795 |
/workspace/coverage/default/7.sram_ctrl_alert_test.252042970 |
|
|
Jul 23 06:10:41 PM PDT 24 |
Jul 23 06:10:46 PM PDT 24 |
35354178 ps |
| T796 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2513090240 |
|
|
Jul 23 06:11:08 PM PDT 24 |
Jul 23 06:11:17 PM PDT 24 |
2986122923 ps |
| T797 |
/workspace/coverage/default/17.sram_ctrl_partial_access.68476349 |
|
|
Jul 23 06:10:56 PM PDT 24 |
Jul 23 06:11:11 PM PDT 24 |
958438934 ps |
| T798 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.2905542138 |
|
|
Jul 23 06:11:51 PM PDT 24 |
Jul 23 06:16:11 PM PDT 24 |
9957079330 ps |
| T799 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2375336329 |
|
|
Jul 23 06:11:24 PM PDT 24 |
Jul 23 06:12:47 PM PDT 24 |
10480523055 ps |
| T800 |
/workspace/coverage/default/18.sram_ctrl_smoke.3651999645 |
|
|
Jul 23 06:11:03 PM PDT 24 |
Jul 23 06:11:13 PM PDT 24 |
1448045459 ps |
| T801 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2552375681 |
|
|
Jul 23 06:10:42 PM PDT 24 |
Jul 23 07:24:53 PM PDT 24 |
729942070246 ps |
| T802 |
/workspace/coverage/default/15.sram_ctrl_regwen.554610463 |
|
|
Jul 23 06:10:59 PM PDT 24 |
Jul 23 06:42:41 PM PDT 24 |
19001586039 ps |
| T803 |
/workspace/coverage/default/40.sram_ctrl_bijection.2875160151 |
|
|
Jul 23 06:12:33 PM PDT 24 |
Jul 23 06:50:48 PM PDT 24 |
473805898451 ps |
| T804 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.602082901 |
|
|
Jul 23 06:13:13 PM PDT 24 |
Jul 23 06:13:45 PM PDT 24 |
1084460815 ps |
| T805 |
/workspace/coverage/default/43.sram_ctrl_smoke.2888614331 |
|
|
Jul 23 06:12:51 PM PDT 24 |
Jul 23 06:14:48 PM PDT 24 |
993924319 ps |
| T806 |
/workspace/coverage/default/21.sram_ctrl_partial_access.142096792 |
|
|
Jul 23 06:11:08 PM PDT 24 |
Jul 23 06:12:38 PM PDT 24 |
1038505405 ps |
| T807 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1024765433 |
|
|
Jul 23 06:10:51 PM PDT 24 |
Jul 23 06:30:29 PM PDT 24 |
18344607671 ps |
| T808 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.2691689235 |
|
|
Jul 23 06:11:12 PM PDT 24 |
Jul 23 06:14:16 PM PDT 24 |
5593854249 ps |
| T809 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.1901840302 |
|
|
Jul 23 06:10:40 PM PDT 24 |
Jul 23 06:15:12 PM PDT 24 |
4110092591 ps |
| T810 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2092687159 |
|
|
Jul 23 06:11:43 PM PDT 24 |
Jul 23 06:11:47 PM PDT 24 |
344692181 ps |
| T811 |
/workspace/coverage/default/26.sram_ctrl_partial_access.539491080 |
|
|
Jul 23 06:11:24 PM PDT 24 |
Jul 23 06:12:16 PM PDT 24 |
4572217882 ps |
| T812 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1937808222 |
|
|
Jul 23 06:10:17 PM PDT 24 |
Jul 23 06:10:35 PM PDT 24 |
5474532762 ps |
| T813 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2693053375 |
|
|
Jul 23 06:12:32 PM PDT 24 |
Jul 23 06:14:27 PM PDT 24 |
2712031843 ps |
| T814 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1833192110 |
|
|
Jul 23 06:12:58 PM PDT 24 |
Jul 23 06:25:11 PM PDT 24 |
42285630578 ps |
| T815 |
/workspace/coverage/default/42.sram_ctrl_executable.1975497555 |
|
|
Jul 23 06:12:50 PM PDT 24 |
Jul 23 06:30:45 PM PDT 24 |
39327439497 ps |
| T816 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1570411515 |
|
|
Jul 23 06:10:57 PM PDT 24 |
Jul 23 06:28:45 PM PDT 24 |
22109017161 ps |
| T817 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2566712754 |
|
|
Jul 23 06:10:45 PM PDT 24 |
Jul 23 06:11:13 PM PDT 24 |
3330294788 ps |
| T818 |
/workspace/coverage/default/16.sram_ctrl_executable.4265581232 |
|
|
Jul 23 06:10:47 PM PDT 24 |
Jul 23 06:41:01 PM PDT 24 |
22270915421 ps |
| T819 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.3432930073 |
|
|
Jul 23 06:12:41 PM PDT 24 |
Jul 23 06:13:38 PM PDT 24 |
34232474854 ps |
| T820 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1771411134 |
|
|
Jul 23 06:10:31 PM PDT 24 |
Jul 23 06:11:42 PM PDT 24 |
3233490780 ps |
| T821 |
/workspace/coverage/default/36.sram_ctrl_bijection.304234692 |
|
|
Jul 23 06:12:05 PM PDT 24 |
Jul 23 06:56:45 PM PDT 24 |
423212352781 ps |
| T822 |
/workspace/coverage/default/47.sram_ctrl_regwen.1996800262 |
|
|
Jul 23 06:13:49 PM PDT 24 |
Jul 23 06:24:11 PM PDT 24 |
11675458040 ps |
| T823 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.189646828 |
|
|
Jul 23 06:10:22 PM PDT 24 |
Jul 23 06:10:38 PM PDT 24 |
180939853 ps |
| T824 |
/workspace/coverage/default/33.sram_ctrl_regwen.150925003 |
|
|
Jul 23 06:11:52 PM PDT 24 |
Jul 23 06:21:48 PM PDT 24 |
38926341752 ps |
| T825 |
/workspace/coverage/default/4.sram_ctrl_regwen.967560258 |
|
|
Jul 23 06:10:24 PM PDT 24 |
Jul 23 06:13:44 PM PDT 24 |
1208612039 ps |
| T826 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.1077087839 |
|
|
Jul 23 06:10:54 PM PDT 24 |
Jul 23 06:11:37 PM PDT 24 |
723352572 ps |
| T827 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2558507218 |
|
|
Jul 23 06:11:40 PM PDT 24 |
Jul 23 08:07:59 PM PDT 24 |
3403961993374 ps |
| T828 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1829111677 |
|
|
Jul 23 06:10:45 PM PDT 24 |
Jul 23 06:11:26 PM PDT 24 |
3654370999 ps |
| T829 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1944180747 |
|
|
Jul 23 06:13:26 PM PDT 24 |
Jul 23 06:13:35 PM PDT 24 |
282702401 ps |
| T830 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2822225856 |
|
|
Jul 23 06:12:22 PM PDT 24 |
Jul 23 06:15:00 PM PDT 24 |
2714059609 ps |
| T831 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2219373724 |
|
|
Jul 23 06:12:48 PM PDT 24 |
Jul 23 06:13:00 PM PDT 24 |
670217589 ps |
| T832 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2218256651 |
|
|
Jul 23 06:13:15 PM PDT 24 |
Jul 23 06:15:56 PM PDT 24 |
12019346698 ps |
| T833 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4165628718 |
|
|
Jul 23 06:11:32 PM PDT 24 |
Jul 23 06:13:21 PM PDT 24 |
776749221 ps |
| T834 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.258297962 |
|
|
Jul 23 06:13:31 PM PDT 24 |
Jul 23 06:22:38 PM PDT 24 |
39387980483 ps |
| T835 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3919139229 |
|
|
Jul 23 06:10:22 PM PDT 24 |
Jul 23 06:10:49 PM PDT 24 |
12227914378 ps |
| T836 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2560565154 |
|
|
Jul 23 06:11:38 PM PDT 24 |
Jul 23 06:13:34 PM PDT 24 |
769116687 ps |
| T837 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.239998019 |
|
|
Jul 23 06:13:06 PM PDT 24 |
Jul 23 06:15:37 PM PDT 24 |
3098518511 ps |
| T838 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.2613491588 |
|
|
Jul 23 06:11:01 PM PDT 24 |
Jul 23 06:13:35 PM PDT 24 |
5392142741 ps |
| T839 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.3411430080 |
|
|
Jul 23 06:11:39 PM PDT 24 |
Jul 23 06:15:08 PM PDT 24 |
6167219282 ps |
| T840 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.931540601 |
|
|
Jul 23 06:12:56 PM PDT 24 |
Jul 23 06:18:02 PM PDT 24 |
15924868441 ps |
| T841 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2305846324 |
|
|
Jul 23 06:10:17 PM PDT 24 |
Jul 23 06:10:59 PM PDT 24 |
3172001721 ps |
| T842 |
/workspace/coverage/default/34.sram_ctrl_executable.728658443 |
|
|
Jul 23 06:11:56 PM PDT 24 |
Jul 23 06:23:17 PM PDT 24 |
33467206495 ps |
| T843 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2349345449 |
|
|
Jul 23 06:10:19 PM PDT 24 |
Jul 23 06:14:38 PM PDT 24 |
7359052904 ps |
| T844 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.893604283 |
|
|
Jul 23 06:11:30 PM PDT 24 |
Jul 23 06:12:13 PM PDT 24 |
3761256292 ps |
| T845 |
/workspace/coverage/default/26.sram_ctrl_bijection.3056527967 |
|
|
Jul 23 06:11:17 PM PDT 24 |
Jul 23 06:40:55 PM PDT 24 |
493733577050 ps |
| T846 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.682601169 |
|
|
Jul 23 06:12:58 PM PDT 24 |
Jul 23 06:13:05 PM PDT 24 |
2783168317 ps |
| T847 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3586397655 |
|
|
Jul 23 06:11:40 PM PDT 24 |
Jul 23 06:11:43 PM PDT 24 |
14164615 ps |
| T848 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.900870293 |
|
|
Jul 23 06:11:01 PM PDT 24 |
Jul 23 06:12:16 PM PDT 24 |
779846830 ps |
| T849 |
/workspace/coverage/default/27.sram_ctrl_executable.641601615 |
|
|
Jul 23 06:11:26 PM PDT 24 |
Jul 23 06:22:58 PM PDT 24 |
11555806056 ps |
| T850 |
/workspace/coverage/default/2.sram_ctrl_bijection.3518392358 |
|
|
Jul 23 06:10:21 PM PDT 24 |
Jul 23 06:23:17 PM PDT 24 |
67583782274 ps |
| T851 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3194540459 |
|
|
Jul 23 06:12:07 PM PDT 24 |
Jul 23 06:17:29 PM PDT 24 |
15466777557 ps |
| T852 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3098525969 |
|
|
Jul 23 06:11:56 PM PDT 24 |
Jul 23 06:13:21 PM PDT 24 |
2411544729 ps |
| T853 |
/workspace/coverage/default/49.sram_ctrl_regwen.69637468 |
|
|
Jul 23 06:14:00 PM PDT 24 |
Jul 23 06:19:36 PM PDT 24 |
5082963273 ps |
| T854 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4005928368 |
|
|
Jul 23 06:10:46 PM PDT 24 |
Jul 23 06:11:01 PM PDT 24 |
2348440663 ps |
| T855 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3586922050 |
|
|
Jul 23 06:10:46 PM PDT 24 |
Jul 23 06:25:05 PM PDT 24 |
7542649954 ps |
| T856 |
/workspace/coverage/default/24.sram_ctrl_regwen.3147279570 |
|
|
Jul 23 06:11:21 PM PDT 24 |
Jul 23 06:18:40 PM PDT 24 |
2370599785 ps |
| T857 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3805151956 |
|
|
Jul 23 06:11:08 PM PDT 24 |
Jul 23 06:16:26 PM PDT 24 |
21008330172 ps |
| T858 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.606826724 |
|
|
Jul 23 06:12:21 PM PDT 24 |
Jul 23 06:14:56 PM PDT 24 |
9769309198 ps |
| T859 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.2643375067 |
|
|
Jul 23 06:11:11 PM PDT 24 |
Jul 23 06:11:19 PM PDT 24 |
681255331 ps |
| T860 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2948987283 |
|
|
Jul 23 06:11:29 PM PDT 24 |
Jul 23 06:18:20 PM PDT 24 |
133367629769 ps |
| T861 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2337703427 |
|
|
Jul 23 06:10:21 PM PDT 24 |
Jul 23 06:15:35 PM PDT 24 |
4854543415 ps |
| T862 |
/workspace/coverage/default/30.sram_ctrl_regwen.2843389460 |
|
|
Jul 23 06:11:36 PM PDT 24 |
Jul 23 06:19:15 PM PDT 24 |
12916462910 ps |
| T863 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.961586592 |
|
|
Jul 23 06:11:50 PM PDT 24 |
Jul 23 06:16:22 PM PDT 24 |
9777001941 ps |
| T864 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1985076553 |
|
|
Jul 23 06:10:41 PM PDT 24 |
Jul 23 06:14:43 PM PDT 24 |
3366693176 ps |
| T865 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2511757932 |
|
|
Jul 23 06:11:53 PM PDT 24 |
Jul 23 06:14:39 PM PDT 24 |
2100198383 ps |
| T866 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1460572821 |
|
|
Jul 23 06:11:12 PM PDT 24 |
Jul 23 08:08:45 PM PDT 24 |
243472463332 ps |
| T867 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.283006384 |
|
|
Jul 23 06:11:50 PM PDT 24 |
Jul 23 06:11:55 PM PDT 24 |
2107503673 ps |
| T868 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.3703511305 |
|
|
Jul 23 06:10:52 PM PDT 24 |
Jul 23 06:12:15 PM PDT 24 |
12950930853 ps |
| T869 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3543075010 |
|
|
Jul 23 06:11:11 PM PDT 24 |
Jul 23 06:26:51 PM PDT 24 |
16667519326 ps |
| T870 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1631948236 |
|
|
Jul 23 06:11:22 PM PDT 24 |
Jul 23 07:36:23 PM PDT 24 |
241342183171 ps |
| T871 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1254012901 |
|
|
Jul 23 06:10:52 PM PDT 24 |
Jul 23 08:31:25 PM PDT 24 |
214686818988 ps |
| T872 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.385876978 |
|
|
Jul 23 06:10:26 PM PDT 24 |
Jul 23 06:16:19 PM PDT 24 |
29013376219 ps |
| T873 |
/workspace/coverage/default/30.sram_ctrl_executable.1369191904 |
|
|
Jul 23 06:11:37 PM PDT 24 |
Jul 23 06:28:25 PM PDT 24 |
24149841348 ps |
| T874 |
/workspace/coverage/default/11.sram_ctrl_regwen.2719804815 |
|
|
Jul 23 06:10:40 PM PDT 24 |
Jul 23 06:21:16 PM PDT 24 |
15528519688 ps |
| T875 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.493774203 |
|
|
Jul 23 06:11:56 PM PDT 24 |
Jul 23 06:12:46 PM PDT 24 |
30663478512 ps |
| T876 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.4019372777 |
|
|
Jul 23 06:12:11 PM PDT 24 |
Jul 23 06:19:25 PM PDT 24 |
23629507583 ps |
| T877 |
/workspace/coverage/default/48.sram_ctrl_partial_access.561534009 |
|
|
Jul 23 06:13:46 PM PDT 24 |
Jul 23 06:13:53 PM PDT 24 |
3904148778 ps |
| T878 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1601005482 |
|
|
Jul 23 06:12:53 PM PDT 24 |
Jul 23 06:41:43 PM PDT 24 |
79740015456 ps |
| T879 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1762963386 |
|
|
Jul 23 06:12:04 PM PDT 24 |
Jul 23 06:18:52 PM PDT 24 |
11203268319 ps |
| T880 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1346703461 |
|
|
Jul 23 06:11:13 PM PDT 24 |
Jul 23 06:31:57 PM PDT 24 |
24846850379 ps |
| T881 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3114777307 |
|
|
Jul 23 06:12:09 PM PDT 24 |
Jul 23 06:14:09 PM PDT 24 |
10148572328 ps |
| T882 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2280645916 |
|
|
Jul 23 06:10:34 PM PDT 24 |
Jul 23 06:28:45 PM PDT 24 |
283925597378 ps |
| T102 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.630891873 |
|
|
Jul 23 06:11:39 PM PDT 24 |
Jul 23 06:13:06 PM PDT 24 |
33817049578 ps |
| T883 |
/workspace/coverage/default/30.sram_ctrl_stress_all.1644141239 |
|
|
Jul 23 06:11:36 PM PDT 24 |
Jul 23 06:44:07 PM PDT 24 |
79889624690 ps |
| T884 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2616514990 |
|
|
Jul 23 06:11:39 PM PDT 24 |
Jul 23 06:17:27 PM PDT 24 |
55687896250 ps |
| T885 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.2431801028 |
|
|
Jul 23 06:11:46 PM PDT 24 |
Jul 23 06:13:15 PM PDT 24 |
11599422464 ps |
| T886 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1790439036 |
|
|
Jul 23 06:13:53 PM PDT 24 |
Jul 23 06:16:53 PM PDT 24 |
9795940348 ps |
| T887 |
/workspace/coverage/default/14.sram_ctrl_regwen.2470993173 |
|
|
Jul 23 06:10:43 PM PDT 24 |
Jul 23 06:17:08 PM PDT 24 |
6162635088 ps |
| T888 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3043866729 |
|
|
Jul 23 06:11:39 PM PDT 24 |
Jul 23 06:17:27 PM PDT 24 |
19298093093 ps |
| T889 |
/workspace/coverage/default/25.sram_ctrl_smoke.3172915670 |
|
|
Jul 23 06:11:22 PM PDT 24 |
Jul 23 06:11:44 PM PDT 24 |
1348289004 ps |
| T890 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2511255699 |
|
|
Jul 23 06:11:23 PM PDT 24 |
Jul 23 06:12:12 PM PDT 24 |
24186438959 ps |
| T891 |
/workspace/coverage/default/37.sram_ctrl_bijection.3808686245 |
|
|
Jul 23 06:12:15 PM PDT 24 |
Jul 23 06:38:05 PM PDT 24 |
88795706564 ps |
| T892 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3406400653 |
|
|
Jul 23 06:11:11 PM PDT 24 |
Jul 23 06:17:37 PM PDT 24 |
6160530889 ps |
| T893 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2067316423 |
|
|
Jul 23 06:10:55 PM PDT 24 |
Jul 23 06:12:46 PM PDT 24 |
39563483972 ps |
| T894 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2500894470 |
|
|
Jul 23 06:12:46 PM PDT 24 |
Jul 23 06:13:23 PM PDT 24 |
818114025 ps |
| T895 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1374610460 |
|
|
Jul 23 06:12:17 PM PDT 24 |
Jul 23 06:30:30 PM PDT 24 |
26714216383 ps |
| T896 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3433745001 |
|
|
Jul 23 06:10:42 PM PDT 24 |
Jul 23 06:10:48 PM PDT 24 |
53062875 ps |
| T897 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.4024181021 |
|
|
Jul 23 06:11:30 PM PDT 24 |
Jul 23 06:11:46 PM PDT 24 |
1160970938 ps |
| T898 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.2504220356 |
|
|
Jul 23 06:11:03 PM PDT 24 |
Jul 23 06:11:56 PM PDT 24 |
22350757602 ps |
| T899 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.2319662751 |
|
|
Jul 23 06:11:16 PM PDT 24 |
Jul 23 06:25:11 PM PDT 24 |
14793383276 ps |
| T900 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2106513178 |
|
|
Jul 23 06:10:25 PM PDT 24 |
Jul 23 06:10:38 PM PDT 24 |
693539268 ps |
| T901 |
/workspace/coverage/default/28.sram_ctrl_partial_access.927914526 |
|
|
Jul 23 06:11:30 PM PDT 24 |
Jul 23 06:11:40 PM PDT 24 |
1987049593 ps |
| T902 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2918554428 |
|
|
Jul 23 06:10:27 PM PDT 24 |
Jul 23 06:55:01 PM PDT 24 |
48917227638 ps |
| T903 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.1115083178 |
|
|
Jul 23 06:10:42 PM PDT 24 |
Jul 23 06:11:00 PM PDT 24 |
3441838973 ps |
| T904 |
/workspace/coverage/default/11.sram_ctrl_partial_access.905824139 |
|
|
Jul 23 06:10:48 PM PDT 24 |
Jul 23 06:11:01 PM PDT 24 |
443400052 ps |
| T905 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.883419533 |
|
|
Jul 23 06:11:24 PM PDT 24 |
Jul 23 06:12:14 PM PDT 24 |
75739934850 ps |
| T906 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2868624291 |
|
|
Jul 23 06:11:15 PM PDT 24 |
Jul 23 06:11:28 PM PDT 24 |
3121378566 ps |
| T907 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.769235431 |
|
|
Jul 23 06:11:03 PM PDT 24 |
Jul 23 06:16:17 PM PDT 24 |
26680560215 ps |
| T908 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.4045499723 |
|
|
Jul 23 06:10:59 PM PDT 24 |
Jul 23 06:41:51 PM PDT 24 |
92976001155 ps |
| T909 |
/workspace/coverage/default/39.sram_ctrl_regwen.1330079766 |
|
|
Jul 23 06:12:25 PM PDT 24 |
Jul 23 06:20:43 PM PDT 24 |
30981554285 ps |
| T910 |
/workspace/coverage/default/30.sram_ctrl_partial_access.1090934649 |
|
|
Jul 23 06:11:38 PM PDT 24 |
Jul 23 06:11:46 PM PDT 24 |
2774722504 ps |
| T911 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2121165398 |
|
|
Jul 23 06:10:45 PM PDT 24 |
Jul 23 06:11:10 PM PDT 24 |
896478817 ps |
| T912 |
/workspace/coverage/default/10.sram_ctrl_executable.748270567 |
|
|
Jul 23 06:10:35 PM PDT 24 |
Jul 23 06:11:48 PM PDT 24 |
3482714876 ps |
| T913 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.4222679214 |
|
|
Jul 23 06:10:55 PM PDT 24 |
Jul 23 06:18:27 PM PDT 24 |
36879745512 ps |
| T914 |
/workspace/coverage/default/41.sram_ctrl_smoke.1521480108 |
|
|
Jul 23 06:12:35 PM PDT 24 |
Jul 23 06:13:03 PM PDT 24 |
12283187620 ps |
| T915 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2347776391 |
|
|
Jul 23 06:11:17 PM PDT 24 |
Jul 23 06:16:33 PM PDT 24 |
14543357021 ps |
| T916 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2436497284 |
|
|
Jul 23 06:13:26 PM PDT 24 |
Jul 23 06:15:09 PM PDT 24 |
57539391229 ps |
| T917 |
/workspace/coverage/default/31.sram_ctrl_regwen.1556704133 |
|
|
Jul 23 06:11:40 PM PDT 24 |
Jul 23 06:30:54 PM PDT 24 |
60711572188 ps |
| T918 |
/workspace/coverage/default/24.sram_ctrl_executable.3973873546 |
|
|
Jul 23 06:11:14 PM PDT 24 |
Jul 23 06:26:52 PM PDT 24 |
39638082818 ps |
| T919 |
/workspace/coverage/default/7.sram_ctrl_executable.458971199 |
|
|
Jul 23 06:10:30 PM PDT 24 |
Jul 23 06:11:15 PM PDT 24 |
2504818768 ps |
| T920 |
/workspace/coverage/default/0.sram_ctrl_smoke.1693401392 |
|
|
Jul 23 06:10:19 PM PDT 24 |
Jul 23 06:10:32 PM PDT 24 |
455942196 ps |
| T921 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.1513129566 |
|
|
Jul 23 06:11:40 PM PDT 24 |
Jul 23 06:13:22 PM PDT 24 |
2148459168 ps |
| T922 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2670260977 |
|
|
Jul 23 06:10:37 PM PDT 24 |
Jul 23 06:19:39 PM PDT 24 |
8387691820 ps |
| T923 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1469600644 |
|
|
Jul 23 06:10:38 PM PDT 24 |
Jul 23 06:52:08 PM PDT 24 |
81172440169 ps |
| T924 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1613225706 |
|
|
Jul 23 06:13:49 PM PDT 24 |
Jul 23 07:12:19 PM PDT 24 |
384679834648 ps |
| T925 |
/workspace/coverage/default/39.sram_ctrl_stress_all.1352860676 |
|
|
Jul 23 06:12:28 PM PDT 24 |
Jul 23 07:37:46 PM PDT 24 |
455467005089 ps |
| T926 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.916477457 |
|
|
Jul 23 06:11:35 PM PDT 24 |
Jul 23 06:12:01 PM PDT 24 |
3553735468 ps |
| T927 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2973804994 |
|
|
Jul 23 06:10:51 PM PDT 24 |
Jul 23 06:11:07 PM PDT 24 |
700480408 ps |
| T928 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3311319218 |
|
|
Jul 23 06:10:31 PM PDT 24 |
Jul 23 06:12:08 PM PDT 24 |
3156297260 ps |
| T929 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3015213909 |
|
|
Jul 23 06:11:04 PM PDT 24 |
Jul 23 06:17:23 PM PDT 24 |
5046539052 ps |
| T930 |
/workspace/coverage/default/41.sram_ctrl_executable.704391572 |
|
|
Jul 23 06:12:46 PM PDT 24 |
Jul 23 06:43:22 PM PDT 24 |
122862660778 ps |
| T931 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2963871988 |
|
|
Jul 23 06:11:09 PM PDT 24 |
Jul 23 06:16:22 PM PDT 24 |
13810834015 ps |
| T932 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.1076589949 |
|
|
Jul 23 06:13:36 PM PDT 24 |
Jul 23 06:18:06 PM PDT 24 |
30291124662 ps |
| T933 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3697713728 |
|
|
Jul 23 06:10:53 PM PDT 24 |
Jul 23 06:18:16 PM PDT 24 |
230084377222 ps |
| T934 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2859589493 |
|
|
Jul 23 06:10:33 PM PDT 24 |
Jul 23 06:10:50 PM PDT 24 |
550998723 ps |
| T935 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3607925104 |
|
|
Jul 23 06:12:26 PM PDT 24 |
Jul 23 06:15:54 PM PDT 24 |
22987493324 ps |
| T936 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.2344901012 |
|
|
Jul 23 06:12:28 PM PDT 24 |
Jul 23 06:12:32 PM PDT 24 |
364053732 ps |
| T937 |
/workspace/coverage/default/12.sram_ctrl_smoke.1782813370 |
|
|
Jul 23 06:10:53 PM PDT 24 |
Jul 23 06:11:10 PM PDT 24 |
1066521798 ps |
| T938 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1356475129 |
|
|
Jul 23 06:12:52 PM PDT 24 |
Jul 23 06:27:38 PM PDT 24 |
56917952300 ps |
| T939 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.72745661 |
|
|
Jul 23 06:10:45 PM PDT 24 |
Jul 23 06:15:10 PM PDT 24 |
4051121429 ps |
| T940 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.3820143311 |
|
|
Jul 23 06:11:07 PM PDT 24 |
Jul 23 06:15:28 PM PDT 24 |
9733023536 ps |
| T941 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.2911344096 |
|
|
Jul 23 06:11:01 PM PDT 24 |
Jul 23 06:13:28 PM PDT 24 |
6117448331 ps |
| T942 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.4041120959 |
|
|
Jul 23 06:12:48 PM PDT 24 |
Jul 23 06:13:07 PM PDT 24 |
2564345028 ps |
| T943 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.514310717 |
|
|
Jul 23 06:11:18 PM PDT 24 |
Jul 23 06:20:41 PM PDT 24 |
53488602887 ps |
| T944 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1667095707 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:48 PM PDT 24 |
142958217 ps |
| T66 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2496188234 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:44 PM PDT 24 |
159032173 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1084887789 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:50 PM PDT 24 |
362156026 ps |
| T946 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.348706435 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:54 PM PDT 24 |
49766457 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1079210774 |
|
|
Jul 23 06:59:39 PM PDT 24 |
Jul 23 06:59:43 PM PDT 24 |
247879395 ps |
| T67 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2831024541 |
|
|
Jul 23 06:59:47 PM PDT 24 |
Jul 23 06:59:58 PM PDT 24 |
680282928 ps |
| T70 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2356960942 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:46 PM PDT 24 |
16088553 ps |
| T108 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2682779892 |
|
|
Jul 23 06:59:36 PM PDT 24 |
Jul 23 06:59:38 PM PDT 24 |
33814692 ps |
| T116 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.485087463 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:47 PM PDT 24 |
13550101 ps |
| T79 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2367127912 |
|
|
Jul 23 06:59:47 PM PDT 24 |
Jul 23 06:59:56 PM PDT 24 |
121263030 ps |
| T68 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3171159211 |
|
|
Jul 23 06:59:43 PM PDT 24 |
Jul 23 06:59:51 PM PDT 24 |
135421637 ps |
| T948 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3195952422 |
|
|
Jul 23 06:59:46 PM PDT 24 |
Jul 23 06:59:57 PM PDT 24 |
1365665705 ps |
| T949 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3608918833 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:46 PM PDT 24 |
17710047 ps |
| T80 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1783435840 |
|
|
Jul 23 06:59:43 PM PDT 24 |
Jul 23 06:59:50 PM PDT 24 |
82888668 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.653739191 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
28841125 ps |
| T951 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1374675674 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:48 PM PDT 24 |
1465493916 ps |
| T109 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3244855029 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
24580218 ps |
| T81 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.914426473 |
|
|
Jul 23 06:59:46 PM PDT 24 |
Jul 23 07:00:19 PM PDT 24 |
4200500802 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4004122086 |
|
|
Jul 23 06:59:25 PM PDT 24 |
Jul 23 06:59:30 PM PDT 24 |
274440401 ps |
| T82 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3041096538 |
|
|
Jul 23 06:59:43 PM PDT 24 |
Jul 23 07:00:13 PM PDT 24 |
3802677077 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2386396543 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:55 PM PDT 24 |
86839477 ps |
| T84 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.977842317 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:47 PM PDT 24 |
12804570 ps |
| T85 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2731788961 |
|
|
Jul 23 06:59:46 PM PDT 24 |
Jul 23 06:59:54 PM PDT 24 |
21361682 ps |
| T134 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1114922352 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:47 PM PDT 24 |
2033595934 ps |
| T86 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3209103381 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:46 PM PDT 24 |
17045238 ps |
| T110 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.768908006 |
|
|
Jul 23 06:59:44 PM PDT 24 |
Jul 23 06:59:52 PM PDT 24 |
102835849 ps |
| T87 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3281257269 |
|
|
Jul 23 06:59:39 PM PDT 24 |
Jul 23 06:59:41 PM PDT 24 |
24155537 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1974774317 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:56 PM PDT 24 |
1391512360 ps |
| T954 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1991478050 |
|
|
Jul 23 06:59:37 PM PDT 24 |
Jul 23 06:59:40 PM PDT 24 |
135550685 ps |
| T89 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.505470347 |
|
|
Jul 23 06:59:49 PM PDT 24 |
Jul 23 07:00:52 PM PDT 24 |
41516769595 ps |
| T955 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.367735829 |
|
|
Jul 23 06:59:46 PM PDT 24 |
Jul 23 06:59:55 PM PDT 24 |
18514141 ps |
| T137 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2753476688 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
258778622 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1432281844 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:48 PM PDT 24 |
1414459683 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2469096833 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:54 PM PDT 24 |
54843032 ps |
| T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2252954434 |
|
|
Jul 23 06:59:36 PM PDT 24 |
Jul 23 07:00:34 PM PDT 24 |
100629502479 ps |
| T958 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2065138063 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:55 PM PDT 24 |
6973282590 ps |
| T138 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1016820844 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:48 PM PDT 24 |
1661728641 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1090671631 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:51 PM PDT 24 |
369379944 ps |
| T91 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3748873027 |
|
|
Jul 23 06:59:31 PM PDT 24 |
Jul 23 07:00:01 PM PDT 24 |
14197567562 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2100195900 |
|
|
Jul 23 06:59:33 PM PDT 24 |
Jul 23 06:59:35 PM PDT 24 |
118190650 ps |
| T139 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.994969159 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:54 PM PDT 24 |
308193922 ps |
| T960 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4002515730 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:47 PM PDT 24 |
29151600 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2167444945 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:52 PM PDT 24 |
176646209 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1216272601 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 07:00:14 PM PDT 24 |
3701407322 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2622627668 |
|
|
Jul 23 06:59:25 PM PDT 24 |
Jul 23 06:59:29 PM PDT 24 |
314084029 ps |
| T963 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3705638283 |
|
|
Jul 23 06:59:44 PM PDT 24 |
Jul 23 06:59:55 PM PDT 24 |
148025179 ps |
| T964 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3608219657 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:44 PM PDT 24 |
185550244 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.260039381 |
|
|
Jul 23 06:59:35 PM PDT 24 |
Jul 23 07:00:04 PM PDT 24 |
4053724481 ps |
| T966 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.661861445 |
|
|
Jul 23 06:59:47 PM PDT 24 |
Jul 23 06:59:56 PM PDT 24 |
28381381 ps |
| T143 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1096995091 |
|
|
Jul 23 06:59:46 PM PDT 24 |
Jul 23 06:59:55 PM PDT 24 |
168517656 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2032706347 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:53 PM PDT 24 |
22437567 ps |
| T968 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2925530468 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:53 PM PDT 24 |
22035711 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4174507951 |
|
|
Jul 23 06:59:32 PM PDT 24 |
Jul 23 06:59:36 PM PDT 24 |
140395732 ps |
| T94 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1400284693 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 07:00:20 PM PDT 24 |
7281282005 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2521338307 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 07:00:31 PM PDT 24 |
7531435177 ps |
| T970 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1717251633 |
|
|
Jul 23 06:59:49 PM PDT 24 |
Jul 23 06:59:57 PM PDT 24 |
58151333 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3344370151 |
|
|
Jul 23 06:59:39 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
125138672 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2494257470 |
|
|
Jul 23 06:59:39 PM PDT 24 |
Jul 23 06:59:42 PM PDT 24 |
29364937 ps |
| T973 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1893234008 |
|
|
Jul 23 06:59:33 PM PDT 24 |
Jul 23 06:59:39 PM PDT 24 |
256040867 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1234485420 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:55 PM PDT 24 |
81462090 ps |
| T135 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4103100328 |
|
|
Jul 23 06:59:50 PM PDT 24 |
Jul 23 07:00:00 PM PDT 24 |
244384954 ps |
| T975 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.250168125 |
|
|
Jul 23 06:59:36 PM PDT 24 |
Jul 23 06:59:39 PM PDT 24 |
144655743 ps |
| T141 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1207541048 |
|
|
Jul 23 06:59:49 PM PDT 24 |
Jul 23 06:59:59 PM PDT 24 |
198359796 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1500481130 |
|
|
Jul 23 06:59:36 PM PDT 24 |
Jul 23 07:00:06 PM PDT 24 |
14382907871 ps |
| T977 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.293584261 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:54 PM PDT 24 |
152926054 ps |
| T978 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.166074178 |
|
|
Jul 23 06:59:29 PM PDT 24 |
Jul 23 06:59:34 PM PDT 24 |
1316830292 ps |
| T96 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3881620408 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 07:00:46 PM PDT 24 |
29365877694 ps |
| T136 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.497176549 |
|
|
Jul 23 06:59:37 PM PDT 24 |
Jul 23 06:59:39 PM PDT 24 |
141766141 ps |
| T104 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2340853350 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:46 PM PDT 24 |
36500300 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1984349845 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:53 PM PDT 24 |
47806835 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1720382931 |
|
|
Jul 23 06:59:34 PM PDT 24 |
Jul 23 06:59:36 PM PDT 24 |
211226219 ps |
| T140 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2732906708 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
159973449 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4203342806 |
|
|
Jul 23 06:59:44 PM PDT 24 |
Jul 23 06:59:52 PM PDT 24 |
59177364 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1139587725 |
|
|
Jul 23 06:59:39 PM PDT 24 |
Jul 23 06:59:41 PM PDT 24 |
26737180 ps |
| T983 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.572561255 |
|
|
Jul 23 06:59:43 PM PDT 24 |
Jul 23 06:59:50 PM PDT 24 |
43684466 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.8398135 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:44 PM PDT 24 |
177554156 ps |
| T984 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4210000325 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 06:59:50 PM PDT 24 |
415891004 ps |
| T106 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3716354988 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:54 PM PDT 24 |
26128708 ps |
| T107 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.147837236 |
|
|
Jul 23 06:59:42 PM PDT 24 |
Jul 23 07:00:15 PM PDT 24 |
7693175428 ps |
| T985 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1744416907 |
|
|
Jul 23 06:59:47 PM PDT 24 |
Jul 23 06:59:59 PM PDT 24 |
1573781645 ps |
| T986 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1687944624 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 07:00:21 PM PDT 24 |
3709419582 ps |
| T987 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3617757759 |
|
|
Jul 23 06:59:45 PM PDT 24 |
Jul 23 06:59:53 PM PDT 24 |
22347349 ps |
| T988 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2176337726 |
|
|
Jul 23 06:59:44 PM PDT 24 |
Jul 23 07:00:54 PM PDT 24 |
78347574870 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1286836404 |
|
|
Jul 23 06:59:32 PM PDT 24 |
Jul 23 06:59:37 PM PDT 24 |
375462249 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.264094177 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:46 PM PDT 24 |
408602801 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.477004834 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
365913052 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3097954974 |
|
|
Jul 23 06:59:35 PM PDT 24 |
Jul 23 06:59:40 PM PDT 24 |
356185119 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4057900930 |
|
|
Jul 23 06:59:44 PM PDT 24 |
Jul 23 06:59:53 PM PDT 24 |
131965577 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4108206448 |
|
|
Jul 23 06:59:46 PM PDT 24 |
Jul 23 06:59:54 PM PDT 24 |
61575053 ps |
| T995 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1420534722 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
173868010 ps |
| T996 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.775064467 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
220788402 ps |
| T997 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2628105039 |
|
|
Jul 23 06:59:40 PM PDT 24 |
Jul 23 06:59:44 PM PDT 24 |
268814360 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1641220820 |
|
|
Jul 23 06:59:28 PM PDT 24 |
Jul 23 06:59:56 PM PDT 24 |
3859792337 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4215261120 |
|
|
Jul 23 06:59:44 PM PDT 24 |
Jul 23 06:59:51 PM PDT 24 |
81069026 ps |
| T103 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.30304044 |
|
|
Jul 23 06:59:33 PM PDT 24 |
Jul 23 06:59:36 PM PDT 24 |
17657476 ps |
| T1000 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4193786582 |
|
|
Jul 23 06:59:37 PM PDT 24 |
Jul 23 06:59:39 PM PDT 24 |
37006447 ps |
| T1001 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2858925792 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:47 PM PDT 24 |
366932802 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.817723186 |
|
|
Jul 23 06:59:41 PM PDT 24 |
Jul 23 06:59:45 PM PDT 24 |
13196643 ps |