Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16208024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

163090748

1

T2

2732

T3

122917

T4

5238

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88292567	1			T2	1507		T3	67509		T4	2884
values[0x0]	43890483	1			T2	715		T3	32749		T4	1398
values[0x1]	47115722	1			T2	760		T3	34978		T4	1447

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8234254	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

171064518

1

T2

2853

T3

129052

T4

5473

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	590409	1			T2	10		T3	576		T4	26
valid_sources[0x01]	572756	1			T2	5		T3	464		T4	25
valid_sources[0x02]	613177	1			T2	19		T3	545		T4	32
valid_sources[0x03]	625114	1			T2	9		T3	550		T4	37
valid_sources[0x04]	577519	1			T2	17		T3	507		T4	37
valid_sources[0x05]	557645	1			T2	10		T3	540		T4	26
valid_sources[0x06]	581052	1			T2	14		T3	552		T4	19
valid_sources[0x07]	591421	1			T2	12		T3	531		T4	31
valid_sources[0x08]	762375	1			T2	6		T3	591		T4	11
valid_sources[0x09]	1743855	1			T2	10		T3	479		T4	16
valid_sources[0x0a]	576327	1			T2	13		T3	516		T4	15
valid_sources[0x0b]	598280	1			T2	11		T3	559		T4	36
valid_sources[0x0c]	577561	1			T2	15		T3	577		T4	27
valid_sources[0x0d]	562633	1			T2	15		T3	475		T4	10
valid_sources[0x0e]	663335	1			T2	19		T3	602		T4	21
valid_sources[0x0f]	591435	1			T2	6		T3	576		T4	8
valid_sources[0x10]	554965	1			T2	12		T3	480		T4	41
valid_sources[0x11]	1930229	1			T2	10		T3	518		T4	16
valid_sources[0x12]	585187	1			T2	5		T3	598		T4	30
valid_sources[0x13]	556491	1			T2	12		T3	521		T4	13
valid_sources[0x14]	652819	1			T2	12		T3	552		T4	19
valid_sources[0x15]	584873	1			T2	7		T3	548		T4	13
valid_sources[0x16]	623649	1			T2	6		T3	557		T4	30
valid_sources[0x17]	566442	1			T2	8		T3	664		T4	32
valid_sources[0x18]	572755	1			T2	9		T3	470		T4	17
valid_sources[0x19]	564622	1			T2	8		T3	477		T4	16
valid_sources[0x1a]	566010	1			T2	8		T3	482		T4	38
valid_sources[0x1b]	585638	1			T2	10		T3	546		T4	12
valid_sources[0x1c]	580625	1			T2	6		T3	500		T4	21
valid_sources[0x1d]	599017	1			T2	11		T3	515		T4	20
valid_sources[0x1e]	580573	1			T2	10		T3	526		T4	12
valid_sources[0x1f]	564401	1			T2	8		T3	548		T4	26
valid_sources[0x20]	557258	1			T2	12		T3	466		T4	10
valid_sources[0x21]	597707	1			T2	12		T3	499		T4	16
valid_sources[0x22]	557107	1			T2	8		T3	510		T4	26
valid_sources[0x23]	555276	1			T2	12		T3	517		T4	14
valid_sources[0x24]	557891	1			T2	13		T3	504		T4	35
valid_sources[0x25]	573397	1			T2	10		T3	486		T4	18
valid_sources[0x26]	637935	1			T2	10		T3	508		T4	34
valid_sources[0x27]	630087	1			T2	12		T3	464		T4	29
valid_sources[0x28]	605884	1			T2	9		T3	574		T4	30
valid_sources[0x29]	560648	1			T2	7		T3	514		T4	42
valid_sources[0x2a]	621508	1			T2	13		T3	508		T4	11
valid_sources[0x2b]	568953	1			T2	10		T3	538		T4	22
valid_sources[0x2c]	576769	1			T2	7		T3	537		T4	32
valid_sources[0x2d]	589145	1			T2	6		T3	534		T4	19
valid_sources[0x2e]	595371	1			T2	7		T3	563		T4	25
valid_sources[0x2f]	775862	1			T2	12		T3	585		T4	25
valid_sources[0x30]	566647	1			T2	17		T3	507		T4	21
valid_sources[0x31]	613346	1			T2	10		T3	484		T4	25
valid_sources[0x32]	560272	1			T2	7		T3	531		T4	34
valid_sources[0x33]	568216	1			T2	12		T3	569		T4	24
valid_sources[0x34]	558066	1			T2	12		T3	521		T4	32
valid_sources[0x35]	566555	1			T2	9		T3	453		T4	32
valid_sources[0x36]	598687	1			T2	14		T3	588		T4	18
valid_sources[0x37]	551295	1			T2	9		T3	523		T4	20
valid_sources[0x38]	631396	1			T2	15		T3	516		T4	33
valid_sources[0x39]	635788	1			T2	16		T3	563		T4	22
valid_sources[0x3a]	615889	1			T2	8		T3	499		T4	28
valid_sources[0x3b]	587604	1			T2	8		T3	574		T4	21
valid_sources[0x3c]	634008	1			T2	13		T3	595		T4	16
valid_sources[0x3d]	618918	1			T2	21		T3	530		T4	15
valid_sources[0x3e]	609425	1			T2	21		T3	480		T4	19
valid_sources[0x3f]	577561	1			T2	5		T3	492		T4	5
valid_sources[0x40]	799432	1			T2	12		T3	472		T4	34
valid_sources[0x41]	561461	1			T2	17		T3	481		T4	28
valid_sources[0x42]	586654	1			T2	10		T3	532		T4	18
valid_sources[0x43]	564988	1			T2	13		T3	564		T4	7
valid_sources[0x44]	2112519	1			T2	17		T3	465		T4	27
valid_sources[0x45]	612063	1			T2	7		T3	496		T4	16
valid_sources[0x46]	592034	1			T2	11		T3	538		T4	24
valid_sources[0x47]	618052	1			T2	6		T3	579		T4	20
valid_sources[0x48]	604537	1			T2	8		T3	528		T4	19
valid_sources[0x49]	1299379	1			T2	12		T3	583		T4	11
valid_sources[0x4a]	651403	1			T2	10		T3	527		T4	21
valid_sources[0x4b]	618499	1			T2	13		T3	511		T4	16
valid_sources[0x4c]	570511	1			T2	15		T3	536		T4	27
valid_sources[0x4d]	582810	1			T2	9		T3	586		T4	13
valid_sources[0x4e]	1659382	1			T2	20		T3	515		T4	22
valid_sources[0x4f]	585838	1			T2	9		T3	459		T4	8
valid_sources[0x50]	657384	1			T2	10		T3	607		T4	42
valid_sources[0x51]	582974	1			T2	15		T3	494		T4	11
valid_sources[0x52]	576066	1			T2	12		T3	556		T4	34
valid_sources[0x53]	630482	1			T2	14		T3	548		T4	17
valid_sources[0x54]	586779	1			T2	18		T3	545		T4	38
valid_sources[0x55]	551701	1			T2	20		T3	640		T4	21
valid_sources[0x56]	552473	1			T2	9		T3	495		T4	16
valid_sources[0x57]	640131	1			T2	10		T3	481		T4	26
valid_sources[0x58]	555778	1			T2	13		T3	537		T4	16
valid_sources[0x59]	2047809	1			T2	11		T3	539		T4	47
valid_sources[0x5a]	608140	1			T2	13		T3	411		T4	14
valid_sources[0x5b]	603813	1			T2	8		T3	506		T4	24
valid_sources[0x5c]	560914	1			T2	11		T3	508		T4	37
valid_sources[0x5d]	592454	1			T2	8		T3	607		T4	22
valid_sources[0x5e]	587858	1			T2	9		T3	480		T4	33
valid_sources[0x5f]	554212	1			T2	21		T3	485		T4	24
valid_sources[0x60]	557182	1			T2	7		T3	468		T4	41
valid_sources[0x61]	601549	1			T2	5		T3	542		T4	26
valid_sources[0x62]	1804952	1			T2	21		T3	576		T4	28
valid_sources[0x63]	553915	1			T2	19		T3	530		T4	8
valid_sources[0x64]	568200	1			T2	10		T3	563		T4	29
valid_sources[0x65]	571965	1			T2	8		T3	548		T4	20
valid_sources[0x66]	595394	1			T2	7		T3	609		T4	13
valid_sources[0x67]	630384	1			T2	12		T3	582		T4	22
valid_sources[0x68]	583330	1			T2	11		T3	495		T4	25
valid_sources[0x69]	576322	1			T2	7		T3	538		T4	9
valid_sources[0x6a]	581083	1			T2	8		T3	585		T4	23
valid_sources[0x6b]	642998	1			T2	18		T3	499		T4	20
valid_sources[0x6c]	561438	1			T2	17		T3	538		T4	30
valid_sources[0x6d]	644662	1			T2	12		T3	502		T4	16
valid_sources[0x6e]	2679594	1			T2	9		T3	521		T4	27
valid_sources[0x6f]	604658	1			T2	10		T3	504		T4	39
valid_sources[0x70]	591918	1			T2	11		T3	621		T4	14
valid_sources[0x71]	603889	1			T2	17		T3	521		T4	22
valid_sources[0x72]	977631	1			T2	11		T3	511		T4	23
valid_sources[0x73]	566386	1			T2	15		T3	546		T4	8
valid_sources[0x74]	584796	1			T2	12		T3	489		T4	24
valid_sources[0x75]	574932	1			T2	13		T3	546		T4	17
valid_sources[0x76]	594755	1			T2	11		T3	469		T4	16
valid_sources[0x77]	602396	1			T2	14		T3	541		T4	25
valid_sources[0x78]	2034861	1			T2	13		T3	529		T4	13
valid_sources[0x79]	577269	1			T2	14		T3	543		T4	23
valid_sources[0x7a]	635376	1			T2	12		T3	530		T4	26
valid_sources[0x7b]	768615	1			T2	8		T3	529		T4	11
valid_sources[0x7c]	615515	1			T2	12		T3	504		T4	25
valid_sources[0x7d]	2646719	1			T2	13		T3	493		T4	39
valid_sources[0x7e]	574963	1			T2	18		T3	572		T4	19
valid_sources[0x7f]	553311	1			T2	8		T3	516		T4	33
valid_sources[0x80]	571664	1			T2	5		T3	564		T4	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80150948

1

T2

1387

T3

61390

T4

2645

values[0x0]

all_enables

biggest_size

41471068

1

T2

674

T3

30795

T4

1316

values[0x1]

all_enables

biggest_size

41468732

1

T2

671

T3

30732

T4

1277

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

137343

1

T1

4

T2

20

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50324	1			T2	25		T7	20		T12	16
values[0x0]	63664	1			T1	8		T2	16		T3	16
values[0x1]	68159	1			T1	3		T2	15		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35150	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146997

1

T1

4

T2

23

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	549	1			T22	2		T23	4		T5	1
valid_sources[0x01]	572	1			T12	2		T22	3		T23	8
valid_sources[0x02]	553	1			T3	1		T22	9		T13	3
valid_sources[0x03]	803	1			T142	1		T24	7		T33	1
valid_sources[0x04]	796	1			T22	1		T23	5		T5	1
valid_sources[0x05]	730	1			T2	2		T22	2		T24	4
valid_sources[0x06]	828	1			T22	4		T5	3		T24	4
valid_sources[0x07]	946	1			T22	5		T143	1		T24	10
valid_sources[0x08]	728	1			T12	10		T22	5		T23	3
valid_sources[0x09]	522	1			T22	2		T23	19		T5	2
valid_sources[0x0a]	745	1			T22	6		T23	7		T5	3
valid_sources[0x0b]	564	1			T2	2		T56	1		T22	2
valid_sources[0x0c]	546	1			T12	2		T22	3		T24	10
valid_sources[0x0d]	657	1			T22	3		T23	1		T24	11
valid_sources[0x0e]	511	1			T22	1		T24	4		T38	3
valid_sources[0x0f]	651	1			T2	2		T12	1		T22	2
valid_sources[0x10]	627	1			T12	2		T22	1		T68	2
valid_sources[0x11]	770	1			T22	9		T23	7		T5	1
valid_sources[0x12]	730	1			T2	1		T18	2		T22	2
valid_sources[0x13]	551	1			T2	1		T22	2		T23	14
valid_sources[0x14]	523	1			T22	3		T23	1		T5	4
valid_sources[0x15]	720	1			T22	1		T5	2		T24	2
valid_sources[0x16]	649	1			T54	1		T22	3		T23	10
valid_sources[0x17]	1091	1			T22	2		T5	1		T24	5
valid_sources[0x18]	594	1			T22	2		T23	16		T5	4
valid_sources[0x19]	753	1			T22	4		T5	1		T24	8
valid_sources[0x1a]	471	1			T22	2		T5	3		T24	5
valid_sources[0x1b]	934	1			T22	2		T23	1		T24	3
valid_sources[0x1c]	740	1			T2	1		T22	4		T24	10
valid_sources[0x1d]	586	1			T22	1		T5	2		T24	7
valid_sources[0x1e]	607	1			T22	1		T80	6		T23	1
valid_sources[0x1f]	1013	1			T12	1		T22	4		T68	1
valid_sources[0x20]	822	1			T1	11		T3	1		T25	1
valid_sources[0x21]	1183	1			T12	3		T56	3		T22	1
valid_sources[0x22]	989	1			T41	1		T22	6		T23	1
valid_sources[0x23]	832	1			T134	1		T5	1		T24	8
valid_sources[0x24]	647	1			T3	1		T68	1		T24	8
valid_sources[0x25]	618	1			T2	3		T75	1		T115	1
valid_sources[0x26]	718	1			T19	105		T22	5		T23	2
valid_sources[0x27]	839	1			T22	5		T23	10		T24	6
valid_sources[0x28]	1254	1			T22	11		T24	5		T33	1
valid_sources[0x29]	721	1			T8	1		T22	5		T23	2
valid_sources[0x2a]	783	1			T41	1		T22	3		T24	4
valid_sources[0x2b]	1078	1			T22	3		T5	2		T142	1
valid_sources[0x2c]	872	1			T12	10		T22	6		T78	1
valid_sources[0x2d]	632	1			T22	8		T24	7		T33	1
valid_sources[0x2e]	740	1			T22	3		T68	4		T23	16
valid_sources[0x2f]	573	1			T22	3		T68	2		T5	3
valid_sources[0x30]	761	1			T22	3		T115	1		T24	6
valid_sources[0x31]	997	1			T12	1		T22	3		T134	3
valid_sources[0x32]	550	1			T2	2		T22	12		T23	11
valid_sources[0x33]	782	1			T22	5		T23	3		T144	1
valid_sources[0x34]	606	1			T2	1		T22	2		T23	1
valid_sources[0x35]	527	1			T22	4		T23	2		T5	2
valid_sources[0x36]	796	1			T22	4		T24	8		T33	2
valid_sources[0x37]	635	1			T22	9		T23	8		T5	4
valid_sources[0x38]	846	1			T12	1		T22	6		T23	5
valid_sources[0x39]	637	1			T22	3		T5	1		T24	6
valid_sources[0x3a]	633	1			T22	5		T23	7		T5	5
valid_sources[0x3b]	651	1			T18	1		T22	6		T23	14
valid_sources[0x3c]	800	1			T22	4		T23	1		T142	2
valid_sources[0x3d]	636	1			T22	2		T68	5		T23	5
valid_sources[0x3e]	703	1			T22	4		T23	10		T5	1
valid_sources[0x3f]	476	1			T22	4		T23	2		T27	1
valid_sources[0x40]	532	1			T22	3		T23	2		T24	5
valid_sources[0x41]	783	1			T22	11		T23	10		T5	1
valid_sources[0x42]	721	1			T12	4		T18	1		T22	3
valid_sources[0x43]	683	1			T2	2		T22	4		T23	13
valid_sources[0x44]	807	1			T12	4		T22	4		T78	1
valid_sources[0x45]	629	1			T3	3		T22	5		T23	11
valid_sources[0x46]	753	1			T22	3		T76	1		T77	2
valid_sources[0x47]	722	1			T22	2		T5	1		T24	4
valid_sources[0x48]	504	1			T22	1		T23	6		T24	2
valid_sources[0x49]	1002	1			T2	1		T22	5		T5	3
valid_sources[0x4a]	511	1			T12	5		T22	5		T23	2
valid_sources[0x4b]	917	1			T25	1		T22	1		T23	1
valid_sources[0x4c]	617	1			T22	2		T113	1		T23	20
valid_sources[0x4d]	711	1			T22	2		T24	5		T42	1
valid_sources[0x4e]	605	1			T12	2		T18	2		T22	1
valid_sources[0x4f]	726	1			T22	6		T23	8		T5	2
valid_sources[0x50]	727	1			T22	3		T145	1		T5	3
valid_sources[0x51]	584	1			T18	1		T22	5		T23	16
valid_sources[0x52]	743	1			T22	1		T23	1		T5	4
valid_sources[0x53]	836	1			T22	1		T23	7		T5	1
valid_sources[0x54]	778	1			T22	2		T23	1		T135	2
valid_sources[0x55]	584	1			T22	2		T23	4		T45	18
valid_sources[0x56]	862	1			T22	4		T23	5		T5	1
valid_sources[0x57]	396	1			T3	1		T22	2		T24	2
valid_sources[0x58]	847	1			T2	1		T22	4		T5	1
valid_sources[0x59]	507	1			T3	1		T5	4		T24	6
valid_sources[0x5a]	780	1			T22	1		T5	3		T24	2
valid_sources[0x5b]	689	1			T22	4		T23	31		T5	1
valid_sources[0x5c]	687	1			T22	12		T69	72		T23	4
valid_sources[0x5d]	488	1			T78	1		T23	3		T5	1
valid_sources[0x5e]	627	1			T22	4		T79	5		T23	14
valid_sources[0x5f]	785	1			T22	16		T23	3		T5	1
valid_sources[0x60]	531	1			T22	4		T24	7		T38	5
valid_sources[0x61]	1134	1			T22	8		T78	2		T23	6
valid_sources[0x62]	558	1			T12	2		T22	4		T23	4
valid_sources[0x63]	850	1			T22	4		T5	2		T24	4
valid_sources[0x64]	984	1			T3	1		T22	7		T68	1
valid_sources[0x65]	543	1			T2	2		T22	2		T23	2
valid_sources[0x66]	937	1			T22	3		T5	1		T24	7
valid_sources[0x67]	1028	1			T56	2		T22	1		T68	6
valid_sources[0x68]	528	1			T2	2		T22	6		T68	1
valid_sources[0x69]	676	1			T22	8		T23	12		T146	1
valid_sources[0x6a]	852	1			T24	5		T33	3		T38	15
valid_sources[0x6b]	572	1			T22	4		T79	1		T23	1
valid_sources[0x6c]	792	1			T22	8		T114	1		T23	5
valid_sources[0x6d]	610	1			T3	2		T22	2		T24	5
valid_sources[0x6e]	761	1			T22	2		T23	6		T5	2
valid_sources[0x6f]	742	1			T22	5		T78	1		T23	1
valid_sources[0x70]	517	1			T12	3		T22	2		T23	10
valid_sources[0x71]	521	1			T22	9		T24	5		T33	3
valid_sources[0x72]	507	1			T9	1		T12	1		T25	1
valid_sources[0x73]	652	1			T2	1		T22	4		T24	10
valid_sources[0x74]	742	1			T22	8		T23	1		T5	1
valid_sources[0x75]	918	1			T2	1		T44	134		T22	4
valid_sources[0x76]	702	1			T22	3		T23	10		T5	2
valid_sources[0x77]	605	1			T23	6		T5	1		T24	10
valid_sources[0x78]	586	1			T12	2		T56	2		T22	4
valid_sources[0x79]	529	1			T22	8		T23	1		T24	6
valid_sources[0x7a]	710	1			T22	5		T23	2		T5	1
valid_sources[0x7b]	840	1			T22	6		T23	24		T5	2
valid_sources[0x7c]	531	1			T3	1		T56	1		T5	1
valid_sources[0x7d]	509	1			T18	1		T22	4		T5	1
valid_sources[0x7e]	714	1			T12	2		T22	1		T23	1
valid_sources[0x7f]	797	1			T22	4		T23	1		T147	2
valid_sources[0x80]	604	1			T3	3		T22	1		T23	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37113

1

T2

14

T7

11

T12

6

values[0x0]

all_enables

biggest_size

51529

1

T1

3

T2

5

T3

9

values[0x1]

all_enables

biggest_size

48701

1

T1

1

T2

1

T3

6