Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 16067318 1 T2 11 T3 10944 T4 491
full_word 159873889 1 T2 173 T3 108965 T4 5238



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 175940887 1 T2 184 T3 119909 T4 5729
auto[TlIntgErrCmd] 105 1 T62 9 T63 4 T64 8
auto[TlIntgErrData] 104 1 T62 6 T63 4 T64 7
auto[TlIntgErrBoth] 111 1 T62 5 T63 2 T64 5



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 84890569 1 T2 97 T3 52182 T4 2884
auto[1] 91050638 1 T2 87 T3 67727 T4 2845



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 7865233 1 T2 4 T3 4744 T4 239
auto[TlIntgErrNone] partial auto[1] 8201784 1 T2 7 T3 6200 T4 252
auto[TlIntgErrNone] full_word auto[0] 77025187 1 T2 93 T3 47438 T4 2645
auto[TlIntgErrNone] full_word auto[1] 82848683 1 T2 80 T3 61527 T4 2593
auto[TlIntgErrCmd] partial auto[0] 47 1 T62 4 T64 5 T128 4
auto[TlIntgErrCmd] partial auto[1] 52 1 T62 4 T63 3 T64 3
auto[TlIntgErrCmd] full_word auto[0] 4 1 T63 1 T125 1 T130 1
auto[TlIntgErrCmd] full_word auto[1] 2 1 T62 1 T131 1 - -
auto[TlIntgErrData] partial auto[0] 49 1 T62 3 T63 3 T64 4
auto[TlIntgErrData] partial auto[1] 47 1 T62 2 T63 1 T64 1
auto[TlIntgErrData] full_word auto[0] 7 1 T62 1 T64 2 T128 1
auto[TlIntgErrData] full_word auto[1] 1 1 T128 1 - - - -
auto[TlIntgErrBoth] partial auto[0] 39 1 T62 4 T63 1 T64 3
auto[TlIntgErrBoth] partial auto[1] 67 1 T62 1 T63 1 T64 2
auto[TlIntgErrBoth] full_word auto[0] 3 1 T125 1 T129 1 T132 1
auto[TlIntgErrBoth] full_word auto[1] 2 1 T128 1 T133 1 - -

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