SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 58.33 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success | 0.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.readback.en | 33.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 6 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
33.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 4 | 2 | 33.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 4 | 2 | 33.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 6 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
others[0] | 0 | 1 | 1 | |
others[1] | 0 | 1 | 1 | |
others[2] | 0 | 1 | 1 | |
others[3] | 0 | 1 | 1 | |
false | 0 | 1 | 1 | |
true | 0 | 1 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 4 | 2 | 33.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
others[0] | 0 | 1 | 1 | |
others[1] | 0 | 1 | 1 | |
others[2] | 0 | 1 | 1 | |
others[3] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
false | 174 | 1 | T1 | 1 | T10 | 1 | T44 | 1 | ||||
true | 161 | 1 | T39 | 1 | T13 | 1 | T23 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 124 | 1 | T12 | 3 | T25 | 2 | T19 | 1 | ||||
others[1] | 100 | 1 | T3 | 1 | T19 | 2 | T68 | 1 | ||||
others[2] | 116 | 1 | T3 | 2 | T68 | 1 | T134 | 1 | ||||
others[3] | 190 | 1 | T7 | 1 | T12 | 3 | T19 | 2 | ||||
false | 998 | 1 | T3 | 5 | T7 | 5 | T12 | 2 | ||||
true | 1064 | 1 | T3 | 8 | T7 | 14 | T12 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 109 | 1 | T3 | 3 | T7 | 2 | T12 | 1 | ||||
others[1] | 727 | 1 | T3 | 5 | T7 | 5 | T12 | 3 | ||||
others[2] | 6239 | 1 | T1 | 1 | T2 | 26 | T3 | 5 | ||||
others[3] | 170 | 1 | T3 | 1 | T7 | 2 | T12 | 1 | ||||
false | 33 | 1 | T7 | 2 | T134 | 1 | T20 | 1 | ||||
true | 25 | 1 | T79 | 1 | T135 | 1 | T21 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |