Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	966705	1			T2	15		T3	67		T12	79
auto[1]	10476760	1			T2	4		T3	593		T4	1
auto[2]	749954	1			T2	5		T3	48		T9	1
auto[3]	10160762	1			T2	4		T3	376		T4	2

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14705488	1			T2	21		T3	776		T4	1
auto[1]	2034905	1			T2	2		T3	110		T4	1
auto[2]	2069766	1			T2	5		T3	174		T4	1
auto[3]	3544022	1			T3	24		T7	104		T9	5

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10062696

1

T2

28

T3

1084

T4

3

auto[1]

12291485

1

T10

1

T40

1

T54

46826

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	346372	1			T2	12		T3	55		T12	65
auto[0]	auto[0]	auto[1]	35774	1			T2	1		T3	3		T12	8
auto[0]	auto[0]	auto[2]	35922	1			T2	2		T3	9		T12	4
auto[0]	auto[0]	auto[3]	47296	1			T12	2		T40	355		T54	2
auto[0]	auto[1]	auto[0]	3642954	1			T2	4		T3	460		T4	1
auto[0]	auto[1]	auto[1]	381035	1			T3	78		T7	541		T9	1
auto[0]	auto[1]	auto[2]	393109	1			T3	46		T7	574		T10	1502
auto[0]	auto[1]	auto[3]	323890	1			T3	9		T7	68		T9	3
auto[0]	auto[2]	auto[0]	252144	1			T2	4		T40	12		T41	604
auto[0]	auto[2]	auto[1]	28796	1			T2	1		T40	77		T41	62
auto[0]	auto[2]	auto[2]	28962	1			T3	43		T9	1		T12	40
auto[0]	auto[2]	auto[3]	32947	1			T3	5		T12	3		T40	203
auto[0]	auto[3]	auto[0]	3461654	1			T2	1		T3	261		T7	3715
auto[0]	auto[3]	auto[1]	372708	1			T3	29		T4	1		T7	376
auto[0]	auto[3]	auto[2]	383777	1			T2	3		T3	76		T4	1
auto[0]	auto[3]	auto[3]	295356	1			T3	10		T7	36		T9	2
auto[1]	auto[0]	auto[0]	16759	1			T54	187		T75	180		T113	95
auto[1]	auto[0]	auto[1]	74331	1			T54	887		T75	746		T113	455
auto[1]	auto[0]	auto[2]	74713	1			T54	869		T75	773		T113	440
auto[1]	auto[0]	auto[3]	335538	1			T54	4015		T75	3442		T113	1841
auto[1]	auto[1]	auto[0]	3486952	1			T54	343		T74	85559		T75	300
auto[1]	auto[1]	auto[1]	575818	1			T54	3073		T74	8400		T75	2553
auto[1]	auto[1]	auto[2]	529150	1			T54	1736		T74	8550		T75	1429
auto[1]	auto[1]	auto[3]	1143852	1			T10	1		T54	13948		T74	887
auto[1]	auto[2]	auto[0]	12203	1			T37	882		T139	391		T140	740
auto[1]	auto[2]	auto[1]	54645	1			T37	3912		T139	1867		T140	3137
auto[1]	auto[2]	auto[2]	61810	1			T54	812		T75	710		T113	348
auto[1]	auto[2]	auto[3]	278447	1			T40	1		T54	3612		T75	3100
auto[1]	auto[3]	auto[0]	3486450	1			T54	186		T56	1		T74	85324
auto[1]	auto[3]	auto[1]	511798	1			T54	744		T74	8589		T75	648
auto[1]	auto[3]	auto[2]	562323	1			T54	2928		T74	8557		T75	2587
auto[1]	auto[3]	auto[3]	1086696	1			T54	13486		T74	817		T75	11571