Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1218858270	192557	0	0
ctrl_regwen_rd_A	1218858270	5227	0	0
exec_rd_A	1218858270	4882	0	0
exec_regwen_rd_A	1218858270	5596	0	0
readback_rd_A	1218858270	3543	0	0
readback_regwen_rd_A	1218858270	3219	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218858270	192557	0	0
T13	887	0	0	0
T22	25267	958	0	0
T23	0	2423	0	0
T24	0	1830	0	0
T38	0	3192	0	0
T58	0	2049	0	0
T59	0	7499	0	0
T68	213754	0	0	0
T70	0	4173	0	0
T71	0	5182	0	0
T72	0	4182	0	0
T73	0	3247	0	0
T74	453111	0	0	0
T75	174454	0	0	0
T76	104716	0	0	0
T77	77968	0	0	0
T78	164395	0	0	0
T79	475720	0	0	0
T80	522563	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218858270	5227	0	0
T13	887	0	0	0
T22	25267	72	0	0
T46	0	89	0	0
T47	0	502	0	0
T58	0	135	0	0
T68	213754	0	0	0
T73	0	275	0	0
T74	453111	0	0	0
T75	174454	0	0	0
T76	104716	0	0	0
T77	77968	0	0	0
T78	164395	0	0	0
T79	475720	0	0	0
T80	522563	0	0	0
T119	0	326	0	0
T120	0	289	0	0
T121	0	247	0	0
T122	0	89	0	0
T123	0	198	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218858270	4882	0	0
T13	887	0	0	0
T22	25267	38	0	0
T46	0	63	0	0
T47	0	382	0	0
T58	0	118	0	0
T68	213754	0	0	0
T73	0	265	0	0
T74	453111	0	0	0
T75	174454	0	0	0
T76	104716	0	0	0
T77	77968	0	0	0
T78	164395	0	0	0
T79	475720	0	0	0
T80	522563	0	0	0
T119	0	310	0	0
T120	0	148	0	0
T121	0	230	0	0
T122	0	89	0	0
T123	0	211	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218858270	5596	0	0
T13	887	0	0	0
T22	25267	57	0	0
T46	0	96	0	0
T47	0	537	0	0
T58	0	197	0	0
T68	213754	0	0	0
T73	0	323	0	0
T74	453111	0	0	0
T75	174454	0	0	0
T76	104716	0	0	0
T77	77968	0	0	0
T78	164395	0	0	0
T79	475720	0	0	0
T80	522563	0	0	0
T119	0	319	0	0
T120	0	256	0	0
T121	0	239	0	0
T122	0	94	0	0
T123	0	247	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218858270	3543	0	0
T13	887	0	0	0
T22	25267	22	0	0
T46	0	76	0	0
T47	0	425	0	0
T58	0	118	0	0
T68	213754	0	0	0
T73	0	319	0	0
T74	453111	0	0	0
T75	174454	0	0	0
T76	104716	0	0	0
T77	77968	0	0	0
T78	164395	0	0	0
T79	475720	0	0	0
T80	522563	0	0	0
T119	0	163	0	0
T120	0	258	0	0
T121	0	252	0	0
T122	0	79	0	0
T123	0	159	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218858270	3219	0	0
T13	887	0	0	0
T22	25267	26	0	0
T46	0	85	0	0
T47	0	428	0	0
T58	0	123	0	0
T68	213754	0	0	0
T73	0	179	0	0
T74	453111	0	0	0
T75	174454	0	0	0
T76	104716	0	0	0
T77	77968	0	0	0
T78	164395	0	0	0
T79	475720	0	0	0
T80	522563	0	0	0
T119	0	235	0	0
T120	0	230	0	0
T121	0	125	0	0
T122	0	48	0	0
T123	0	219	0	0