Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	350322070	1			T3	472992		T4	746468		T5	208268
instr_valid_dis	307023595	1			T3	275620		T4	746468		T5	208268
instr_en	31061557	1			T6	208756		T26	30666		T63	11802

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18552102	1			T3	77872		T6	17630		T26	7320
sram_ifetch_valid_disable	304565630	1			T3	353052		T4	746468		T5	208268
sram_ifetch_enable	27204338	1			T3	42068		T6	113642		T26	57720

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	350322070	1			T3	472992		T4	746468		T5	208268
hw_debug_en_valid_off	303737690	1			T3	330476		T4	746468		T5	208268
hw_debug_en_on	32444630	1			T3	37182		T6	32052		T26	64540

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	304565630	1			T3	353052		T4	746468		T5	208268
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	292042237	1			T3	241670		T4	746468		T5	208268
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8904859	1			T6	77484		T26	23388		T19	118426
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	7096458	1			T3	53954		T26	42		T20	13832
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1670084	1			T26	42		T76	33610		T122	10406
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4728348	1			T76	60952		T140	13446		T143	2852
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	8576126	1			T3	23918		T6	17630		T26	7278
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3491376	1			T63	31566		T76	40070		T140	17614
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1212080	1			T6	17630		T26	7278		T140	46
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14108492	1			T3	13264		T6	14422		T26	57262
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	8502582	1			T26	39400		T76	171620		T139	221870
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4154352	1			T6	14422		T19	16206		T144	33062

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	15193208	1			T6	113642		T63	11802		T19	103036
lc_exec_en	9760012	1			T63	11802		T19	90476		T20	109336
valid_exec_dis	294592366	1			T3	276522		T4	746468		T5	208268
invalid_exec_dis	45756440	1			T3	119940		T6	131272		T26	65040