Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	145687753	1			T3	151972		T4	339496		T5	94563
triple_byte_access	2845437	1			T3	3021		T4	6735		T5	1948
halfword_access	4356335	1			T3	4626		T4	10018		T5	2896
byte_access	6078513	1			T3	6064		T4	13556		T5	3765
zero_access	1819358	1			T3	1516		T4	3429		T5	962

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80218810

1

T3

85389

T4

186661

T5

51935

auto[1]

80568586

1

T3

81810

T4

186573

T5

52199

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72532436	1			T3	77617		T4	169740		T5	47192
auto[0]	triple_byte_access	1361881	1			T3	1537		T4	3403		T5	980
auto[0]	halfword_access	2133088	1			T3	2337		T4	5021		T5	1445
auto[0]	byte_access	3112177	1			T3	3094		T4	6773		T5	1857
auto[0]	zero_access	1079228	1			T3	804		T4	1724		T5	461
auto[1]	word_access	73155317	1			T3	74355		T4	169756		T5	47371
auto[1]	triple_byte_access	1483556	1			T3	1484		T4	3332		T5	968
auto[1]	halfword_access	2223247	1			T3	2289		T4	4997		T5	1451
auto[1]	byte_access	2966336	1			T3	2970		T4	6783		T5	1908
auto[1]	zero_access	740130	1			T3	712		T4	1705		T5	501