Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	345008166	1			T1	144179		T2	20048		T3	17034
instr_valid_dis	305454138	1			T1	144179		T2	20048		T3	17034
instr_en	26625925	1			T13	35412		T22	374590		T30	364944

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13345104	1			T13	105842		T22	118910		T30	172932
sram_ifetch_valid_disable	301239575	1			T1	144179		T2	20048		T3	17034
sram_ifetch_enable	30423487	1			T13	6848		T22	248510		T27	6495

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	345008166	1			T1	144179		T2	20048		T3	17034
hw_debug_en_valid_off	307399849	1			T1	144179		T2	20048		T3	17034
hw_debug_en_on	26121514	1			T13	35412		T22	109444		T30	59014

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	301239575	1			T1	144179		T2	20048		T3	17034
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	285130202	1			T1	144179		T2	20048		T3	17034
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11605769	1			T22	66850		T30	88826		T73	76076
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5564296	1			T13	70430		T22	92916		T30	160608
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2138342	1			T13	70430		T22	59680		T23	112870
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2372922	1			T22	33236		T30	160608		T26	13608
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5625824	1			T13	35412		T22	25994		T30	12324
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3419686	1			T73	3268		T137	81124		T123	5616
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1369848	1			T13	35412		T22	25994		T30	12324
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11853248	1			T22	33548		T30	13864		T23	75590
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3300332	1			T23	75590		T70	69528		T82	99790
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6781380	1			T22	33548		T30	13864		T73	76076

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10532996	1			T22	248510		T30	103186		T73	64596
lc_exec_en	8642442	1			T22	49902		T30	32826		T24	4076
valid_exec_dis	298824110	1			T1	144179		T2	20048		T3	17034
invalid_exec_dis	43768591	1			T13	112690		T22	367420		T27	6495