Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.99 99.19 94.27 99.72 100.00 96.03 99.12 97.62


Total tests in report: 1038
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
68.25 68.25 89.94 89.94 66.82 66.82 85.09 85.09 23.81 23.81 77.49 77.49 93.27 93.27 41.32 41.32 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1011168123
87.94 19.69 96.08 6.13 83.53 16.71 93.22 8.13 90.48 66.67 89.34 11.85 96.05 2.78 66.91 25.59 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.547340744
92.67 4.72 97.38 1.31 87.32 3.79 94.94 1.72 100.00 9.52 92.89 3.55 96.05 0.00 80.07 13.16 /workspace/coverage/default/47.sram_ctrl_stress_all.861841917
93.93 1.27 98.77 1.39 87.56 0.24 97.76 2.82 100.00 0.00 94.79 1.90 96.93 0.88 81.72 1.65 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.515664706
94.90 0.97 99.10 0.33 89.57 2.01 98.73 0.96 100.00 0.00 96.21 1.42 97.51 0.58 83.18 1.46 /workspace/coverage/default/1.sram_ctrl_sec_cm.3843487858
95.66 0.76 99.10 0.00 89.93 0.36 98.73 0.00 100.00 0.00 96.21 0.00 97.51 0.00 88.12 4.94 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1432206057
96.36 0.71 99.10 0.00 89.93 0.00 98.73 0.00 100.00 0.00 96.21 0.00 97.51 0.00 93.05 4.94 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3905816173
96.65 0.29 99.10 0.00 90.17 0.24 98.73 0.00 100.00 0.00 96.21 0.00 97.66 0.15 94.70 1.65 /workspace/coverage/default/0.sram_ctrl_regwen.2036182909
96.91 0.26 99.10 0.00 90.40 0.24 98.79 0.07 100.00 0.00 96.21 0.00 98.83 1.17 95.06 0.37 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.680222476
97.05 0.13 99.10 0.00 90.40 0.00 98.79 0.00 100.00 0.00 96.21 0.00 98.83 0.00 95.98 0.91 /workspace/coverage/default/35.sram_ctrl_stress_all.1043759886
97.17 0.13 99.18 0.08 90.40 0.00 99.62 0.83 100.00 0.00 96.21 0.00 98.83 0.00 95.98 0.00 /workspace/coverage/default/1.sram_ctrl_ram_cfg.161906837
97.25 0.08 99.18 0.00 90.40 0.00 99.62 0.00 100.00 0.00 96.21 0.00 98.83 0.00 96.53 0.55 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1191974933
97.31 0.06 99.18 0.00 90.76 0.36 99.69 0.07 100.00 0.00 96.21 0.00 98.83 0.00 96.53 0.00 /workspace/coverage/default/1.sram_ctrl_alert_test.886639238
97.37 0.06 99.18 0.00 91.00 0.24 99.69 0.00 100.00 0.00 96.21 0.00 98.83 0.00 96.71 0.18 /workspace/coverage/default/34.sram_ctrl_stress_all.3791202902
97.43 0.05 99.18 0.00 91.00 0.00 99.69 0.00 100.00 0.00 96.21 0.00 98.83 0.00 97.07 0.37 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1805881528
97.45 0.03 99.18 0.00 91.00 0.00 99.69 0.00 100.00 0.00 96.21 0.00 98.83 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3038109005
97.48 0.03 99.18 0.00 91.00 0.00 99.69 0.00 100.00 0.00 96.21 0.00 98.83 0.00 97.44 0.18 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1000978810
97.50 0.03 99.18 0.00 91.00 0.00 99.69 0.00 100.00 0.00 96.21 0.00 98.83 0.00 97.62 0.18 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2806206186
97.53 0.03 99.18 0.00 91.00 0.00 99.72 0.03 100.00 0.00 96.21 0.00 98.98 0.15 97.62 0.00 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1551346672
97.55 0.02 99.18 0.00 91.00 0.00 99.72 0.00 100.00 0.00 96.21 0.00 99.12 0.15 97.62 0.00 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4289862075


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3969723125
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3077383513
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2836946122
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4283865637
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3233099410
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.482253095
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3238668916
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2685802822
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1870086078
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2187443196
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.726101506
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3523694928
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4055345395
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2047380789
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.448198022
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1164379709
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1384883615
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2642827498
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2040885467
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2621745986
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2906051737
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3938316047
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1574503232
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2498646302
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4147295571
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1076688821
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3142479034
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1638240601
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.833076440
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4239728891
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.929817370
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2532176993
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.841148395
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1869085551
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2966352394
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2265516400
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2545550715
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3481185876
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2702254230
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2839536932
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4009451113
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1606275895
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2065317243
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2378609311
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1237864944
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3335137295
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3557486617
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.759387982
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3186243076
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.143452727
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3424326329
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3057569607
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4216086228
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2221315941
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2875166456
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.139140414
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4091845219
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.272665566
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3129189479
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3059791393
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1500719852
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3090336559
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1383313446
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1517427176
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3731697105
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4268346230
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1731427754
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3038675012
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3104411529
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2850523384
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2786651566
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1603641294
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2067195058
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3505682940
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1120526988
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1653362745
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.576520603
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3804859562
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3007823820
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3429562212
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3975837947
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2151811799
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.130647156
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3339416809
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1867866627
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3721309821
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1450700970
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3769621898
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.731494989
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2659099072
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1615111708
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1002474534
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3211913158
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2833091864
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2901819400
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.606755621
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3446398216
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1264352039
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.4006756866
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4216634052
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3385535117
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.62215692
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2275168207
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2707107387
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1075535047
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.389576422
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1323306110
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1009320986
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3594670206
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4045312552
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1695828839
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1351554055
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2115000807
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1945630021
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2376003667
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2961697175
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1690650424
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.453052557
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3544918338
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3288734600
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2288299406
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2932927490
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1682864779
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1737557652
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3276163196
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2957054814
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2251971636
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1386261791
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3825962553
/workspace/coverage/default/0.sram_ctrl_alert_test.4251031289
/workspace/coverage/default/0.sram_ctrl_bijection.2038862635
/workspace/coverage/default/0.sram_ctrl_executable.1001166228
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3594624372
/workspace/coverage/default/0.sram_ctrl_max_throughput.2892055511
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2438937687
/workspace/coverage/default/0.sram_ctrl_mem_walk.3031199346
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3012728534
/workspace/coverage/default/0.sram_ctrl_partial_access.2704537826
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1055462773
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3990553646
/workspace/coverage/default/0.sram_ctrl_sec_cm.1628710846
/workspace/coverage/default/0.sram_ctrl_smoke.1432678337
/workspace/coverage/default/0.sram_ctrl_stress_all.1198732850
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.16221709
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3590036233
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.80814594
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.591760207
/workspace/coverage/default/1.sram_ctrl_bijection.1006103919
/workspace/coverage/default/1.sram_ctrl_executable.1468772477
/workspace/coverage/default/1.sram_ctrl_lc_escalation.2975686915
/workspace/coverage/default/1.sram_ctrl_max_throughput.1805753521
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2895014451
/workspace/coverage/default/1.sram_ctrl_mem_walk.3668838069
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2385443375
/workspace/coverage/default/1.sram_ctrl_partial_access.1211244582
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.625061224
/workspace/coverage/default/1.sram_ctrl_regwen.4080608216
/workspace/coverage/default/1.sram_ctrl_smoke.3803505339
/workspace/coverage/default/1.sram_ctrl_stress_all.3513973158
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1318029261
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.768087082
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2058167349
/workspace/coverage/default/10.sram_ctrl_alert_test.272540731
/workspace/coverage/default/10.sram_ctrl_bijection.165969425
/workspace/coverage/default/10.sram_ctrl_executable.1538693976
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2962151415
/workspace/coverage/default/10.sram_ctrl_max_throughput.3034896896
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.94046414
/workspace/coverage/default/10.sram_ctrl_mem_walk.2180242033
/workspace/coverage/default/10.sram_ctrl_multiple_keys.408829899
/workspace/coverage/default/10.sram_ctrl_partial_access.7531973
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2499252179
/workspace/coverage/default/10.sram_ctrl_ram_cfg.368327472
/workspace/coverage/default/10.sram_ctrl_regwen.3331689684
/workspace/coverage/default/10.sram_ctrl_smoke.3305218855
/workspace/coverage/default/10.sram_ctrl_stress_all.3188214793
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1870691811
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3625897591
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3873766791
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3634711130
/workspace/coverage/default/11.sram_ctrl_alert_test.2725822350
/workspace/coverage/default/11.sram_ctrl_bijection.3312746465
/workspace/coverage/default/11.sram_ctrl_executable.2621995843
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4287716355
/workspace/coverage/default/11.sram_ctrl_max_throughput.2968129231
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2314110270
/workspace/coverage/default/11.sram_ctrl_mem_walk.14874129
/workspace/coverage/default/11.sram_ctrl_multiple_keys.4041571290
/workspace/coverage/default/11.sram_ctrl_partial_access.716364430
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3036545852
/workspace/coverage/default/11.sram_ctrl_regwen.2652304448
/workspace/coverage/default/11.sram_ctrl_smoke.2817053378
/workspace/coverage/default/11.sram_ctrl_stress_all.898165311
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3592840705
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1272892765
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4177243720
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.406474528
/workspace/coverage/default/12.sram_ctrl_alert_test.404554399
/workspace/coverage/default/12.sram_ctrl_bijection.2726659759
/workspace/coverage/default/12.sram_ctrl_executable.3985703560
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3658514559
/workspace/coverage/default/12.sram_ctrl_max_throughput.1649521156
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3188151343
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/workspace/coverage/default/42.sram_ctrl_regwen.3100007151
/workspace/coverage/default/42.sram_ctrl_smoke.2945390327
/workspace/coverage/default/42.sram_ctrl_stress_all.3646207860
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.394934477
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1505932372
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.374521481
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3475283369
/workspace/coverage/default/43.sram_ctrl_alert_test.635732932
/workspace/coverage/default/43.sram_ctrl_bijection.4164764737
/workspace/coverage/default/43.sram_ctrl_executable.3609237719
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1351940829
/workspace/coverage/default/43.sram_ctrl_max_throughput.3507392812
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3404588079
/workspace/coverage/default/43.sram_ctrl_mem_walk.809911900
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1369494613
/workspace/coverage/default/43.sram_ctrl_partial_access.263658573
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3079881330
/workspace/coverage/default/43.sram_ctrl_ram_cfg.345764356
/workspace/coverage/default/43.sram_ctrl_regwen.2635245580
/workspace/coverage/default/43.sram_ctrl_smoke.1895104330
/workspace/coverage/default/43.sram_ctrl_stress_all.3891725559
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.662046166
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2991493960
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1910259287
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1312378450
/workspace/coverage/default/44.sram_ctrl_alert_test.3549705118
/workspace/coverage/default/44.sram_ctrl_bijection.95707116
/workspace/coverage/default/44.sram_ctrl_executable.2868323767
/workspace/coverage/default/44.sram_ctrl_lc_escalation.180939743
/workspace/coverage/default/44.sram_ctrl_max_throughput.1156742612
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1560783649
/workspace/coverage/default/44.sram_ctrl_mem_walk.3964340450
/workspace/coverage/default/44.sram_ctrl_multiple_keys.106977988
/workspace/coverage/default/44.sram_ctrl_partial_access.835969702
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1423853423
/workspace/coverage/default/44.sram_ctrl_ram_cfg.427051474
/workspace/coverage/default/44.sram_ctrl_regwen.3442284297
/workspace/coverage/default/44.sram_ctrl_smoke.324917465
/workspace/coverage/default/44.sram_ctrl_stress_all.787332040
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.360538766
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2738039456
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1228638587
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3729736492
/workspace/coverage/default/45.sram_ctrl_alert_test.3657362109
/workspace/coverage/default/45.sram_ctrl_bijection.3190868438
/workspace/coverage/default/45.sram_ctrl_executable.2945173772
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1284934026
/workspace/coverage/default/45.sram_ctrl_max_throughput.1280357146
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3031416684
/workspace/coverage/default/45.sram_ctrl_mem_walk.104273274
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3165105343
/workspace/coverage/default/45.sram_ctrl_partial_access.2630246040
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2899889093
/workspace/coverage/default/45.sram_ctrl_ram_cfg.32356912
/workspace/coverage/default/45.sram_ctrl_regwen.2358690532
/workspace/coverage/default/45.sram_ctrl_smoke.2177232533
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1054263024
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1604024718
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.613059531
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.310754953
/workspace/coverage/default/46.sram_ctrl_alert_test.353556841
/workspace/coverage/default/46.sram_ctrl_bijection.1854824415
/workspace/coverage/default/46.sram_ctrl_executable.441481775
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3068530694
/workspace/coverage/default/46.sram_ctrl_max_throughput.2570022399
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.947532520
/workspace/coverage/default/46.sram_ctrl_mem_walk.120808912
/workspace/coverage/default/46.sram_ctrl_multiple_keys.128122746
/workspace/coverage/default/46.sram_ctrl_partial_access.1156070123
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3033181611
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3831791164
/workspace/coverage/default/46.sram_ctrl_regwen.2814673217
/workspace/coverage/default/46.sram_ctrl_smoke.2540605549
/workspace/coverage/default/46.sram_ctrl_stress_all.2591067547
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.968747913
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3342574369
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3910860607
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.794336714
/workspace/coverage/default/47.sram_ctrl_alert_test.1595824526
/workspace/coverage/default/47.sram_ctrl_bijection.2447756017
/workspace/coverage/default/47.sram_ctrl_executable.1274598630
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2435207504
/workspace/coverage/default/47.sram_ctrl_max_throughput.4128635934
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3219782523
/workspace/coverage/default/47.sram_ctrl_mem_walk.1192829206
/workspace/coverage/default/47.sram_ctrl_multiple_keys.215766057
/workspace/coverage/default/47.sram_ctrl_partial_access.3198852003
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1231676155
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3563165865
/workspace/coverage/default/47.sram_ctrl_regwen.548809184
/workspace/coverage/default/47.sram_ctrl_smoke.711474480
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2435881717
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2675035361
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3138321384
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.4050436560
/workspace/coverage/default/48.sram_ctrl_alert_test.3255967602
/workspace/coverage/default/48.sram_ctrl_bijection.1565494090
/workspace/coverage/default/48.sram_ctrl_executable.1135779663
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3280323027
/workspace/coverage/default/48.sram_ctrl_max_throughput.149714276
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2086734273
/workspace/coverage/default/48.sram_ctrl_mem_walk.1475117026
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3328373000
/workspace/coverage/default/48.sram_ctrl_partial_access.2196984064
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1634711315
/workspace/coverage/default/48.sram_ctrl_ram_cfg.845925103
/workspace/coverage/default/48.sram_ctrl_regwen.3145889061
/workspace/coverage/default/48.sram_ctrl_smoke.4159157746
/workspace/coverage/default/48.sram_ctrl_stress_all.2318771382
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4294589618
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1532766558
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.781721866
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2797036513
/workspace/coverage/default/49.sram_ctrl_alert_test.4268684994
/workspace/coverage/default/49.sram_ctrl_bijection.887126823
/workspace/coverage/default/49.sram_ctrl_executable.3192402678
/workspace/coverage/default/49.sram_ctrl_lc_escalation.3718845360
/workspace/coverage/default/49.sram_ctrl_max_throughput.1340993647
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1988896087
/workspace/coverage/default/49.sram_ctrl_mem_walk.1377942617
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3565450809
/workspace/coverage/default/49.sram_ctrl_partial_access.2984249038
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3130466257
/workspace/coverage/default/49.sram_ctrl_ram_cfg.761965830
/workspace/coverage/default/49.sram_ctrl_regwen.1378726408
/workspace/coverage/default/49.sram_ctrl_smoke.4260990030
/workspace/coverage/default/49.sram_ctrl_stress_all.3161571545
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.215413134
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1589071140
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2668600557
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.611246490
/workspace/coverage/default/5.sram_ctrl_alert_test.1012048341
/workspace/coverage/default/5.sram_ctrl_bijection.2419927508
/workspace/coverage/default/5.sram_ctrl_executable.685389464
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1690407388
/workspace/coverage/default/5.sram_ctrl_max_throughput.241214800
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2855533199
/workspace/coverage/default/5.sram_ctrl_mem_walk.26543433
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3671590540
/workspace/coverage/default/5.sram_ctrl_partial_access.40007165
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2371988497
/workspace/coverage/default/5.sram_ctrl_ram_cfg.616849493
/workspace/coverage/default/5.sram_ctrl_regwen.682475541
/workspace/coverage/default/5.sram_ctrl_smoke.1436385581
/workspace/coverage/default/5.sram_ctrl_stress_all.447088514
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2364473770
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3917285945
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1317130573
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.4174213107
/workspace/coverage/default/6.sram_ctrl_alert_test.1480109605
/workspace/coverage/default/6.sram_ctrl_bijection.2417847849
/workspace/coverage/default/6.sram_ctrl_executable.1570480648
/workspace/coverage/default/6.sram_ctrl_lc_escalation.110270848
/workspace/coverage/default/6.sram_ctrl_max_throughput.992095082
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2253048767
/workspace/coverage/default/6.sram_ctrl_mem_walk.2219785468
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1777986592
/workspace/coverage/default/6.sram_ctrl_partial_access.3438522721
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1974948444
/workspace/coverage/default/6.sram_ctrl_ram_cfg.902550244
/workspace/coverage/default/6.sram_ctrl_regwen.2037763355
/workspace/coverage/default/6.sram_ctrl_smoke.3407896202
/workspace/coverage/default/6.sram_ctrl_stress_all.3542548416
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1037695014
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3256552485
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.567377490
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1481515186
/workspace/coverage/default/7.sram_ctrl_alert_test.3669824003
/workspace/coverage/default/7.sram_ctrl_bijection.1148055349
/workspace/coverage/default/7.sram_ctrl_executable.752072162
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3899502237
/workspace/coverage/default/7.sram_ctrl_max_throughput.702274567
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2402909311
/workspace/coverage/default/7.sram_ctrl_mem_walk.3119905078
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4238661561
/workspace/coverage/default/7.sram_ctrl_partial_access.3069427245
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2453302418
/workspace/coverage/default/7.sram_ctrl_regwen.1591664737
/workspace/coverage/default/7.sram_ctrl_smoke.1138902681
/workspace/coverage/default/7.sram_ctrl_stress_all.2248603440
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2410756014
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1307342318
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2592144080
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2852499941
/workspace/coverage/default/8.sram_ctrl_alert_test.1058113572
/workspace/coverage/default/8.sram_ctrl_bijection.2579832504
/workspace/coverage/default/8.sram_ctrl_executable.1388445928
/workspace/coverage/default/8.sram_ctrl_lc_escalation.351872343
/workspace/coverage/default/8.sram_ctrl_max_throughput.1518791840
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.4051102075
/workspace/coverage/default/8.sram_ctrl_mem_walk.485925231
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1015447632
/workspace/coverage/default/8.sram_ctrl_partial_access.3499820706
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2566300446
/workspace/coverage/default/8.sram_ctrl_ram_cfg.626473092
/workspace/coverage/default/8.sram_ctrl_regwen.1092182373
/workspace/coverage/default/8.sram_ctrl_smoke.1313682405
/workspace/coverage/default/8.sram_ctrl_stress_all.2280274230
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1518413577
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2196575836
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3719530351
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1830859040
/workspace/coverage/default/9.sram_ctrl_alert_test.2821826426
/workspace/coverage/default/9.sram_ctrl_bijection.653733607
/workspace/coverage/default/9.sram_ctrl_executable.2154288879
/workspace/coverage/default/9.sram_ctrl_lc_escalation.4118607544
/workspace/coverage/default/9.sram_ctrl_max_throughput.3585191031
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1010889042
/workspace/coverage/default/9.sram_ctrl_mem_walk.3998904262
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3565840929
/workspace/coverage/default/9.sram_ctrl_partial_access.3179216405
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.218908964
/workspace/coverage/default/9.sram_ctrl_ram_cfg.987623214
/workspace/coverage/default/9.sram_ctrl_regwen.3765389647
/workspace/coverage/default/9.sram_ctrl_smoke.2071980474
/workspace/coverage/default/9.sram_ctrl_stress_all.1014479943
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1243206441
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1946456339
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1648320033




Total test records in report: 1038
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/26.sram_ctrl_bijection.3639706117 Jul 27 06:48:46 PM PDT 24 Jul 27 07:10:10 PM PDT 24 200114534107 ps
T2 /workspace/coverage/default/46.sram_ctrl_smoke.2540605549 Jul 27 06:52:56 PM PDT 24 Jul 27 06:55:14 PM PDT 24 2712305874 ps
T3 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.941903362 Jul 27 06:47:44 PM PDT 24 Jul 27 06:49:18 PM PDT 24 1591479211 ps
T5 /workspace/coverage/default/30.sram_ctrl_max_throughput.3497921798 Jul 27 06:49:38 PM PDT 24 Jul 27 06:51:08 PM PDT 24 3164975588 ps
T4 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.515664706 Jul 27 06:50:41 PM PDT 24 Jul 27 07:04:33 PM PDT 24 10364437654 ps
T9 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3829762989 Jul 27 06:48:30 PM PDT 24 Jul 27 06:50:37 PM PDT 24 3909615711 ps
T10 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1011168123 Jul 27 06:45:29 PM PDT 24 Jul 27 06:51:54 PM PDT 24 16043151580 ps
T11 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2724466626 Jul 27 06:48:05 PM PDT 24 Jul 27 06:54:01 PM PDT 24 36154305264 ps
T12 /workspace/coverage/default/10.sram_ctrl_bijection.165969425 Jul 27 06:45:58 PM PDT 24 Jul 27 07:22:57 PM PDT 24 32154806543 ps
T13 /workspace/coverage/default/25.sram_ctrl_executable.3389140530 Jul 27 06:48:37 PM PDT 24 Jul 27 06:57:41 PM PDT 24 37453850993 ps
T46 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1551346672 Jul 27 06:45:15 PM PDT 24 Jul 27 06:47:58 PM PDT 24 10659211440 ps
T47 /workspace/coverage/default/38.sram_ctrl_multiple_keys.218838340 Jul 27 06:51:16 PM PDT 24 Jul 27 07:06:27 PM PDT 24 33611378710 ps
T14 /workspace/coverage/default/22.sram_ctrl_alert_test.3643999532 Jul 27 06:48:11 PM PDT 24 Jul 27 06:48:12 PM PDT 24 22246375 ps
T45 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.4051102075 Jul 27 06:45:57 PM PDT 24 Jul 27 06:47:11 PM PDT 24 2685206178 ps
T48 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2451355163 Jul 27 06:51:43 PM PDT 24 Jul 27 06:54:10 PM PDT 24 3066879061 ps
T21 /workspace/coverage/default/14.sram_ctrl_bijection.269579434 Jul 27 06:46:32 PM PDT 24 Jul 27 07:32:37 PM PDT 24 689636475693 ps
T59 /workspace/coverage/default/27.sram_ctrl_partial_access.2012748530 Jul 27 06:49:05 PM PDT 24 Jul 27 06:49:19 PM PDT 24 966106140 ps
T22 /workspace/coverage/default/18.sram_ctrl_regwen.1506497202 Jul 27 06:47:18 PM PDT 24 Jul 27 07:06:41 PM PDT 24 16310555490 ps
T49 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1484967011 Jul 27 06:46:44 PM PDT 24 Jul 27 07:02:42 PM PDT 24 11966501388 ps
T27 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.547340744 Jul 27 06:51:58 PM PDT 24 Jul 27 06:52:43 PM PDT 24 2241884105 ps
T71 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3831187106 Jul 27 06:46:19 PM PDT 24 Jul 27 06:51:16 PM PDT 24 5331132129 ps
T72 /workspace/coverage/default/40.sram_ctrl_multiple_keys.387340479 Jul 27 06:51:37 PM PDT 24 Jul 27 06:59:31 PM PDT 24 53389364649 ps
T30 /workspace/coverage/default/45.sram_ctrl_regwen.2358690532 Jul 27 06:52:48 PM PDT 24 Jul 27 07:12:55 PM PDT 24 13653789445 ps
T23 /workspace/coverage/default/0.sram_ctrl_regwen.2036182909 Jul 27 06:45:09 PM PDT 24 Jul 27 07:06:02 PM PDT 24 73711410211 ps
T73 /workspace/coverage/default/34.sram_ctrl_executable.322343651 Jul 27 06:50:36 PM PDT 24 Jul 27 07:04:03 PM PDT 24 113831431278 ps
T24 /workspace/coverage/default/17.sram_ctrl_regwen.469545700 Jul 27 06:47:10 PM PDT 24 Jul 27 06:58:49 PM PDT 24 17314525177 ps
T50 /workspace/coverage/default/38.sram_ctrl_mem_walk.2377406622 Jul 27 06:51:25 PM PDT 24 Jul 27 06:56:41 PM PDT 24 52503958664 ps
T80 /workspace/coverage/default/23.sram_ctrl_partial_access.633743298 Jul 27 06:48:14 PM PDT 24 Jul 27 06:48:37 PM PDT 24 6086497566 ps
T81 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1735984980 Jul 27 06:50:04 PM PDT 24 Jul 27 06:56:47 PM PDT 24 18937533020 ps
T96 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.774980278 Jul 27 06:49:04 PM PDT 24 Jul 27 06:50:20 PM PDT 24 18163064109 ps
T111 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1121687800 Jul 27 06:49:55 PM PDT 24 Jul 27 06:57:46 PM PDT 24 78203413615 ps
T6 /workspace/coverage/default/33.sram_ctrl_lc_escalation.3699765773 Jul 27 06:50:17 PM PDT 24 Jul 27 06:50:53 PM PDT 24 22186588950 ps
T145 /workspace/coverage/default/25.sram_ctrl_max_throughput.1321008527 Jul 27 06:48:37 PM PDT 24 Jul 27 06:49:20 PM PDT 24 746802160 ps
T7 /workspace/coverage/default/7.sram_ctrl_lc_escalation.3899502237 Jul 27 06:45:38 PM PDT 24 Jul 27 06:46:42 PM PDT 24 41630710150 ps
T147 /workspace/coverage/default/32.sram_ctrl_partial_access.1770086961 Jul 27 06:49:56 PM PDT 24 Jul 27 06:51:08 PM PDT 24 8687371739 ps
T8 /workspace/coverage/default/35.sram_ctrl_lc_escalation.47447618 Jul 27 06:50:40 PM PDT 24 Jul 27 06:51:18 PM PDT 24 5625535282 ps
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T29 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3905816173 Jul 27 06:45:09 PM PDT 24 Jul 27 06:45:34 PM PDT 24 1038259578 ps
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T26 /workspace/coverage/default/47.sram_ctrl_stress_all.861841917 Jul 27 06:53:30 PM PDT 24 Jul 27 07:45:52 PM PDT 24 450132751217 ps
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T158 /workspace/coverage/default/35.sram_ctrl_bijection.4173769135 Jul 27 06:50:33 PM PDT 24 Jul 27 07:02:58 PM PDT 24 32472090133 ps
T55 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.109149196 Jul 27 06:51:30 PM PDT 24 Jul 27 06:52:53 PM PDT 24 2623970516 ps
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T74 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1342023866 Jul 27 06:50:33 PM PDT 24 Jul 27 06:51:02 PM PDT 24 2170773519 ps
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T166 /workspace/coverage/default/19.sram_ctrl_stress_all.1678480200 Jul 27 06:47:35 PM PDT 24 Jul 27 08:00:05 PM PDT 24 83152402129 ps
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T170 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2058167349 Jul 27 06:46:05 PM PDT 24 Jul 27 07:14:44 PM PDT 24 20262844689 ps
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T113 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1685379343 Jul 27 06:50:36 PM PDT 24 Jul 27 06:55:14 PM PDT 24 6833241525 ps
T173 /workspace/coverage/default/18.sram_ctrl_partial_access.1402702934 Jul 27 06:47:18 PM PDT 24 Jul 27 06:47:33 PM PDT 24 1739671382 ps
T58 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1560783649 Jul 27 06:52:41 PM PDT 24 Jul 27 06:55:29 PM PDT 24 5113709188 ps
T75 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.931433881 Jul 27 06:47:42 PM PDT 24 Jul 27 06:47:55 PM PDT 24 364535403 ps
T139 /workspace/coverage/default/4.sram_ctrl_stress_all.333975140 Jul 27 06:45:22 PM PDT 24 Jul 27 07:41:56 PM PDT 24 138017577169 ps
T114 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2032957324 Jul 27 06:49:22 PM PDT 24 Jul 27 06:53:43 PM PDT 24 6441693424 ps
T174 /workspace/coverage/default/9.sram_ctrl_partial_access.3179216405 Jul 27 06:45:56 PM PDT 24 Jul 27 06:46:03 PM PDT 24 2710523302 ps
T175 /workspace/coverage/default/41.sram_ctrl_max_throughput.123681108 Jul 27 06:51:46 PM PDT 24 Jul 27 06:52:48 PM PDT 24 741031941 ps
T176 /workspace/coverage/default/14.sram_ctrl_executable.3914934489 Jul 27 06:46:43 PM PDT 24 Jul 27 07:02:43 PM PDT 24 9479137648 ps
T177 /workspace/coverage/default/9.sram_ctrl_max_throughput.3585191031 Jul 27 06:45:49 PM PDT 24 Jul 27 06:46:03 PM PDT 24 2865245287 ps
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T76 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2364473770 Jul 27 06:45:36 PM PDT 24 Jul 27 06:45:45 PM PDT 24 871917448 ps
T179 /workspace/coverage/default/24.sram_ctrl_multiple_keys.2752573207 Jul 27 06:48:22 PM PDT 24 Jul 27 07:02:51 PM PDT 24 76472937764 ps
T32 /workspace/coverage/default/14.sram_ctrl_ram_cfg.514742308 Jul 27 06:46:44 PM PDT 24 Jul 27 06:46:47 PM PDT 24 1491891060 ps
T18 /workspace/coverage/default/3.sram_ctrl_sec_cm.994294860 Jul 27 06:45:19 PM PDT 24 Jul 27 06:45:22 PM PDT 24 336316938 ps
T36 /workspace/coverage/default/28.sram_ctrl_multiple_keys.1225486249 Jul 27 06:49:15 PM PDT 24 Jul 27 07:17:23 PM PDT 24 161995023031 ps
T37 /workspace/coverage/default/4.sram_ctrl_mem_walk.3050521674 Jul 27 06:45:25 PM PDT 24 Jul 27 06:51:16 PM PDT 24 77993703377 ps
T38 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1788324969 Jul 27 06:47:52 PM PDT 24 Jul 27 06:48:01 PM PDT 24 570711231 ps
T39 /workspace/coverage/default/10.sram_ctrl_regwen.3331689684 Jul 27 06:46:00 PM PDT 24 Jul 27 06:56:55 PM PDT 24 49950385867 ps
T40 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1127464753 Jul 27 06:50:49 PM PDT 24 Jul 27 06:56:02 PM PDT 24 54414149157 ps
T41 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.406474528 Jul 27 06:46:17 PM PDT 24 Jul 27 07:05:05 PM PDT 24 271401535842 ps
T42 /workspace/coverage/default/28.sram_ctrl_max_throughput.1563223370 Jul 27 06:49:13 PM PDT 24 Jul 27 06:50:37 PM PDT 24 1525926485 ps
T43 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4068438643 Jul 27 06:46:36 PM PDT 24 Jul 27 06:47:41 PM PDT 24 1573224924 ps
T44 /workspace/coverage/default/18.sram_ctrl_multiple_keys.3609075476 Jul 27 06:47:16 PM PDT 24 Jul 27 06:50:55 PM PDT 24 9436312317 ps
T180 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2577578922 Jul 27 06:49:48 PM PDT 24 Jul 27 06:57:18 PM PDT 24 31530661196 ps
T181 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1473618692 Jul 27 06:45:12 PM PDT 24 Jul 27 06:52:23 PM PDT 24 18171576677 ps
T182 /workspace/coverage/default/2.sram_ctrl_lc_escalation.974570027 Jul 27 06:45:10 PM PDT 24 Jul 27 06:46:02 PM PDT 24 33050083147 ps
T183 /workspace/coverage/default/4.sram_ctrl_regwen.663196453 Jul 27 06:45:18 PM PDT 24 Jul 27 06:54:40 PM PDT 24 11425686117 ps
T184 /workspace/coverage/default/30.sram_ctrl_bijection.3625491425 Jul 27 06:49:38 PM PDT 24 Jul 27 07:10:11 PM PDT 24 211761687823 ps
T19 /workspace/coverage/default/2.sram_ctrl_sec_cm.3909198102 Jul 27 06:45:13 PM PDT 24 Jul 27 06:45:15 PM PDT 24 183210680 ps
T185 /workspace/coverage/default/30.sram_ctrl_executable.1486900932 Jul 27 06:49:38 PM PDT 24 Jul 27 07:04:45 PM PDT 24 40066855572 ps
T186 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.3000783364 Jul 27 06:45:19 PM PDT 24 Jul 27 06:55:59 PM PDT 24 16879208820 ps
T187 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4050436560 Jul 27 06:53:37 PM PDT 24 Jul 27 07:00:29 PM PDT 24 19944596259 ps
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T189 /workspace/coverage/default/5.sram_ctrl_max_throughput.241214800 Jul 27 06:45:20 PM PDT 24 Jul 27 06:46:11 PM PDT 24 744743912 ps
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T194 /workspace/coverage/default/16.sram_ctrl_regwen.2553717295 Jul 27 06:47:00 PM PDT 24 Jul 27 06:57:01 PM PDT 24 35769086668 ps
T195 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2302643611 Jul 27 06:48:12 PM PDT 24 Jul 27 06:48:32 PM PDT 24 5972599104 ps
T196 /workspace/coverage/default/8.sram_ctrl_stress_all.2280274230 Jul 27 06:45:50 PM PDT 24 Jul 27 08:39:28 PM PDT 24 949760022783 ps
T197 /workspace/coverage/default/2.sram_ctrl_stress_all.2813607260 Jul 27 06:45:12 PM PDT 24 Jul 27 07:22:39 PM PDT 24 69618401052 ps
T198 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1312378450 Jul 27 06:52:32 PM PDT 24 Jul 27 07:22:54 PM PDT 24 170102262093 ps
T60 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3219782523 Jul 27 06:53:30 PM PDT 24 Jul 27 06:54:55 PM PDT 24 6558707874 ps
T199 /workspace/coverage/default/29.sram_ctrl_lc_escalation.4006673672 Jul 27 06:49:20 PM PDT 24 Jul 27 06:51:11 PM PDT 24 48907310280 ps
T33 /workspace/coverage/default/18.sram_ctrl_ram_cfg.1089320022 Jul 27 06:47:18 PM PDT 24 Jul 27 06:47:21 PM PDT 24 690848365 ps
T200 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2055899122 Jul 27 06:48:31 PM PDT 24 Jul 27 06:56:40 PM PDT 24 39264724469 ps
T17 /workspace/coverage/default/39.sram_ctrl_alert_test.3977648548 Jul 27 06:51:40 PM PDT 24 Jul 27 06:51:40 PM PDT 24 47930871 ps
T201 /workspace/coverage/default/30.sram_ctrl_stress_all.3281439850 Jul 27 06:49:38 PM PDT 24 Jul 27 08:42:20 PM PDT 24 97424188595 ps
T202 /workspace/coverage/default/3.sram_ctrl_smoke.23647368 Jul 27 06:45:12 PM PDT 24 Jul 27 06:46:15 PM PDT 24 799745964 ps
T20 /workspace/coverage/default/1.sram_ctrl_sec_cm.3843487858 Jul 27 06:45:09 PM PDT 24 Jul 27 06:45:12 PM PDT 24 354860815 ps
T203 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1532766558 Jul 27 06:53:29 PM PDT 24 Jul 27 06:57:34 PM PDT 24 23428456433 ps
T140 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3690306755 Jul 27 06:51:16 PM PDT 24 Jul 27 06:55:51 PM PDT 24 12952049457 ps
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T205 /workspace/coverage/default/22.sram_ctrl_lc_escalation.3471031153 Jul 27 06:48:04 PM PDT 24 Jul 27 06:48:54 PM PDT 24 6900816513 ps
T206 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2590743525 Jul 27 06:46:15 PM PDT 24 Jul 27 06:48:29 PM PDT 24 6335403179 ps
T207 /workspace/coverage/default/10.sram_ctrl_stress_all.3188214793 Jul 27 06:46:01 PM PDT 24 Jul 27 07:38:17 PM PDT 24 475836795410 ps
T208 /workspace/coverage/default/47.sram_ctrl_lc_escalation.2435207504 Jul 27 06:53:20 PM PDT 24 Jul 27 06:54:34 PM PDT 24 41206360061 ps
T209 /workspace/coverage/default/7.sram_ctrl_stress_all.2248603440 Jul 27 06:45:39 PM PDT 24 Jul 27 08:31:01 PM PDT 24 230067251760 ps
T210 /workspace/coverage/default/47.sram_ctrl_multiple_keys.215766057 Jul 27 06:53:21 PM PDT 24 Jul 27 07:01:16 PM PDT 24 6463151633 ps
T16 /workspace/coverage/default/6.sram_ctrl_alert_test.1480109605 Jul 27 06:45:34 PM PDT 24 Jul 27 06:45:35 PM PDT 24 16213154 ps
T211 /workspace/coverage/default/22.sram_ctrl_multiple_keys.3159671079 Jul 27 06:47:55 PM PDT 24 Jul 27 07:03:06 PM PDT 24 21814400769 ps
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T213 /workspace/coverage/default/31.sram_ctrl_executable.1440221152 Jul 27 06:49:56 PM PDT 24 Jul 27 07:00:36 PM PDT 24 28266510117 ps
T77 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1518413577 Jul 27 06:45:49 PM PDT 24 Jul 27 06:46:39 PM PDT 24 1077072394 ps
T214 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1814146587 Jul 27 06:49:48 PM PDT 24 Jul 27 07:19:50 PM PDT 24 88096430589 ps
T215 /workspace/coverage/default/3.sram_ctrl_ram_cfg.3066275195 Jul 27 06:45:12 PM PDT 24 Jul 27 06:45:15 PM PDT 24 390972342 ps
T216 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2218750086 Jul 27 06:50:35 PM PDT 24 Jul 27 07:14:54 PM PDT 24 19122390119 ps
T78 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2017049472 Jul 27 06:46:45 PM PDT 24 Jul 27 06:47:04 PM PDT 24 1868761047 ps
T217 /workspace/coverage/default/49.sram_ctrl_partial_access.2984249038 Jul 27 06:53:46 PM PDT 24 Jul 27 06:54:21 PM PDT 24 3980178450 ps
T218 /workspace/coverage/default/48.sram_ctrl_ram_cfg.845925103 Jul 27 06:53:36 PM PDT 24 Jul 27 06:53:39 PM PDT 24 715566545 ps
T219 /workspace/coverage/default/30.sram_ctrl_alert_test.1018063350 Jul 27 06:49:46 PM PDT 24 Jul 27 06:49:47 PM PDT 24 79243834 ps
T220 /workspace/coverage/default/16.sram_ctrl_executable.4117014132 Jul 27 06:47:02 PM PDT 24 Jul 27 07:09:33 PM PDT 24 242998078569 ps
T221 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3932171658 Jul 27 06:45:12 PM PDT 24 Jul 27 06:48:45 PM PDT 24 32126068174 ps
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T223 /workspace/coverage/default/43.sram_ctrl_partial_access.263658573 Jul 27 06:52:12 PM PDT 24 Jul 27 06:52:16 PM PDT 24 1565357186 ps
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T226 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.310754953 Jul 27 06:53:05 PM PDT 24 Jul 27 07:01:43 PM PDT 24 19331422068 ps
T56 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4230457742 Jul 27 06:52:05 PM PDT 24 Jul 27 06:54:45 PM PDT 24 11748095971 ps
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T228 /workspace/coverage/default/14.sram_ctrl_mem_walk.1849969220 Jul 27 06:46:44 PM PDT 24 Jul 27 06:52:22 PM PDT 24 51207942953 ps
T229 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2314497958 Jul 27 06:45:19 PM PDT 24 Jul 27 06:46:39 PM PDT 24 3313892066 ps
T230 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.781721866 Jul 27 06:53:31 PM PDT 24 Jul 27 06:54:11 PM PDT 24 1126347907 ps
T231 /workspace/coverage/default/26.sram_ctrl_ram_cfg.91462215 Jul 27 06:48:56 PM PDT 24 Jul 27 06:48:59 PM PDT 24 1539111292 ps
T232 /workspace/coverage/default/27.sram_ctrl_regwen.402541914 Jul 27 06:49:03 PM PDT 24 Jul 27 07:01:52 PM PDT 24 10073092375 ps
T233 /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2065716908 Jul 27 06:49:03 PM PDT 24 Jul 27 06:55:17 PM PDT 24 27627367802 ps
T234 /workspace/coverage/default/9.sram_ctrl_smoke.2071980474 Jul 27 06:45:50 PM PDT 24 Jul 27 06:45:58 PM PDT 24 412064044 ps
T235 /workspace/coverage/default/11.sram_ctrl_smoke.2817053378 Jul 27 06:45:58 PM PDT 24 Jul 27 06:46:11 PM PDT 24 3147184637 ps
T236 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1689236378 Jul 27 06:49:21 PM PDT 24 Jul 27 06:50:52 PM PDT 24 793172149 ps
T237 /workspace/coverage/default/43.sram_ctrl_ram_cfg.345764356 Jul 27 06:52:23 PM PDT 24 Jul 27 06:52:26 PM PDT 24 716165053 ps
T238 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.230019193 Jul 27 06:51:30 PM PDT 24 Jul 27 07:23:43 PM PDT 24 14664096514 ps
T239 /workspace/coverage/default/11.sram_ctrl_multiple_keys.4041571290 Jul 27 06:45:59 PM PDT 24 Jul 27 06:54:41 PM PDT 24 9241317538 ps
T240 /workspace/coverage/default/46.sram_ctrl_alert_test.353556841 Jul 27 06:53:12 PM PDT 24 Jul 27 06:53:12 PM PDT 24 14484516 ps
T241 /workspace/coverage/default/28.sram_ctrl_executable.2319549767 Jul 27 06:49:14 PM PDT 24 Jul 27 07:08:11 PM PDT 24 23553918117 ps
T242 /workspace/coverage/default/1.sram_ctrl_alert_test.886639238 Jul 27 06:45:13 PM PDT 24 Jul 27 06:45:14 PM PDT 24 41522387 ps
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T244 /workspace/coverage/default/2.sram_ctrl_multiple_keys.3161941237 Jul 27 06:45:12 PM PDT 24 Jul 27 06:54:14 PM PDT 24 29937733840 ps
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T297 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.221552181 Jul 27 06:52:04 PM PDT 24 Jul 27 06:56:15 PM PDT 24 27887883533 ps
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T299 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2438937687 Jul 27 06:45:07 PM PDT 24 Jul 27 06:47:08 PM PDT 24 1628237419 ps
T300 /workspace/coverage/default/23.sram_ctrl_ram_cfg.3188303846 Jul 27 06:48:21 PM PDT 24 Jul 27 06:48:24 PM PDT 24 704848926 ps
T301 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3817607375 Jul 27 06:51:15 PM PDT 24 Jul 27 07:00:51 PM PDT 24 34441723207 ps
T302 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.374894175 Jul 27 06:49:30 PM PDT 24 Jul 27 06:59:41 PM PDT 24 49610863980 ps
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T307 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2738039456 Jul 27 06:52:32 PM PDT 24 Jul 27 06:54:54 PM PDT 24 13490708232 ps
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