Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	141421795	1			T1	720896		T2	9108		T3	7006
triple_byte_access	2875142	1			T2	182		T3	297		T4	2685
halfword_access	4404896	1			T2	281		T3	456		T4	4056
byte_access	6134852	1			T2	361		T3	608		T4	5380
zero_access	1829446	1			T2	92		T3	150		T4	1346

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78109222

1

T1

360448

T2

4914

T3

4284

auto[1]

78556909

1

T1

360448

T2

5110

T3

4233

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	70351356	1			T1	360448		T2	4452		T3	3517
auto[0]	triple_byte_access	1378407	1			T2	87		T3	142		T4	1349
auto[0]	halfword_access	2158557	1			T2	159		T3	241		T4	2067
auto[0]	byte_access	3139312	1			T2	172		T3	313		T4	2648
auto[0]	zero_access	1081590	1			T2	44		T3	71		T4	664
auto[1]	word_access	71070439	1			T1	360448		T2	4656		T3	3489
auto[1]	triple_byte_access	1496735	1			T2	95		T3	155		T4	1336
auto[1]	halfword_access	2246339	1			T2	122		T3	215		T4	1989
auto[1]	byte_access	2995540	1			T2	189		T3	295		T4	2732
auto[1]	zero_access	747856	1			T2	48		T3	79		T4	682