Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	345969402	1			T1	65332		T2	60748		T3	393212
instr_valid_dis	302626537	1			T1	65332		T2	60748		T3	393212
instr_en	27877506	1			T10	47558		T28	126974		T30	300260

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15140832	1			T10	108852		T30	218588		T49	108244
sram_ifetch_valid_disable	301733580	1			T1	65332		T2	60748		T3	393212
sram_ifetch_enable	29094990	1			T10	116600		T28	46028		T30	49524

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	345969402	1			T1	65332		T2	60748		T3	393212
hw_debug_en_valid_off	297110222	1			T1	65332		T2	60748		T3	393212
hw_debug_en_on	36694300	1			T10	114208		T28	29150		T30	273484

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	301733580	1			T1	65332		T2	60748		T3	393212
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	287184283	1			T1	65332		T2	60748		T3	393212
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11040066	1			T28	97754		T30	71426		T137	38572
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5193262	1			T10	67404		T30	32962		T49	43314
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2291196	1			T10	41580		T137	28462		T71	22580
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2041412	1			T30	32962		T137	9268		T146	15928
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6422386	1			T10	41448		T30	167990		T49	64930
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1565956	1			T10	19664		T137	32738		T7	99890
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1469498	1			T10	21784		T30	167990		T137	14144
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	16822982	1			T10	24140		T28	12342		T30	79638
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	9423960	1			T10	4038		T30	15290		T137	3178
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6338130	1			T28	12342		T30	64348		T137	20366

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11014486	1			T10	25774		T28	29220		T30	10246
lc_exec_en	13448932	1			T10	48620		T28	16808		T30	25856
valid_exec_dis	291363502	1			T1	65332		T2	60748		T3	393212
invalid_exec_dis	44235822	1			T10	225452		T28	46028		T30	268112