Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	143964287	1			T1	1656		T2	1490		T3	196606
triple_byte_access	2698030	1			T1	3654		T2	3453		T4	29837
halfword_access	4135745	1			T1	6854		T2	6287		T4	44238
byte_access	5771821	1			T1	12938		T2	12055		T4	58799
zero_access	1739290	1			T1	7564		T2	7089		T4	14577

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78805945

1

T1

16195

T2

15191

T3

65536

auto[1]

79503228

1

T1

16471

T2

15183

T3

131070

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	71500131	1			T1	141		T2	120		T3	65536
auto[0]	triple_byte_access	1291001	1			T1	695		T2	634		T4	15016
auto[0]	halfword_access	2023216	1			T1	2342		T2	2156		T4	22074
auto[0]	byte_access	2956722	1			T1	6871		T2	6596		T4	29365
auto[0]	zero_access	1034875	1			T1	6146		T2	5685		T4	7330
auto[1]	word_access	72464156	1			T1	1515		T2	1370		T3	131070
auto[1]	triple_byte_access	1407029	1			T1	2959		T2	2819		T4	14821
auto[1]	halfword_access	2112529	1			T1	4512		T2	4131		T4	22164
auto[1]	byte_access	2815099	1			T1	6067		T2	5459		T4	29434
auto[1]	zero_access	704415	1			T1	1418		T2	1404		T4	7247