Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	363334944	1			T1	428462		T2	196606		T3	275252
instr_valid_dis	319905185	1			T1	428462		T2	196606		T3	275252
instr_en	31185110	1			T19	412409		T21	361316		T44	220186

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12381901	1			T1	137350		T19	84916		T20	112722
sram_ifetch_valid_disable	320149516	1			T1	404097		T2	196606		T3	275252
sram_ifetch_enable	30803527	1			T1	106296		T19	393436		T20	117028

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	363334944	1			T1	428462		T2	196606		T3	275252
hw_debug_en_valid_off	318063853	1			T1	398618		T2	196606		T3	275252
hw_debug_en_on	30965419	1			T1	210504		T19	269716		T20	172532

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	320149516	1			T1	404097		T2	196606		T3	275252
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	305185691	1			T1	404097		T2	196606		T3	275252
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11049080	1			T19	134128		T21	128378		T44	115972
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5192403	1			T1	34396		T19	43408		T20	75458
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1806257	1			T1	34396		T19	29314		T20	75458
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2366060	1			T19	14094		T44	47776		T61	35868
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4912960	1			T1	102954		T19	41508		T21	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2131916	1			T1	102954		T61	156618		T72	19234
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2051576	1			T19	41508		T21	20000		T44	11806
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	12370892	1			T1	57104		T19	63624		T20	97736
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	7715546	1			T1	57104		T19	13262		T20	97736
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3316074	1			T19	50362		T21	38214		T44	44976

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	15103782	1			T19	393436		T21	212938		T44	44632
lc_exec_en	13681567	1			T1	50446		T19	164584		T20	74796
valid_exec_dis	310551089	1			T1	402855		T2	196606		T3	275252
invalid_exec_dis	43185428	1			T1	243646		T19	401928		T20	229750