Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	151864839	1			T1	196492		T2	98303		T3	125117
triple_byte_access	2733893	1			T1	11763		T3	2464		T4	100
halfword_access	4185694	1			T1	17361		T3	3763		T4	135
byte_access	5822212	1			T1	23646		T3	5056		T4	191
zero_access	1728694	1			T1	5844		T3	1226		T4	44

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82980001

1

T1

101989

T2

32768

T3

68653

auto[1]

83355331

1

T1

100364

T2

65535

T3

68973

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75618557	1			T1	989696		T2	32768		T3	62449
auto[0]	triple_byte_access	1312090	1			T1	5994		T3	1224		T4	53
auto[0]	halfword_access	2053569	1			T1	9022		T3	1923		T4	61
auto[0]	byte_access	2978219	1			T1	12167		T3	2442		T4	93
auto[0]	zero_access	1017566	1			T1	3018		T3	615		T4	24
auto[1]	word_access	76246282	1			T1	975230		T2	65535		T3	62668
auto[1]	triple_byte_access	1421803	1			T1	5769		T3	1240		T4	47
auto[1]	halfword_access	2132125	1			T1	8339		T3	1840		T4	74
auto[1]	byte_access	2843993	1			T1	11479		T3	2614		T4	98
auto[1]	zero_access	711128	1			T1	2826		T3	611		T4	20