SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 0 | 9 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
csr_exec_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
en_sram_ifetch_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
lc_hw_debug_en_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
executable_cross | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
instr_invalid_dis | 357627262 | 1 | T2 | 20078 | T3 | 2222 | T4 | 13178 | ||||
instr_valid_dis | 317383753 | 1 | T2 | 20078 | T3 | 2222 | T4 | 13178 | ||||
instr_en | 21645666 | 1 | T6 | 140346 | T8 | 235146 | T11 | 640408 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
sram_ifetch_invalid_disable | 12368092 | 1 | T6 | 65316 | T8 | 131442 | T11 | 375906 | ||||
sram_ifetch_valid_disable | 312345520 | 1 | T2 | 20078 | T3 | 2222 | T4 | 13178 | ||||
sram_ifetch_enable | 32913650 | 1 | T6 | 126672 | T8 | 202104 | T11 | 194770 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | 357627262 | 1 | T2 | 20078 | T3 | 2222 | T4 | 13178 | ||||
hw_debug_en_valid_off | 310660332 | 1 | T2 | 20078 | T3 | 2222 | T4 | 13178 | ||||
hw_debug_en_on | 30918756 | 1 | T6 | 72868 | T8 | 66586 | T11 | 197630 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 16 | 0 | 16 | 100.00 | |
Automatically Generated Cross Bins | 12 | 0 | 12 | 100.00 | |
User Defined Cross Bins | 4 | 0 | 4 | 100.00 |
lc_hw_debug_en_cp | en_sram_ifetch_cp | csr_exec_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_invalid_dis | 312345520 | 1 | T2 | 20078 | T3 | 2222 | T4 | 13178 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_valid_dis | 298176130 | 1 | T2 | 20078 | T3 | 2222 | T4 | 13178 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_en | 7898097 | 1 | T6 | 38310 | T8 | 63958 | T11 | 122444 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_invalid_dis | 5750266 | 1 | T6 | 13400 | T8 | 86702 | T11 | 47852 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_valid_dis | 2336326 | 1 | T6 | 13400 | T8 | 24596 | T18 | 70902 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_en | 1065630 | 1 | T8 | 62106 | T11 | 47852 | T148 | 13708 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_invalid_dis | 4330908 | 1 | T6 | 22902 | T11 | 26574 | T18 | 42802 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_valid_dis | 2246888 | 1 | T18 | 42802 | T19 | 20000 | T141 | 132 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_en | 1302302 | 1 | T6 | 22902 | T11 | 26574 | T74 | 18678 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_invalid_dis | 13208768 | 1 | T8 | 45884 | T11 | 35196 | T18 | 48782 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_valid_dis | 6995888 | 1 | T8 | 20000 | T18 | 48782 | T19 | 44154 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_en | 3478370 | 1 | T8 | 25884 | T11 | 35196 | T74 | 481136 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
csr_exec_en | 10573397 | 1 | T6 | 66064 | T8 | 79028 | T11 | 148024 | ||||
lc_exec_en | 13379080 | 1 | T6 | 49966 | T8 | 20702 | T11 | 135860 | ||||
valid_exec_dis | 304401877 | 1 | T2 | 20078 | T3 | 2222 | T4 | 13178 | ||||
invalid_exec_dis | 45281742 | 1 | T6 | 191988 | T8 | 333546 | T11 | 570676 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |