Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Total tests in report: 1034

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
75.35	75.35	93.05	93.05	76.78	76.78	86.71	86.71	33.33	33.33	85.55	85.55	93.57	93.57	58.50	58.50	/workspace/coverage/default/47.sram_ctrl_stress_all.3712435211
92.18	16.83	98.28	5.23	85.78	9.00	88.36	1.65	100.00	66.67	93.84	8.29	95.47	1.90	83.55	25.05	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1914327103
93.88	1.70	98.77	0.49	87.56	1.78	95.63	7.27	100.00	0.00	94.79	0.95	96.49	1.02	83.91	0.37	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1029685464
94.85	0.97	98.94	0.16	88.15	0.59	95.83	0.21	100.00	0.00	95.50	0.71	96.49	0.00	89.03	5.12	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3558117888
95.52	0.67	98.94	0.00	88.15	0.00	97.07	1.24	100.00	0.00	95.50	0.00	96.49	0.00	92.50	3.47	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3300706824
96.10	0.57	99.10	0.16	89.93	1.78	97.49	0.41	100.00	0.00	96.21	0.71	97.08	0.58	92.87	0.37	/workspace/coverage/default/0.sram_ctrl_sec_cm.3829281524
96.37	0.28	99.10	0.00	90.05	0.12	97.49	0.00	100.00	0.00	96.21	0.00	97.81	0.73	93.97	1.10	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2163651542
96.63	0.25	99.10	0.00	90.76	0.71	98.00	0.52	100.00	0.00	96.21	0.00	97.81	0.00	94.52	0.55	/workspace/coverage/default/12.sram_ctrl_alert_test.1969588169
96.83	0.20	99.10	0.00	90.76	0.00	98.07	0.07	100.00	0.00	96.21	0.00	99.12	1.32	94.52	0.00	/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3728229566
96.99	0.16	99.18	0.08	90.76	0.00	99.14	1.07	100.00	0.00	96.21	0.00	99.12	0.00	94.52	0.00	/workspace/coverage/default/36.sram_ctrl_ram_cfg.4219114311
97.12	0.13	99.18	0.00	90.76	0.00	99.69	0.55	100.00	0.00	96.21	0.00	99.12	0.00	94.88	0.37	/workspace/coverage/default/49.sram_ctrl_executable.3945506451
97.25	0.13	99.18	0.00	90.76	0.00	99.69	0.00	100.00	0.00	96.21	0.00	99.12	0.00	95.80	0.91	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.821977368
97.36	0.10	99.18	0.00	90.76	0.00	99.69	0.00	100.00	0.00	96.21	0.00	99.12	0.00	96.53	0.73	/workspace/coverage/default/0.sram_ctrl_stress_all.3648263173
97.43	0.08	99.18	0.00	90.76	0.00	99.69	0.00	100.00	0.00	96.21	0.00	99.12	0.00	97.07	0.55	/workspace/coverage/default/44.sram_ctrl_stress_all.840492454
97.47	0.03	99.18	0.00	91.00	0.24	99.69	0.00	100.00	0.00	96.21	0.00	99.12	0.00	97.07	0.00	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2329211066
97.49	0.03	99.18	0.00	91.00	0.00	99.69	0.00	100.00	0.00	96.21	0.00	99.12	0.00	97.26	0.18	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1498510958
97.52	0.03	99.18	0.00	91.00	0.00	99.69	0.00	100.00	0.00	96.21	0.00	99.12	0.00	97.44	0.18	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.847421541
97.52	0.01	99.18	0.00	91.00	0.00	99.72	0.03	100.00	0.00	96.21	0.00	99.12	0.00	97.44	0.00	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1991654100

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.949370418
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1919973742
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1822090414
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1816676686
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2158947016
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2505583132
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1675826931
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1124532669
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3558431769
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1528908154
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2067104354
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2479574967
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3664098733
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1119310767
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3908623140
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2651529132
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1883719475
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2428113202
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2284930153
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3392188797
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.46098989
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.187052519
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.526756557
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1279179604
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3916778358
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.722139646
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2668465294
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1613857189
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3078055800
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4077814195
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2995517786
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1047998194
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1757344984
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3755701692
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3724519034
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.21270050
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.118655797
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4282493399
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1738410318
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3345390328
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2437506098
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2406520917
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1784459511
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2099222614
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4238763472
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1636990631
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.304387385
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1314652381
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4271933515
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2608482552
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.73988529
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2586952492
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3785352412
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2536228035
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2950791611
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2031543997
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3639168159
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1827711794
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1385723960
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.233135227
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.113673811
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3053317612
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1998690258
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1988833283
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2438300726
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.197755351
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.222192699
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2148286347
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1613251578
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3694592133
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.480719463
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2532671293
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.332834656
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.582181686
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.220291859
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2497924123
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3997435758
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.81420077
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1514096551
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3511674831
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4133298345
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2652014158
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3615408751
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3865168439
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1260367920
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1247220074
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3867173429
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2492647555
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3694075859
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2712121507
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3271801158
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2288450810
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.493735162
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1245284077
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.995856315
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3406380518
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3865987962
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1798520587
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2254279503
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1149319925
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3585955023
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3617527243
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2037712155
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2754663380
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.875911106
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2241630850
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3440487955
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3376444374
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.627053836
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3906045442
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2635426377
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2744739150
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3751279947
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1981880551
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1727669727
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2243369193
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4168901636
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.166617608
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1045757317
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4247400286
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1982232547
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3592093682
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4197197661
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2765026030
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2006825449
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2801050578
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1235800945
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2780915346
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.822086181
/workspace/coverage/default/0.sram_ctrl_alert_test.2873908673
/workspace/coverage/default/0.sram_ctrl_bijection.653394461
/workspace/coverage/default/0.sram_ctrl_executable.2452277394
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2762899174
/workspace/coverage/default/0.sram_ctrl_max_throughput.1473865834
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2020761180
/workspace/coverage/default/0.sram_ctrl_mem_walk.348659220
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1043988265
/workspace/coverage/default/0.sram_ctrl_partial_access.3668040428
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2018534698
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1996663145
/workspace/coverage/default/0.sram_ctrl_regwen.188513973
/workspace/coverage/default/0.sram_ctrl_smoke.889364731
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1649296232
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3034524162
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3522072323
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3756497454
/workspace/coverage/default/1.sram_ctrl_alert_test.3946014518
/workspace/coverage/default/1.sram_ctrl_bijection.3904929897
/workspace/coverage/default/1.sram_ctrl_executable.513821575
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1870639779
/workspace/coverage/default/1.sram_ctrl_max_throughput.3418744680
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3547709565
/workspace/coverage/default/1.sram_ctrl_mem_walk.1866242251
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3319288913
/workspace/coverage/default/1.sram_ctrl_partial_access.460122035
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3577182682
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2759750135
/workspace/coverage/default/1.sram_ctrl_regwen.827185771
/workspace/coverage/default/1.sram_ctrl_sec_cm.2573231591
/workspace/coverage/default/1.sram_ctrl_smoke.3439414796
/workspace/coverage/default/1.sram_ctrl_stress_all.3470796449
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1345461381
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.476327269
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4073505160
/workspace/coverage/default/10.sram_ctrl_alert_test.3219540084
/workspace/coverage/default/10.sram_ctrl_bijection.1224216007
/workspace/coverage/default/10.sram_ctrl_executable.2048866898
/workspace/coverage/default/10.sram_ctrl_lc_escalation.1952068931
/workspace/coverage/default/10.sram_ctrl_max_throughput.3854824118
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.889196893
/workspace/coverage/default/10.sram_ctrl_mem_walk.2032650062
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1940093617
/workspace/coverage/default/10.sram_ctrl_partial_access.1264113267
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1666647185
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1333313390
/workspace/coverage/default/10.sram_ctrl_regwen.4272564966
/workspace/coverage/default/10.sram_ctrl_smoke.2082250057
/workspace/coverage/default/10.sram_ctrl_stress_all.2447568871
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.271948276
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1274890079
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.987051212
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1873578057
/workspace/coverage/default/11.sram_ctrl_alert_test.2161909905
/workspace/coverage/default/11.sram_ctrl_bijection.927589239
/workspace/coverage/default/11.sram_ctrl_executable.3750896423
/workspace/coverage/default/11.sram_ctrl_lc_escalation.566909260
/workspace/coverage/default/11.sram_ctrl_max_throughput.1905784673
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3727678559
/workspace/coverage/default/11.sram_ctrl_mem_walk.3927257243
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3933422926
/workspace/coverage/default/11.sram_ctrl_partial_access.132641889
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.800538168
/workspace/coverage/default/11.sram_ctrl_ram_cfg.264096493
/workspace/coverage/default/11.sram_ctrl_regwen.1114048858
/workspace/coverage/default/11.sram_ctrl_smoke.3569856062
/workspace/coverage/default/11.sram_ctrl_stress_all.1876159638
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3628164176
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/workspace/coverage/default/42.sram_ctrl_max_throughput.1092252532
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.4049245626
/workspace/coverage/default/42.sram_ctrl_mem_walk.3984292945
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2248661507
/workspace/coverage/default/42.sram_ctrl_partial_access.1944309020
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3043336874
/workspace/coverage/default/42.sram_ctrl_ram_cfg.4294888963
/workspace/coverage/default/42.sram_ctrl_regwen.892114617
/workspace/coverage/default/42.sram_ctrl_smoke.3074334533
/workspace/coverage/default/42.sram_ctrl_stress_all.78238513
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3608596712
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.2142969221
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3461877346
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.4214833044
/workspace/coverage/default/43.sram_ctrl_alert_test.3430831343
/workspace/coverage/default/43.sram_ctrl_bijection.3240024502
/workspace/coverage/default/43.sram_ctrl_executable.265299647
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3891814889
/workspace/coverage/default/43.sram_ctrl_max_throughput.3621831163
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2758671100
/workspace/coverage/default/43.sram_ctrl_mem_walk.3615363864
/workspace/coverage/default/43.sram_ctrl_multiple_keys.533350163
/workspace/coverage/default/43.sram_ctrl_partial_access.2275104822
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2744814715
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1213593487
/workspace/coverage/default/43.sram_ctrl_regwen.57465463
/workspace/coverage/default/43.sram_ctrl_smoke.250035153
/workspace/coverage/default/43.sram_ctrl_stress_all.2523726084
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1726938799
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4072572627
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1846289666
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2776325123
/workspace/coverage/default/44.sram_ctrl_alert_test.517358047
/workspace/coverage/default/44.sram_ctrl_bijection.4116403474
/workspace/coverage/default/44.sram_ctrl_executable.1099762146
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2815819699
/workspace/coverage/default/44.sram_ctrl_max_throughput.998837665
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2361750399
/workspace/coverage/default/44.sram_ctrl_mem_walk.1376403477
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4205002113
/workspace/coverage/default/44.sram_ctrl_partial_access.569535738
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2384354953
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2457398134
/workspace/coverage/default/44.sram_ctrl_regwen.150065828
/workspace/coverage/default/44.sram_ctrl_smoke.3265219561
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3121368018
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.190146358
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.319831809
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1044674950
/workspace/coverage/default/45.sram_ctrl_alert_test.4188406225
/workspace/coverage/default/45.sram_ctrl_bijection.425673069
/workspace/coverage/default/45.sram_ctrl_executable.2862696182
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2043126632
/workspace/coverage/default/45.sram_ctrl_max_throughput.3654268719
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1672607044
/workspace/coverage/default/45.sram_ctrl_mem_walk.693437098
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2257939707
/workspace/coverage/default/45.sram_ctrl_partial_access.3639802459
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2848537880
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1245593886
/workspace/coverage/default/45.sram_ctrl_regwen.3646073676
/workspace/coverage/default/45.sram_ctrl_smoke.775088848
/workspace/coverage/default/45.sram_ctrl_stress_all.1026517716
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.759852231
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3666281217
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1822611387
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.720494642
/workspace/coverage/default/46.sram_ctrl_alert_test.1967315520
/workspace/coverage/default/46.sram_ctrl_bijection.1502157659
/workspace/coverage/default/46.sram_ctrl_executable.1204330433
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2981113346
/workspace/coverage/default/46.sram_ctrl_max_throughput.3159006659
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1430370822
/workspace/coverage/default/46.sram_ctrl_mem_walk.2514342073
/workspace/coverage/default/46.sram_ctrl_multiple_keys.3291045299
/workspace/coverage/default/46.sram_ctrl_partial_access.135633634
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2492928411
/workspace/coverage/default/46.sram_ctrl_ram_cfg.92486211
/workspace/coverage/default/46.sram_ctrl_regwen.3504321758
/workspace/coverage/default/46.sram_ctrl_smoke.2346720130
/workspace/coverage/default/46.sram_ctrl_stress_all.3169395324
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2911215898
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2395141242
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1358364217
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1801832205
/workspace/coverage/default/47.sram_ctrl_alert_test.3142900459
/workspace/coverage/default/47.sram_ctrl_bijection.1421198811
/workspace/coverage/default/47.sram_ctrl_executable.3165517861
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1753657678
/workspace/coverage/default/47.sram_ctrl_max_throughput.2168752660
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3928173727
/workspace/coverage/default/47.sram_ctrl_mem_walk.2618543996
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1662450754
/workspace/coverage/default/47.sram_ctrl_partial_access.2565821821
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2827344822
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2115413802
/workspace/coverage/default/47.sram_ctrl_regwen.2336183482
/workspace/coverage/default/47.sram_ctrl_smoke.755430212
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3545625365
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.4190696632
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1107511039
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.925256976
/workspace/coverage/default/48.sram_ctrl_alert_test.3152631549
/workspace/coverage/default/48.sram_ctrl_bijection.983496443
/workspace/coverage/default/48.sram_ctrl_executable.1399983902
/workspace/coverage/default/48.sram_ctrl_lc_escalation.823793319
/workspace/coverage/default/48.sram_ctrl_max_throughput.715885664
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.447659089
/workspace/coverage/default/48.sram_ctrl_mem_walk.317539335
/workspace/coverage/default/48.sram_ctrl_multiple_keys.493923886
/workspace/coverage/default/48.sram_ctrl_partial_access.4009030169
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.41277593
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2429012564
/workspace/coverage/default/48.sram_ctrl_regwen.1414903425
/workspace/coverage/default/48.sram_ctrl_smoke.4224770982
/workspace/coverage/default/48.sram_ctrl_stress_all.3564319136
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.544717305
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.617984319
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2255014253
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2661823972
/workspace/coverage/default/49.sram_ctrl_alert_test.162441939
/workspace/coverage/default/49.sram_ctrl_bijection.1518407484
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1134756094
/workspace/coverage/default/49.sram_ctrl_max_throughput.2032385109
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2756663188
/workspace/coverage/default/49.sram_ctrl_mem_walk.1009450323
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1237701360
/workspace/coverage/default/49.sram_ctrl_partial_access.1878099898
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1221258028
/workspace/coverage/default/49.sram_ctrl_regwen.590887185
/workspace/coverage/default/49.sram_ctrl_smoke.36137994
/workspace/coverage/default/49.sram_ctrl_stress_all.2840847970
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3870275489
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.685323945
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.74429973
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.275921285
/workspace/coverage/default/5.sram_ctrl_alert_test.2589448706
/workspace/coverage/default/5.sram_ctrl_bijection.2207733886
/workspace/coverage/default/5.sram_ctrl_executable.1281265908
/workspace/coverage/default/5.sram_ctrl_lc_escalation.377158301
/workspace/coverage/default/5.sram_ctrl_max_throughput.3566329873
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1697430382
/workspace/coverage/default/5.sram_ctrl_mem_walk.3612724084
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2619899068
/workspace/coverage/default/5.sram_ctrl_partial_access.2375313190
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3380634451
/workspace/coverage/default/5.sram_ctrl_ram_cfg.699009131
/workspace/coverage/default/5.sram_ctrl_regwen.1078123279
/workspace/coverage/default/5.sram_ctrl_smoke.3086495475
/workspace/coverage/default/5.sram_ctrl_stress_all.1384366742
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3634270316
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3275667529
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.558200225
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3625874464
/workspace/coverage/default/6.sram_ctrl_alert_test.2675357993
/workspace/coverage/default/6.sram_ctrl_bijection.2408571404
/workspace/coverage/default/6.sram_ctrl_executable.3432886853
/workspace/coverage/default/6.sram_ctrl_lc_escalation.251363242
/workspace/coverage/default/6.sram_ctrl_max_throughput.1580610561
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3678182936
/workspace/coverage/default/6.sram_ctrl_mem_walk.2157486624
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2290737850
/workspace/coverage/default/6.sram_ctrl_partial_access.3980489077
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3880873088
/workspace/coverage/default/6.sram_ctrl_ram_cfg.270182770
/workspace/coverage/default/6.sram_ctrl_regwen.2908400722
/workspace/coverage/default/6.sram_ctrl_smoke.4056134798
/workspace/coverage/default/6.sram_ctrl_stress_all.3969588766
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.619993975
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1437153867
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.738072213
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3619484350
/workspace/coverage/default/7.sram_ctrl_alert_test.1625105271
/workspace/coverage/default/7.sram_ctrl_bijection.2619331002
/workspace/coverage/default/7.sram_ctrl_executable.572641750
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3672731590
/workspace/coverage/default/7.sram_ctrl_max_throughput.2210955012
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1035200512
/workspace/coverage/default/7.sram_ctrl_mem_walk.2834493641
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3151948120
/workspace/coverage/default/7.sram_ctrl_partial_access.1612708149
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1782963377
/workspace/coverage/default/7.sram_ctrl_ram_cfg.635265511
/workspace/coverage/default/7.sram_ctrl_regwen.32460845
/workspace/coverage/default/7.sram_ctrl_smoke.3251388761
/workspace/coverage/default/7.sram_ctrl_stress_all.3354847038
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.4282244572
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2328753567
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.578885107
/workspace/coverage/default/8.sram_ctrl_alert_test.1067121387
/workspace/coverage/default/8.sram_ctrl_bijection.1277996985
/workspace/coverage/default/8.sram_ctrl_executable.3496355645
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1350778924
/workspace/coverage/default/8.sram_ctrl_max_throughput.1485195692
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1589590946
/workspace/coverage/default/8.sram_ctrl_mem_walk.4231059971
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3647207583
/workspace/coverage/default/8.sram_ctrl_partial_access.3281233689
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.575026467
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1357951387
/workspace/coverage/default/8.sram_ctrl_smoke.1641042541
/workspace/coverage/default/8.sram_ctrl_stress_all.880021854
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.301820818
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3321075006
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2360996785
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3499949166
/workspace/coverage/default/9.sram_ctrl_alert_test.760605655
/workspace/coverage/default/9.sram_ctrl_bijection.1739026746
/workspace/coverage/default/9.sram_ctrl_executable.1168212247
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2434890666
/workspace/coverage/default/9.sram_ctrl_max_throughput.716913181
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1128052349
/workspace/coverage/default/9.sram_ctrl_mem_walk.940192155
/workspace/coverage/default/9.sram_ctrl_multiple_keys.702379872
/workspace/coverage/default/9.sram_ctrl_partial_access.2400326467
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.188414287
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1665597728
/workspace/coverage/default/9.sram_ctrl_regwen.820298161
/workspace/coverage/default/9.sram_ctrl_smoke.1738982688
/workspace/coverage/default/9.sram_ctrl_stress_all.101139020
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1484066667
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.532269403
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.672391730

Total test records in report: 1034

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/14.sram_ctrl_alert_test.178970425	Jul 30 06:47:39 PM PDT 24	Jul 30 06:47:40 PM PDT 24	11448261 ps
T2	/workspace/coverage/default/40.sram_ctrl_smoke.1471960041	Jul 30 06:50:02 PM PDT 24	Jul 30 06:52:23 PM PDT 24	782691050 ps
T3	/workspace/coverage/default/43.sram_ctrl_smoke.250035153	Jul 30 06:50:27 PM PDT 24	Jul 30 06:50:34 PM PDT 24	715447311 ps
T4	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1846289666	Jul 30 06:50:27 PM PDT 24	Jul 30 06:51:07 PM PDT 24	1280752576 ps
T5	/workspace/coverage/default/48.sram_ctrl_multiple_keys.493923886	Jul 30 06:51:10 PM PDT 24	Jul 30 07:23:44 PM PDT 24	102814931246 ps
T10	/workspace/coverage/default/38.sram_ctrl_max_throughput.3083859847	Jul 30 06:49:39 PM PDT 24	Jul 30 06:49:53 PM PDT 24	3055360872 ps
T6	/workspace/coverage/default/49.sram_ctrl_executable.3945506451	Jul 30 06:51:31 PM PDT 24	Jul 30 07:04:07 PM PDT 24	69481341990 ps
T7	/workspace/coverage/default/38.sram_ctrl_lc_escalation.3735754133	Jul 30 06:49:40 PM PDT 24	Jul 30 06:50:50 PM PDT 24	44563848292 ps
T8	/workspace/coverage/default/47.sram_ctrl_stress_all.3712435211	Jul 30 06:51:10 PM PDT 24	Jul 30 08:15:21 PM PDT 24	212999972653 ps
T11	/workspace/coverage/default/33.sram_ctrl_stress_all.1413127951	Jul 30 06:49:00 PM PDT 24	Jul 30 07:18:12 PM PDT 24	37999413469 ps
T39	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4091963188	Jul 30 06:47:24 PM PDT 24	Jul 30 06:49:37 PM PDT 24	5218327908 ps
T40	/workspace/coverage/default/28.sram_ctrl_partial_access.3125417331	Jul 30 06:48:21 PM PDT 24	Jul 30 06:49:49 PM PDT 24	934685588 ps
T18	/workspace/coverage/default/17.sram_ctrl_regwen.1190944551	Jul 30 06:47:47 PM PDT 24	Jul 30 07:01:25 PM PDT 24	6982794429 ps
T41	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3499949166	Jul 30 06:47:12 PM PDT 24	Jul 30 07:04:22 PM PDT 24	10468158794 ps
T20	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3625874464	Jul 30 06:47:01 PM PDT 24	Jul 30 07:02:37 PM PDT 24	24485639212 ps
T21	/workspace/coverage/default/18.sram_ctrl_stress_all.155804649	Jul 30 06:47:44 PM PDT 24	Jul 30 07:45:45 PM PDT 24	457678071775 ps
T71	/workspace/coverage/default/11.sram_ctrl_max_throughput.1905784673	Jul 30 06:47:19 PM PDT 24	Jul 30 06:48:34 PM PDT 24	2974654706 ps
T42	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1991654100	Jul 30 06:47:41 PM PDT 24	Jul 30 06:56:50 PM PDT 24	16847140908 ps
T9	/workspace/coverage/default/37.sram_ctrl_lc_escalation.2000272439	Jul 30 06:49:32 PM PDT 24	Jul 30 06:50:19 PM PDT 24	7447881616 ps
T89	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2615928769	Jul 30 06:47:38 PM PDT 24	Jul 30 06:49:59 PM PDT 24	1790949243 ps
T90	/workspace/coverage/default/31.sram_ctrl_partial_access.1273108609	Jul 30 06:48:40 PM PDT 24	Jul 30 06:48:44 PM PDT 24	1446618092 ps
T19	/workspace/coverage/default/0.sram_ctrl_stress_all.3648263173	Jul 30 06:47:07 PM PDT 24	Jul 30 07:02:23 PM PDT 24	48400522383 ps
T91	/workspace/coverage/default/43.sram_ctrl_partial_access.2275104822	Jul 30 06:50:26 PM PDT 24	Jul 30 06:51:04 PM PDT 24	2901457136 ps
T73	/workspace/coverage/default/28.sram_ctrl_lc_escalation.1672045679	Jul 30 06:48:23 PM PDT 24	Jul 30 06:49:24 PM PDT 24	9132050456 ps
T43	/workspace/coverage/default/5.sram_ctrl_mem_walk.3612724084	Jul 30 06:47:02 PM PDT 24	Jul 30 06:50:13 PM PDT 24	64131845195 ps
T53	/workspace/coverage/default/15.sram_ctrl_max_throughput.3705660750	Jul 30 06:47:50 PM PDT 24	Jul 30 06:49:06 PM PDT 24	2951193611 ps
T12	/workspace/coverage/default/12.sram_ctrl_alert_test.1969588169	Jul 30 06:47:43 PM PDT 24	Jul 30 06:47:43 PM PDT 24	12615429 ps
T13	/workspace/coverage/default/8.sram_ctrl_alert_test.1067121387	Jul 30 06:47:13 PM PDT 24	Jul 30 06:47:14 PM PDT 24	43904749 ps
T54	/workspace/coverage/default/48.sram_ctrl_smoke.4224770982	Jul 30 06:51:09 PM PDT 24	Jul 30 06:51:26 PM PDT 24	518398655 ps
T14	/workspace/coverage/default/39.sram_ctrl_alert_test.3011287821	Jul 30 06:50:02 PM PDT 24	Jul 30 06:50:03 PM PDT 24	54546964 ps
T55	/workspace/coverage/default/33.sram_ctrl_smoke.1115379887	Jul 30 06:48:54 PM PDT 24	Jul 30 06:50:37 PM PDT 24	2734807346 ps
T56	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.1029685464	Jul 30 06:47:49 PM PDT 24	Jul 30 06:48:52 PM PDT 24	1002528905 ps
T25	/workspace/coverage/default/36.sram_ctrl_ram_cfg.4219114311	Jul 30 06:49:28 PM PDT 24	Jul 30 06:49:31 PM PDT 24	352115062 ps
T22	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3364422742	Jul 30 06:47:47 PM PDT 24	Jul 30 06:48:18 PM PDT 24	3833446959 ps
T79	/workspace/coverage/default/3.sram_ctrl_multiple_keys.2794983763	Jul 30 06:47:05 PM PDT 24	Jul 30 07:07:22 PM PDT 24	11004665682 ps
T74	/workspace/coverage/default/29.sram_ctrl_stress_all.987971862	Jul 30 06:48:28 PM PDT 24	Jul 30 08:48:00 PM PDT 24	63226382627 ps
T26	/workspace/coverage/default/38.sram_ctrl_ram_cfg.3391994609	Jul 30 06:49:40 PM PDT 24	Jul 30 06:49:43 PM PDT 24	349425510 ps
T44	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.889196893	Jul 30 06:47:27 PM PDT 24	Jul 30 06:48:53 PM PDT 24	2685753637 ps
T61	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2255014253	Jul 30 06:51:14 PM PDT 24	Jul 30 06:51:37 PM PDT 24	1208125608 ps
T62	/workspace/coverage/default/4.sram_ctrl_lc_escalation.4291638244	Jul 30 06:47:15 PM PDT 24	Jul 30 06:48:06 PM PDT 24	31231063400 ps
T63	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3300706824	Jul 30 06:51:26 PM PDT 24	Jul 30 06:56:48 PM PDT 24	13939594776 ps
T64	/workspace/coverage/default/47.sram_ctrl_lc_escalation.1753657678	Jul 30 06:51:07 PM PDT 24	Jul 30 06:52:58 PM PDT 24	38127902474 ps
T65	/workspace/coverage/default/49.sram_ctrl_partial_access.1878099898	Jul 30 06:51:23 PM PDT 24	Jul 30 06:53:02 PM PDT 24	3932911381 ps
T45	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.447659089	Jul 30 06:51:20 PM PDT 24	Jul 30 06:52:43 PM PDT 24	3154886218 ps
T66	/workspace/coverage/default/35.sram_ctrl_max_throughput.4023993486	Jul 30 06:49:12 PM PDT 24	Jul 30 06:49:55 PM PDT 24	4530945671 ps
T48	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.162979287	Jul 30 06:49:06 PM PDT 24	Jul 30 06:50:33 PM PDT 24	5235348230 ps
T67	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.517736104	Jul 30 06:48:42 PM PDT 24	Jul 30 06:49:46 PM PDT 24	5084051067 ps
T27	/workspace/coverage/default/42.sram_ctrl_ram_cfg.4294888963	Jul 30 06:50:21 PM PDT 24	Jul 30 06:50:24 PM PDT 24	1530804481 ps
T110	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.343168157	Jul 30 06:47:51 PM PDT 24	Jul 30 06:51:23 PM PDT 24	15655442418 ps
T145	/workspace/coverage/default/16.sram_ctrl_multiple_keys.846829995	Jul 30 06:47:48 PM PDT 24	Jul 30 07:07:20 PM PDT 24	35959417789 ps
T23	/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1914327103	Jul 30 06:49:07 PM PDT 24	Jul 30 06:50:08 PM PDT 24	20918508648 ps
T141	/workspace/coverage/default/43.sram_ctrl_regwen.57465463	Jul 30 06:50:30 PM PDT 24	Jul 30 07:10:39 PM PDT 24	17705175462 ps
T149	/workspace/coverage/default/44.sram_ctrl_ram_cfg.2457398134	Jul 30 06:50:41 PM PDT 24	Jul 30 06:50:44 PM PDT 24	360867665 ps
T24	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1833208987	Jul 30 06:47:40 PM PDT 24	Jul 30 06:47:47 PM PDT 24	180289295 ps
T123	/workspace/coverage/default/7.sram_ctrl_stress_all.3354847038	Jul 30 06:47:11 PM PDT 24	Jul 30 07:14:26 PM PDT 24	168469799682 ps
T124	/workspace/coverage/default/7.sram_ctrl_executable.572641750	Jul 30 06:47:00 PM PDT 24	Jul 30 07:09:28 PM PDT 24	10569672534 ps
T95	/workspace/coverage/default/48.sram_ctrl_access_during_key_req.925256976	Jul 30 06:51:18 PM PDT 24	Jul 30 07:13:28 PM PDT 24	30002410811 ps
T111	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1629035126	Jul 30 06:47:47 PM PDT 24	Jul 30 06:54:00 PM PDT 24	29327720783 ps
T125	/workspace/coverage/default/29.sram_ctrl_bijection.1976403107	Jul 30 06:48:23 PM PDT 24	Jul 30 07:23:04 PM PDT 24	317735170136 ps
T126	/workspace/coverage/default/22.sram_ctrl_multiple_keys.3505332273	Jul 30 06:47:50 PM PDT 24	Jul 30 06:48:52 PM PDT 24	8307951425 ps
T127	/workspace/coverage/default/12.sram_ctrl_lc_escalation.3912417968	Jul 30 06:47:33 PM PDT 24	Jul 30 06:48:02 PM PDT 24	3896022429 ps
T49	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1035200512	Jul 30 06:47:03 PM PDT 24	Jul 30 06:49:34 PM PDT 24	4948585714 ps
T128	/workspace/coverage/default/5.sram_ctrl_lc_escalation.377158301	Jul 30 06:47:14 PM PDT 24	Jul 30 06:48:13 PM PDT 24	42170204867 ps
T112	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.1824312462	Jul 30 06:48:13 PM PDT 24	Jul 30 06:50:23 PM PDT 24	6378131355 ps
T150	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1196844905	Jul 30 06:47:06 PM PDT 24	Jul 30 06:49:09 PM PDT 24	1641916314 ps
T50	/workspace/coverage/default/45.sram_ctrl_mem_walk.693437098	Jul 30 06:50:48 PM PDT 24	Jul 30 06:53:51 PM PDT 24	37512965963 ps
T51	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2662992900	Jul 30 06:48:57 PM PDT 24	Jul 30 06:49:27 PM PDT 24	4177884658 ps
T151	/workspace/coverage/default/27.sram_ctrl_partial_access.3031790988	Jul 30 06:48:14 PM PDT 24	Jul 30 06:48:32 PM PDT 24	2127872803 ps
T113	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.154815921	Jul 30 06:48:23 PM PDT 24	Jul 30 06:52:39 PM PDT 24	47431494203 ps
T52	/workspace/coverage/default/34.sram_ctrl_mem_walk.616705450	Jul 30 06:49:03 PM PDT 24	Jul 30 06:51:54 PM PDT 24	9046768510 ps
T152	/workspace/coverage/default/24.sram_ctrl_bijection.1571848686	Jul 30 06:47:48 PM PDT 24	Jul 30 07:00:43 PM PDT 24	11397953286 ps
T153	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1053447476	Jul 30 06:47:52 PM PDT 24	Jul 30 06:49:47 PM PDT 24	1597814823 ps
T142	/workspace/coverage/default/0.sram_ctrl_regwen.188513973	Jul 30 06:47:09 PM PDT 24	Jul 30 06:59:36 PM PDT 24	2886238519 ps
T154	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.672391730	Jul 30 06:47:12 PM PDT 24	Jul 30 06:49:09 PM PDT 24	806328098 ps
T155	/workspace/coverage/default/35.sram_ctrl_bijection.1003154679	Jul 30 06:49:07 PM PDT 24	Jul 30 07:07:55 PM PDT 24	249200819650 ps
T156	/workspace/coverage/default/3.sram_ctrl_regwen.2189917707	Jul 30 06:47:04 PM PDT 24	Jul 30 06:52:04 PM PDT 24	22145166676 ps
T157	/workspace/coverage/default/25.sram_ctrl_max_throughput.2160637383	Jul 30 06:47:56 PM PDT 24	Jul 30 06:48:16 PM PDT 24	1602933806 ps
T114	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.587157121	Jul 30 06:47:38 PM PDT 24	Jul 30 06:56:30 PM PDT 24	32005687321 ps
T158	/workspace/coverage/default/2.sram_ctrl_mem_walk.2545971384	Jul 30 06:47:03 PM PDT 24	Jul 30 06:50:23 PM PDT 24	147899118148 ps
T159	/workspace/coverage/default/48.sram_ctrl_mem_walk.317539335	Jul 30 06:51:22 PM PDT 24	Jul 30 06:56:55 PM PDT 24	18345718282 ps
T160	/workspace/coverage/default/44.sram_ctrl_alert_test.517358047	Jul 30 06:50:41 PM PDT 24	Jul 30 06:50:42 PM PDT 24	15499369 ps
T161	/workspace/coverage/default/25.sram_ctrl_alert_test.122572456	Jul 30 06:48:03 PM PDT 24	Jul 30 06:48:04 PM PDT 24	16458672 ps
T57	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1522873775	Jul 30 06:50:15 PM PDT 24	Jul 30 06:51:44 PM PDT 24	2722695815 ps
T162	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4073505160	Jul 30 06:47:01 PM PDT 24	Jul 30 06:49:28 PM PDT 24	795830077 ps
T163	/workspace/coverage/default/41.sram_ctrl_partial_access.3874279966	Jul 30 06:50:08 PM PDT 24	Jul 30 06:51:13 PM PDT 24	817684708 ps
T75	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2163651542	Jul 30 06:47:06 PM PDT 24	Jul 30 06:47:33 PM PDT 24	1108853447 ps
T164	/workspace/coverage/default/41.sram_ctrl_alert_test.1607085039	Jul 30 06:50:21 PM PDT 24	Jul 30 06:50:22 PM PDT 24	15272525 ps
T143	/workspace/coverage/default/31.sram_ctrl_regwen.3493820043	Jul 30 06:48:47 PM PDT 24	Jul 30 06:59:22 PM PDT 24	15216973313 ps
T139	/workspace/coverage/default/38.sram_ctrl_regwen.1291804158	Jul 30 06:49:42 PM PDT 24	Jul 30 07:05:33 PM PDT 24	11269235101 ps
T165	/workspace/coverage/default/42.sram_ctrl_max_throughput.1092252532	Jul 30 06:50:23 PM PDT 24	Jul 30 06:50:34 PM PDT 24	1368363927 ps
T166	/workspace/coverage/default/30.sram_ctrl_lc_escalation.1826660228	Jul 30 06:48:34 PM PDT 24	Jul 30 06:48:51 PM PDT 24	2264367774 ps
T167	/workspace/coverage/default/46.sram_ctrl_mem_walk.2514342073	Jul 30 06:50:59 PM PDT 24	Jul 30 06:57:16 PM PDT 24	41366824423 ps
T168	/workspace/coverage/default/25.sram_ctrl_ram_cfg.4085179451	Jul 30 06:48:05 PM PDT 24	Jul 30 06:48:08 PM PDT 24	1355476399 ps
T169	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1465172055	Jul 30 06:48:32 PM PDT 24	Jul 30 06:51:12 PM PDT 24	6475205740 ps
T170	/workspace/coverage/default/25.sram_ctrl_bijection.2399849113	Jul 30 06:47:57 PM PDT 24	Jul 30 07:10:22 PM PDT 24	155262728985 ps
T171	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.854377964	Jul 30 06:47:54 PM PDT 24	Jul 30 06:51:06 PM PDT 24	19948586830 ps
T172	/workspace/coverage/default/13.sram_ctrl_mem_walk.3769908493	Jul 30 06:47:51 PM PDT 24	Jul 30 06:53:42 PM PDT 24	18717509918 ps
T173	/workspace/coverage/default/29.sram_ctrl_smoke.2438548049	Jul 30 06:48:26 PM PDT 24	Jul 30 06:48:39 PM PDT 24	929186495 ps
T76	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1345461381	Jul 30 06:47:00 PM PDT 24	Jul 30 06:47:08 PM PDT 24	791739432 ps
T140	/workspace/coverage/default/34.sram_ctrl_executable.1553297691	Jul 30 06:49:01 PM PDT 24	Jul 30 06:49:58 PM PDT 24	1829089942 ps
T174	/workspace/coverage/default/33.sram_ctrl_partial_access.257949063	Jul 30 06:49:01 PM PDT 24	Jul 30 06:49:19 PM PDT 24	1291638208 ps
T175	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.2284275792	Jul 30 06:49:43 PM PDT 24	Jul 30 07:11:33 PM PDT 24	32042821971 ps
T176	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.1951177343	Jul 30 06:47:44 PM PDT 24	Jul 30 06:50:34 PM PDT 24	4605793492 ps
T177	/workspace/coverage/default/2.sram_ctrl_stress_all.1104654771	Jul 30 06:47:09 PM PDT 24	Jul 30 07:19:56 PM PDT 24	45187961385 ps
T178	/workspace/coverage/default/30.sram_ctrl_smoke.2788484315	Jul 30 06:48:29 PM PDT 24	Jul 30 06:48:41 PM PDT 24	716455008 ps
T179	/workspace/coverage/default/44.sram_ctrl_partial_access.569535738	Jul 30 06:50:33 PM PDT 24	Jul 30 06:50:44 PM PDT 24	771300535 ps
T180	/workspace/coverage/default/15.sram_ctrl_regwen.676058855	Jul 30 06:47:43 PM PDT 24	Jul 30 06:51:54 PM PDT 24	3580192456 ps
T58	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1705921411	Jul 30 06:50:04 PM PDT 24	Jul 30 06:51:33 PM PDT 24	6350400774 ps
T77	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.848516880	Jul 30 06:50:00 PM PDT 24	Jul 30 06:50:17 PM PDT 24	530933963 ps
T181	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2656244879	Jul 30 06:47:45 PM PDT 24	Jul 30 06:53:52 PM PDT 24	5129928622 ps
T182	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.3280167885	Jul 30 06:48:29 PM PDT 24	Jul 30 06:49:48 PM PDT 24	2483591731 ps
T183	/workspace/coverage/default/32.sram_ctrl_ram_cfg.1035755755	Jul 30 06:48:50 PM PDT 24	Jul 30 06:48:53 PM PDT 24	1548741782 ps
T184	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3461877346	Jul 30 06:50:18 PM PDT 24	Jul 30 06:51:06 PM PDT 24	2818778233 ps
T185	/workspace/coverage/default/3.sram_ctrl_ram_cfg.2479522502	Jul 30 06:47:04 PM PDT 24	Jul 30 06:47:08 PM PDT 24	356152094 ps
T186	/workspace/coverage/default/22.sram_ctrl_regwen.3928872521	Jul 30 06:47:51 PM PDT 24	Jul 30 06:51:52 PM PDT 24	5052341069 ps
T187	/workspace/coverage/default/27.sram_ctrl_max_throughput.1722775809	Jul 30 06:48:14 PM PDT 24	Jul 30 06:49:01 PM PDT 24	2929738467 ps
T188	/workspace/coverage/default/15.sram_ctrl_ram_cfg.3780640532	Jul 30 06:47:39 PM PDT 24	Jul 30 06:47:43 PM PDT 24	362501588 ps
T189	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.632200974	Jul 30 06:50:12 PM PDT 24	Jul 30 06:52:36 PM PDT 24	1175050697 ps
T190	/workspace/coverage/default/27.sram_ctrl_alert_test.1752985422	Jul 30 06:48:21 PM PDT 24	Jul 30 06:48:22 PM PDT 24	15852366 ps
T191	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3756497454	Jul 30 06:47:00 PM PDT 24	Jul 30 07:04:29 PM PDT 24	106951967250 ps
T192	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1970471661	Jul 30 06:48:23 PM PDT 24	Jul 30 06:53:08 PM PDT 24	6931521181 ps
T193	/workspace/coverage/default/10.sram_ctrl_stress_all.2447568871	Jul 30 06:47:37 PM PDT 24	Jul 30 07:09:16 PM PDT 24	205592829769 ps
T144	/workspace/coverage/default/8.sram_ctrl_stress_all.880021854	Jul 30 06:47:13 PM PDT 24	Jul 30 08:41:20 PM PDT 24	332236126048 ps
T194	/workspace/coverage/default/45.sram_ctrl_ram_cfg.1245593886	Jul 30 06:50:49 PM PDT 24	Jul 30 06:50:52 PM PDT 24	346090821 ps
T148	/workspace/coverage/default/40.sram_ctrl_executable.3018090495	Jul 30 06:50:03 PM PDT 24	Jul 30 07:11:06 PM PDT 24	22856382151 ps
T195	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3619484350	Jul 30 06:47:02 PM PDT 24	Jul 30 06:48:25 PM PDT 24	4848445428 ps
T196	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2395141242	Jul 30 06:50:51 PM PDT 24	Jul 30 06:55:39 PM PDT 24	4308033421 ps
T78	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1474964146	Jul 30 06:47:51 PM PDT 24	Jul 30 06:49:02 PM PDT 24	2596193700 ps
T59	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2827457412	Jul 30 06:48:12 PM PDT 24	Jul 30 06:50:35 PM PDT 24	4053945663 ps
T197	/workspace/coverage/default/44.sram_ctrl_regwen.150065828	Jul 30 06:50:37 PM PDT 24	Jul 30 07:19:57 PM PDT 24	18634713495 ps
T198	/workspace/coverage/default/47.sram_ctrl_ram_cfg.2115413802	Jul 30 06:51:06 PM PDT 24	Jul 30 06:51:10 PM PDT 24	680983531 ps
T199	/workspace/coverage/default/28.sram_ctrl_multiple_keys.3241713125	Jul 30 06:48:21 PM PDT 24	Jul 30 07:07:51 PM PDT 24	8404181917 ps
T200	/workspace/coverage/default/23.sram_ctrl_mem_walk.421885194	Jul 30 06:47:53 PM PDT 24	Jul 30 06:50:29 PM PDT 24	10957157663 ps
T201	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1044674950	Jul 30 06:50:54 PM PDT 24	Jul 30 07:04:26 PM PDT 24	15513855044 ps
T202	/workspace/coverage/default/33.sram_ctrl_executable.921845497	Jul 30 06:48:57 PM PDT 24	Jul 30 07:03:25 PM PDT 24	34607602671 ps
T203	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.582274947	Jul 30 06:47:06 PM PDT 24	Jul 30 06:53:07 PM PDT 24	7431845010 ps
T204	/workspace/coverage/default/26.sram_ctrl_mem_walk.3421374694	Jul 30 06:48:15 PM PDT 24	Jul 30 06:53:49 PM PDT 24	57681340659 ps
T205	/workspace/coverage/default/34.sram_ctrl_multiple_keys.2425886150	Jul 30 06:48:59 PM PDT 24	Jul 30 07:03:14 PM PDT 24	34439259387 ps
T206	/workspace/coverage/default/1.sram_ctrl_max_throughput.3418744680	Jul 30 06:47:00 PM PDT 24	Jul 30 06:47:54 PM PDT 24	1399533527 ps
T207	/workspace/coverage/default/2.sram_ctrl_max_throughput.92083373	Jul 30 06:47:01 PM PDT 24	Jul 30 06:47:10 PM PDT 24	692848004 ps
T208	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.4190696632	Jul 30 06:51:02 PM PDT 24	Jul 30 06:54:30 PM PDT 24	6081631877 ps
T115	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.15180081	Jul 30 06:47:40 PM PDT 24	Jul 30 06:47:49 PM PDT 24	1558302331 ps
T146	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3580497554	Jul 30 06:48:39 PM PDT 24	Jul 30 06:53:18 PM PDT 24	49784999651 ps
T209	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.1891925640	Jul 30 06:47:57 PM PDT 24	Jul 30 07:07:41 PM PDT 24	26751821062 ps
T210	/workspace/coverage/default/23.sram_ctrl_stress_all.2275090939	Jul 30 06:47:59 PM PDT 24	Jul 30 08:32:28 PM PDT 24	114473401878 ps
T211	/workspace/coverage/default/19.sram_ctrl_lc_escalation.2664759396	Jul 30 06:47:48 PM PDT 24	Jul 30 06:48:25 PM PDT 24	6130213767 ps
T212	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.265984191	Jul 30 06:47:02 PM PDT 24	Jul 30 06:51:10 PM PDT 24	8247604938 ps
T213	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3121368018	Jul 30 06:50:40 PM PDT 24	Jul 30 06:50:53 PM PDT 24	310508469 ps
T138	/workspace/coverage/default/19.sram_ctrl_executable.3714123589	Jul 30 06:47:48 PM PDT 24	Jul 30 06:57:24 PM PDT 24	44974831524 ps
T214	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1537788129	Jul 30 06:49:41 PM PDT 24	Jul 30 06:55:15 PM PDT 24	27973466931 ps
T60	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.4249632083	Jul 30 06:47:42 PM PDT 24	Jul 30 06:48:55 PM PDT 24	5752213052 ps
T215	/workspace/coverage/default/15.sram_ctrl_lc_escalation.1690381173	Jul 30 06:47:41 PM PDT 24	Jul 30 06:48:49 PM PDT 24	11742230645 ps
T216	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.414603537	Jul 30 06:49:42 PM PDT 24	Jul 30 06:56:11 PM PDT 24	9957551164 ps
T217	/workspace/coverage/default/4.sram_ctrl_executable.2695186524	Jul 30 06:46:59 PM PDT 24	Jul 30 06:54:41 PM PDT 24	68898993107 ps
T218	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2086080581	Jul 30 06:47:50 PM PDT 24	Jul 30 06:49:56 PM PDT 24	3180547964 ps
T219	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.459374421	Jul 30 06:49:43 PM PDT 24	Jul 30 06:50:05 PM PDT 24	2958752391 ps
T220	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.583631184	Jul 30 06:48:46 PM PDT 24	Jul 30 06:53:38 PM PDT 24	43423025579 ps
T221	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.1409445751	Jul 30 06:47:42 PM PDT 24	Jul 30 06:57:18 PM PDT 24	8208910847 ps
T222	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.822086181	Jul 30 06:47:13 PM PDT 24	Jul 30 06:59:32 PM PDT 24	21508300483 ps
T223	/workspace/coverage/default/46.sram_ctrl_multiple_keys.3291045299	Jul 30 06:50:51 PM PDT 24	Jul 30 06:53:00 PM PDT 24	3026245653 ps
T224	/workspace/coverage/default/22.sram_ctrl_max_throughput.1123880849	Jul 30 06:47:52 PM PDT 24	Jul 30 06:49:55 PM PDT 24	1311393464 ps
T225	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3928173727	Jul 30 06:51:07 PM PDT 24	Jul 30 06:52:30 PM PDT 24	2433730672 ps
T226	/workspace/coverage/default/40.sram_ctrl_partial_access.2517701361	Jul 30 06:49:59 PM PDT 24	Jul 30 06:50:06 PM PDT 24	724935463 ps
T227	/workspace/coverage/default/21.sram_ctrl_partial_access.2860832990	Jul 30 06:47:51 PM PDT 24	Jul 30 06:48:09 PM PDT 24	2855091317 ps
T228	/workspace/coverage/default/38.sram_ctrl_executable.906357246	Jul 30 06:49:39 PM PDT 24	Jul 30 07:07:42 PM PDT 24	82927694957 ps
T229	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.950541880	Jul 30 06:47:42 PM PDT 24	Jul 30 06:48:45 PM PDT 24	2013915099 ps
T230	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3960206961	Jul 30 06:49:16 PM PDT 24	Jul 30 06:49:47 PM PDT 24	2028528163 ps
T231	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3187514370	Jul 30 06:48:50 PM PDT 24	Jul 30 07:03:03 PM PDT 24	83242042717 ps
T232	/workspace/coverage/default/13.sram_ctrl_multiple_keys.673922614	Jul 30 06:47:40 PM PDT 24	Jul 30 07:07:08 PM PDT 24	143292402941 ps
T233	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3728448629	Jul 30 06:48:57 PM PDT 24	Jul 30 07:14:14 PM PDT 24	14533682286 ps
T234	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1873578057	Jul 30 06:47:32 PM PDT 24	Jul 30 06:58:54 PM PDT 24	21455611714 ps
T235	/workspace/coverage/default/3.sram_ctrl_stress_all.2254739198	Jul 30 06:46:59 PM PDT 24	Jul 30 07:24:58 PM PDT 24	19143863565 ps
T236	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1753264067	Jul 30 06:47:52 PM PDT 24	Jul 30 06:48:06 PM PDT 24	371189796 ps
T237	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3526504265	Jul 30 06:49:59 PM PDT 24	Jul 30 07:09:26 PM PDT 24	140730522410 ps
T238	/workspace/coverage/default/23.sram_ctrl_bijection.2438395537	Jul 30 06:47:53 PM PDT 24	Jul 30 07:18:16 PM PDT 24	99722334807 ps
T239	/workspace/coverage/default/48.sram_ctrl_partial_access.4009030169	Jul 30 06:51:14 PM PDT 24	Jul 30 06:51:28 PM PDT 24	927497460 ps
T240	/workspace/coverage/default/24.sram_ctrl_max_throughput.635652563	Jul 30 06:47:51 PM PDT 24	Jul 30 06:48:57 PM PDT 24	3201979760 ps
T241	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3824040294	Jul 30 06:49:16 PM PDT 24	Jul 30 06:52:10 PM PDT 24	8309908823 ps
T242	/workspace/coverage/default/6.sram_ctrl_partial_access.3980489077	Jul 30 06:47:04 PM PDT 24	Jul 30 06:47:26 PM PDT 24	1854752582 ps
T243	/workspace/coverage/default/42.sram_ctrl_regwen.892114617	Jul 30 06:50:23 PM PDT 24	Jul 30 07:06:52 PM PDT 24	84818846421 ps
T244	/workspace/coverage/default/4.sram_ctrl_stress_all.2002854754	Jul 30 06:47:10 PM PDT 24	Jul 30 08:57:15 PM PDT 24	408178441746 ps
T245	/workspace/coverage/default/38.sram_ctrl_alert_test.1575551405	Jul 30 06:49:45 PM PDT 24	Jul 30 06:49:46 PM PDT 24	15131235 ps
T246	/workspace/coverage/default/34.sram_ctrl_partial_access.3790058368	Jul 30 06:48:58 PM PDT 24	Jul 30 06:49:17 PM PDT 24	814245695 ps
T247	/workspace/coverage/default/34.sram_ctrl_alert_test.49483473	Jul 30 06:49:09 PM PDT 24	Jul 30 06:49:09 PM PDT 24	34651386 ps
T248	/workspace/coverage/default/5.sram_ctrl_regwen.1078123279	Jul 30 06:47:24 PM PDT 24	Jul 30 07:10:02 PM PDT 24	9985602882 ps
T249	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3814281071	Jul 30 06:48:24 PM PDT 24	Jul 30 06:50:59 PM PDT 24	4431649344 ps
T250	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2827344822	Jul 30 06:51:02 PM PDT 24	Jul 30 06:56:49 PM PDT 24	5334532331 ps
T251	/workspace/coverage/default/19.sram_ctrl_bijection.3976842587	Jul 30 06:47:42 PM PDT 24	Jul 30 07:08:11 PM PDT 24	64364098003 ps
T252	/workspace/coverage/default/44.sram_ctrl_stress_all.840492454	Jul 30 06:50:45 PM PDT 24	Jul 30 09:02:07 PM PDT 24	861518866831 ps
T253	/workspace/coverage/default/26.sram_ctrl_smoke.4176424441	Jul 30 06:48:07 PM PDT 24	Jul 30 06:48:20 PM PDT 24	5418593710 ps
T254	/workspace/coverage/default/24.sram_ctrl_multiple_keys.1998250094	Jul 30 06:47:54 PM PDT 24	Jul 30 07:04:20 PM PDT 24	40601095989 ps
T255	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1561857526	Jul 30 06:49:00 PM PDT 24	Jul 30 06:50:18 PM PDT 24	9847520517 ps
T256	/workspace/coverage/default/29.sram_ctrl_executable.3909578782	Jul 30 06:48:27 PM PDT 24	Jul 30 07:03:41 PM PDT 24	124209789105 ps
T257	/workspace/coverage/default/8.sram_ctrl_multiple_keys.3647207583	Jul 30 06:47:05 PM PDT 24	Jul 30 06:48:36 PM PDT 24	11122020490 ps
T258	/workspace/coverage/default/9.sram_ctrl_bijection.1739026746	Jul 30 06:47:18 PM PDT 24	Jul 30 07:19:14 PM PDT 24	199575381272 ps
T259	/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.606986735	Jul 30 06:48:21 PM PDT 24	Jul 30 06:49:01 PM PDT 24	1455517342 ps
T260	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.4282244572	Jul 30 06:47:13 PM PDT 24	Jul 30 06:50:09 PM PDT 24	12832365584 ps
T261	/workspace/coverage/default/16.sram_ctrl_alert_test.597493665	Jul 30 06:47:47 PM PDT 24	Jul 30 06:47:48 PM PDT 24	45111733 ps
T147	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.800538168	Jul 30 06:47:24 PM PDT 24	Jul 30 06:54:55 PM PDT 24	20763345060 ps
T262	/workspace/coverage/default/12.sram_ctrl_executable.285905743	Jul 30 06:47:40 PM PDT 24	Jul 30 07:00:30 PM PDT 24	58954329287 ps
T263	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1953183071	Jul 30 06:49:32 PM PDT 24	Jul 30 06:51:00 PM PDT 24	3589842007 ps
T264	/workspace/coverage/default/2.sram_ctrl_partial_access.369841217	Jul 30 06:47:00 PM PDT 24	Jul 30 06:47:20 PM PDT 24	5384103932 ps
T265	/workspace/coverage/default/38.sram_ctrl_stress_all.1978565170	Jul 30 06:49:44 PM PDT 24	Jul 30 08:58:09 PM PDT 24	101120303509 ps
T266	/workspace/coverage/default/47.sram_ctrl_multiple_keys.1662450754	Jul 30 06:51:02 PM PDT 24	Jul 30 06:57:07 PM PDT 24	150288387098 ps
T267	/workspace/coverage/default/23.sram_ctrl_partial_access.3941600471	Jul 30 06:47:53 PM PDT 24	Jul 30 06:47:59 PM PDT 24	515158246 ps
T268	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3727678559	Jul 30 06:47:32 PM PDT 24	Jul 30 06:48:53 PM PDT 24	10171409547 ps
T269	/workspace/coverage/default/45.sram_ctrl_bijection.425673069	Jul 30 06:50:40 PM PDT 24	Jul 30 07:20:17 PM PDT 24	26352285521 ps
T270	/workspace/coverage/default/38.sram_ctrl_bijection.2409081855	Jul 30 06:49:36 PM PDT 24	Jul 30 07:02:01 PM PDT 24	63117876244 ps
T271	/workspace/coverage/default/17.sram_ctrl_multiple_keys.2717233061	Jul 30 06:47:40 PM PDT 24	Jul 30 07:03:10 PM PDT 24	50944803928 ps
T272	/workspace/coverage/default/7.sram_ctrl_multiple_keys.3151948120	Jul 30 06:47:02 PM PDT 24	Jul 30 06:55:54 PM PDT 24	6993235419 ps
T273	/workspace/coverage/default/35.sram_ctrl_partial_access.260203513	Jul 30 06:49:12 PM PDT 24	Jul 30 06:49:25 PM PDT 24	4084581609 ps
T274	/workspace/coverage/default/14.sram_ctrl_smoke.3409178478	Jul 30 06:47:52 PM PDT 24	Jul 30 06:47:56 PM PDT 24	1585401558 ps
T275	/workspace/coverage/default/31.sram_ctrl_bijection.455765229	Jul 30 06:48:36 PM PDT 24	Jul 30 07:21:00 PM PDT 24	63347880774 ps
T276	/workspace/coverage/default/22.sram_ctrl_executable.3450868497	Jul 30 06:47:52 PM PDT 24	Jul 30 07:10:36 PM PDT 24	25043042136 ps
T277	/workspace/coverage/default/17.sram_ctrl_stress_all.2561206670	Jul 30 06:47:48 PM PDT 24	Jul 30 06:49:03 PM PDT 24	2916931492 ps
T278	/workspace/coverage/default/20.sram_ctrl_executable.3776495806	Jul 30 06:47:48 PM PDT 24	Jul 30 06:58:02 PM PDT 24	91102820016 ps
T279	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.4088375566	Jul 30 06:48:06 PM PDT 24	Jul 30 06:52:10 PM PDT 24	20952902155 ps
T280	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1822611387	Jul 30 06:50:46 PM PDT 24	Jul 30 06:50:53 PM PDT 24	6028970506 ps
T281	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.738072213	Jul 30 06:47:18 PM PDT 24	Jul 30 06:47:39 PM PDT 24	2999620128 ps
T282	/workspace/coverage/default/7.sram_ctrl_bijection.2619331002	Jul 30 06:47:11 PM PDT 24	Jul 30 07:08:28 PM PDT 24	134616929157 ps
T283	/workspace/coverage/default/35.sram_ctrl_regwen.1582522436	Jul 30 06:49:16 PM PDT 24	Jul 30 07:00:44 PM PDT 24	19129095235 ps
T284	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1565032335	Jul 30 06:47:52 PM PDT 24	Jul 30 06:49:13 PM PDT 24	1455843355 ps
T285	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3487584725	Jul 30 06:47:21 PM PDT 24	Jul 30 06:52:05 PM PDT 24	3936900186 ps
T286	/workspace/coverage/default/2.sram_ctrl_ram_cfg.1375003067	Jul 30 06:47:03 PM PDT 24	Jul 30 06:47:08 PM PDT 24	676208501 ps
T287	/workspace/coverage/default/25.sram_ctrl_smoke.2896877548	Jul 30 06:47:52 PM PDT 24	Jul 30 06:48:02 PM PDT 24	864724842 ps
T288	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.188414287	Jul 30 06:47:07 PM PDT 24	Jul 30 06:51:28 PM PDT 24	27758811452 ps
T289	/workspace/coverage/default/16.sram_ctrl_stress_all.960309179	Jul 30 06:47:47 PM PDT 24	Jul 30 08:04:58 PM PDT 24	173919722587 ps
T290	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2994015646	Jul 30 06:47:43 PM PDT 24	Jul 30 06:48:05 PM PDT 24	813549004 ps
T291	/workspace/coverage/default/10.sram_ctrl_multiple_keys.1940093617	Jul 30 06:47:26 PM PDT 24	Jul 30 06:55:45 PM PDT 24	6696032524 ps
T292	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1430370822	Jul 30 06:51:01 PM PDT 24	Jul 30 06:54:00 PM PDT 24	26405621095 ps
T293	/workspace/coverage/default/36.sram_ctrl_lc_escalation.2797094905	Jul 30 06:49:24 PM PDT 24	Jul 30 06:50:13 PM PDT 24	8661385927 ps
T294	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3666281217	Jul 30 06:50:45 PM PDT 24	Jul 30 06:55:09 PM PDT 24	8984455203 ps
T295	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.143285491	Jul 30 06:48:13 PM PDT 24	Jul 30 06:50:06 PM PDT 24	15238377671 ps
T296	/workspace/coverage/default/9.sram_ctrl_mem_walk.940192155	Jul 30 06:47:19 PM PDT 24	Jul 30 06:51:34 PM PDT 24	17125989188 ps
T297	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2360996785	Jul 30 06:47:23 PM PDT 24	Jul 30 06:48:32 PM PDT 24	3407249972 ps
T298	/workspace/coverage/default/18.sram_ctrl_smoke.1682408690	Jul 30 06:47:48 PM PDT 24	Jul 30 06:48:08 PM PDT 24	1256377206 ps
T299	/workspace/coverage/default/47.sram_ctrl_regwen.2336183482	Jul 30 06:51:06 PM PDT 24	Jul 30 07:08:51 PM PDT 24	4700109746 ps
T300	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.433683956	Jul 30 06:48:46 PM PDT 24	Jul 30 06:52:19 PM PDT 24	16162618498 ps
T301	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.1439914572	Jul 30 06:47:04 PM PDT 24	Jul 30 06:51:01 PM PDT 24	3319177319 ps
T302	/workspace/coverage/default/21.sram_ctrl_executable.2977289029	Jul 30 06:47:51 PM PDT 24	Jul 30 07:06:04 PM PDT 24	145699539757 ps
T303	/workspace/coverage/default/8.sram_ctrl_mem_walk.4231059971	Jul 30 06:47:04 PM PDT 24	Jul 30 06:49:21 PM PDT 24	7897119701 ps
T304	/workspace/coverage/default/37.sram_ctrl_smoke.1731509991	Jul 30 06:49:29 PM PDT 24	Jul 30 06:50:14 PM PDT 24	728758966 ps
T305	/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1726938799	Jul 30 06:50:31 PM PDT 24	Jul 30 06:51:02 PM PDT 24	2395809183 ps
T306	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2884791481	Jul 30 06:48:10 PM PDT 24	Jul 30 07:05:38 PM PDT 24	8477879685 ps
T307	/workspace/coverage/default/42.sram_ctrl_smoke.3074334533	Jul 30 06:50:18 PM PDT 24	Jul 30 06:51:24 PM PDT 24	796461080 ps
T308	/workspace/coverage/default/4.sram_ctrl_partial_access.2089401849	Jul 30 06:47:32 PM PDT 24	Jul 30 06:49:06 PM PDT 24	5012726391 ps
T309	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.1138273814	Jul 30 06:47:00 PM PDT 24	Jul 30 06:52:34 PM PDT 24	45830828778 ps
T310	/workspace/coverage/default/25.sram_ctrl_executable.2596336942	Jul 30 06:48:02 PM PDT 24	Jul 30 07:16:29 PM PDT 24	39171734547 ps
T311	/workspace/coverage/default/33.sram_ctrl_ram_cfg.4254952687	Jul 30 06:48:59 PM PDT 24	Jul 30 06:49:03 PM PDT 24	1537579425 ps
T312	/workspace/coverage/default/22.sram_ctrl_partial_access.4172721047	Jul 30 06:47:49 PM PDT 24	Jul 30 06:48:09 PM PDT 24	1099468759 ps