Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	150788823	1			T2	9113		T3	1003		T4	5424
triple_byte_access	2651278	1			T2	195		T3	23		T4	222
halfword_access	4067463	1			T2	268		T3	29		T4	363
byte_access	5687172	1			T2	374		T3	42		T4	458
zero_access	1717911	1			T2	89		T3	14		T4	122

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82212363

1

T2

4975

T3

550

T4

3297

auto[1]

82700284

1

T2

5064

T3

561

T4

3292

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75024897	1			T2	4525		T3	505		T4	2686
auto[0]	triple_byte_access	1263724	1			T2	100		T3	9		T4	119
auto[0]	halfword_access	1984494	1			T2	142		T3	15		T4	195
auto[0]	byte_access	2913466	1			T2	172		T3	14		T4	235
auto[0]	zero_access	1025782	1			T2	36		T3	7		T4	62
auto[1]	word_access	75763926	1			T2	4588		T3	498		T4	2738
auto[1]	triple_byte_access	1387554	1			T2	95		T3	14		T4	103
auto[1]	halfword_access	2082969	1			T2	126		T3	14		T4	168
auto[1]	byte_access	2773706	1			T2	202		T3	28		T4	223
auto[1]	zero_access	692129	1			T2	53		T3	7		T4	60