Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	358271808	1			T2	306988		T3	127948		T4	394410
instr_valid_dis	314170883	1			T2	306988		T3	127948		T4	394410
instr_en	32107631	1			T5	47688		T12	64402		T7	69698

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11345820	1			T5	45634		T12	135034		T7	81648
sram_ifetch_valid_disable	319662976	1			T2	306988		T3	127948		T4	394410
sram_ifetch_enable	27263012	1			T5	106510		T12	125934		T7	131808

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	358271808	1			T2	306988		T3	127948		T4	394410
hw_debug_en_valid_off	321567234	1			T2	306988		T3	127948		T4	394410
hw_debug_en_on	25369786	1			T5	183336		T12	69178		T7	161662

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	319662976	1			T2	306988		T3	127948		T4	394410
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	301454097	1			T2	306988		T3	127948		T4	394410
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12032219	1			T5	47688		T12	17950		T7	6682
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3986312	1			T5	388		T12	88582		T7	28642
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1729206	1			T5	388		T7	17336		T47	56
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1521654	1			T7	11306		T22	9538		T48	30876
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4887518	1			T5	27430		T7	33006		T22	31958
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1785774	1			T7	17604		T165	56180		T161	14868
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2391524	1			T7	15402		T22	31958		T23	24952
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11515016	1			T5	141036		T12	18468		T7	25450
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6643456	1			T5	128464		T7	18768		T86	50036
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3590164	1			T5	12572		T7	6682		T47	30028

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	15004768	1			T7	36308		T22	124886		T48	23546
lc_exec_en	8967252	1			T5	14870		T12	50710		T7	103206
valid_exec_dis	311828538	1			T2	306988		T3	127948		T4	394410
invalid_exec_dis	38608832	1			T5	152144		T12	260968		T7	213456