Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.92 99.19 94.15 99.72 100.00 95.79 99.12 97.44


Total tests in report: 1032
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
75.69 75.69 93.05 93.05 76.90 76.90 88.43 88.43 33.33 33.33 85.31 85.31 93.42 93.42 59.41 59.41 /workspace/coverage/default/46.sram_ctrl_stress_all.3728066903
87.42 11.73 96.65 3.60 84.83 7.94 90.08 1.65 71.43 38.10 90.28 4.98 95.32 1.90 83.36 23.95 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2967690603
92.05 4.63 98.12 1.47 84.83 0.00 90.08 0.00 100.00 28.57 92.65 2.37 95.32 0.00 83.36 0.00 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3283601863
93.87 1.82 98.36 0.25 87.09 2.25 97.73 7.64 100.00 0.00 92.89 0.24 95.47 0.15 85.56 2.19 /workspace/coverage/default/1.sram_ctrl_stress_all.4065694653
94.80 0.93 98.53 0.16 87.91 0.83 97.93 0.21 100.00 0.00 93.60 0.71 95.47 0.00 90.13 4.57 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.256470491
95.50 0.70 98.69 0.16 89.69 1.78 98.69 0.76 100.00 0.00 94.31 0.71 96.05 0.58 91.04 0.91 /workspace/coverage/default/1.sram_ctrl_sec_cm.3070274188
95.97 0.47 98.94 0.25 90.40 0.71 98.76 0.07 100.00 0.00 95.02 0.71 97.08 1.02 91.59 0.55 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3562594581
96.26 0.29 98.94 0.00 90.40 0.00 98.76 0.00 100.00 0.00 95.02 0.00 97.08 0.00 93.60 2.01 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3488797866
96.50 0.24 99.10 0.16 90.52 0.12 98.76 0.00 100.00 0.00 95.50 0.47 97.81 0.73 93.78 0.18 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3668506139
96.65 0.16 99.10 0.00 90.52 0.00 98.76 0.00 100.00 0.00 95.50 0.00 97.81 0.00 94.88 1.10 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3981788162
96.81 0.16 99.10 0.00 90.52 0.00 98.83 0.07 100.00 0.00 95.50 0.00 98.83 1.02 94.88 0.00 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3974583903
96.94 0.13 99.10 0.00 90.52 0.00 98.83 0.00 100.00 0.00 95.50 0.00 98.83 0.00 95.80 0.91 /workspace/coverage/default/7.sram_ctrl_stress_all.2620996034
97.07 0.13 99.18 0.08 90.52 0.00 99.66 0.83 100.00 0.00 95.50 0.00 98.83 0.00 95.80 0.00 /workspace/coverage/default/17.sram_ctrl_ram_cfg.1506875315
97.17 0.10 99.18 0.00 90.52 0.00 99.66 0.00 100.00 0.00 95.50 0.00 98.83 0.00 96.53 0.73 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2589720728
97.27 0.09 99.18 0.00 90.88 0.36 99.72 0.07 100.00 0.00 95.73 0.24 98.83 0.00 96.53 0.00 /workspace/coverage/default/17.sram_ctrl_alert_test.459159972
97.35 0.08 99.18 0.00 90.88 0.00 99.72 0.00 100.00 0.00 95.73 0.00 98.83 0.00 97.07 0.55 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2786199409
97.39 0.04 99.18 0.00 90.88 0.00 99.72 0.00 100.00 0.00 95.73 0.00 99.12 0.29 97.07 0.00 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2731991841
97.42 0.03 99.18 0.00 90.88 0.00 99.72 0.00 100.00 0.00 95.97 0.24 99.12 0.00 97.07 0.00 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3815209926
97.45 0.03 99.18 0.00 90.88 0.00 99.72 0.00 100.00 0.00 95.97 0.00 99.12 0.00 97.26 0.18 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4063269162
97.47 0.03 99.18 0.00 90.88 0.00 99.72 0.00 100.00 0.00 95.97 0.00 99.12 0.00 97.44 0.18 /workspace/coverage/default/13.sram_ctrl_regwen.3762727151

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3363625367
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.474147436
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1425604192
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1472789289
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2911624332
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1721025398
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4209127533
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1420743200
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.510873719
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1056927899
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2692097600
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2710484660
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2226710449
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2788120918
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3938168666
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1300494693
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.139606537
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3811999492
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1208582656
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4113077235
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.644916105
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1149188426
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.141328644
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.335796351
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.210288298
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.514660449
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1418699055
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.116839132
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2928534363
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.219770655
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2110787145
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3160713857
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3359327007
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4043385571
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.398845551
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3766120588
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3248137643
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3643510263
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2995962495
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3868488623
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.418766163
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4109108866
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.903175855
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3794964332
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3075389591
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1051285411
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1815915218
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.470137087
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4212709804
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.4122771461
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2399964741
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.601711845
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.362576203
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2146314983
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4048473373
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3602581591
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.902973442
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1014547444
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4116569733
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.343920083
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1597547078
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3077770228
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2565903967
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3695080899
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3290651573
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1410310452
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3550163667
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1590995550
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.409018406
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3641784383
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3277740873
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3350698010
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1861805044
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4107608868
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3034617312
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1582675057
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2748622497
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3624740067
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.78057055
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3852229734
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.719460168
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.827957925
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1726034678
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2135345392
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3191871766
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3029858427
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.691714928
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.766226068
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.207139195
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3835917758
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3143866516
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3036478696
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3808667628
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3606143158
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3510774630
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1034897935
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1106396048
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2685519265
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3528980240
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1160557746
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.356248480
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1481797982
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.34865540
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1481424700
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2474931933
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1750355784
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3612612405
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4055729238
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.229976318
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1234314950
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1559925694
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3186414923
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.475456999
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1306201735
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1582135713
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.917793404
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4002197658
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2562931701
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2775639464
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3711035341
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1925667218
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2821681238
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1539448931
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2891028740
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1232672557
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2634732517
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2119449722
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.974707217
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.362845349
/workspace/coverage/default/0.sram_ctrl_alert_test.3673663366
/workspace/coverage/default/0.sram_ctrl_bijection.596315058
/workspace/coverage/default/0.sram_ctrl_executable.3701195216
/workspace/coverage/default/0.sram_ctrl_lc_escalation.727680283
/workspace/coverage/default/0.sram_ctrl_max_throughput.5863401
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.404848238
/workspace/coverage/default/0.sram_ctrl_mem_walk.4102155366
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2804731206
/workspace/coverage/default/0.sram_ctrl_partial_access.2000403196
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.936338281
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2583175217
/workspace/coverage/default/0.sram_ctrl_regwen.3213213233
/workspace/coverage/default/0.sram_ctrl_sec_cm.3227859716
/workspace/coverage/default/0.sram_ctrl_smoke.2874611262
/workspace/coverage/default/0.sram_ctrl_stress_all.808243370
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1564475691
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3949153602
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.112946954
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2637330264
/workspace/coverage/default/1.sram_ctrl_alert_test.1472194516
/workspace/coverage/default/1.sram_ctrl_bijection.2248267393
/workspace/coverage/default/1.sram_ctrl_executable.3900082079
/workspace/coverage/default/1.sram_ctrl_lc_escalation.614664678
/workspace/coverage/default/1.sram_ctrl_max_throughput.1991685599
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.340189115
/workspace/coverage/default/1.sram_ctrl_mem_walk.459041121
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2683501460
/workspace/coverage/default/1.sram_ctrl_partial_access.3045905519
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1158720039
/workspace/coverage/default/1.sram_ctrl_ram_cfg.45144433
/workspace/coverage/default/1.sram_ctrl_regwen.3408270393
/workspace/coverage/default/1.sram_ctrl_smoke.2481174029
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3717011278
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1850944486
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3110298729
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.4035495784
/workspace/coverage/default/10.sram_ctrl_alert_test.1929131989
/workspace/coverage/default/10.sram_ctrl_bijection.2049259209
/workspace/coverage/default/10.sram_ctrl_executable.1421447903
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2616684146
/workspace/coverage/default/10.sram_ctrl_max_throughput.207791662
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2220396153
/workspace/coverage/default/10.sram_ctrl_mem_walk.3954737880
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3739571929
/workspace/coverage/default/10.sram_ctrl_partial_access.1222743739
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3005648624
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2863849680
/workspace/coverage/default/10.sram_ctrl_regwen.2004730749
/workspace/coverage/default/10.sram_ctrl_smoke.2838987808
/workspace/coverage/default/10.sram_ctrl_stress_all.1523152526
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1496614689
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.580004883
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3057846847
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3581907083
/workspace/coverage/default/11.sram_ctrl_alert_test.1301765147
/workspace/coverage/default/11.sram_ctrl_bijection.2462217821
/workspace/coverage/default/11.sram_ctrl_executable.3562471472
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1434712841
/workspace/coverage/default/11.sram_ctrl_max_throughput.893984024
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3302331601
/workspace/coverage/default/11.sram_ctrl_mem_walk.1506892874
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3429772065
/workspace/coverage/default/11.sram_ctrl_partial_access.1773668315
/workspace/coverage/default/11.sram_ctrl_ram_cfg.458712887
/workspace/coverage/default/11.sram_ctrl_regwen.2673611433
/workspace/coverage/default/11.sram_ctrl_smoke.1400749494
/workspace/coverage/default/11.sram_ctrl_stress_all.1637084383
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1548040623
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.903786586
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3766856841
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.537638097
/workspace/coverage/default/12.sram_ctrl_alert_test.1956263912
/workspace/coverage/default/12.sram_ctrl_bijection.2465068309
/workspace/coverage/default/12.sram_ctrl_executable.819251454
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/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1058883099
/workspace/coverage/default/43.sram_ctrl_alert_test.780387294
/workspace/coverage/default/43.sram_ctrl_bijection.3235941713
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2890010340
/workspace/coverage/default/43.sram_ctrl_max_throughput.3570867958
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2539496814
/workspace/coverage/default/43.sram_ctrl_mem_walk.717395142
/workspace/coverage/default/43.sram_ctrl_multiple_keys.4237444334
/workspace/coverage/default/43.sram_ctrl_partial_access.3160461703
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.430632795
/workspace/coverage/default/43.sram_ctrl_ram_cfg.108235772
/workspace/coverage/default/43.sram_ctrl_regwen.4098903200
/workspace/coverage/default/43.sram_ctrl_smoke.2271407980
/workspace/coverage/default/43.sram_ctrl_stress_all.2844414637
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.4240464767
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2235999459
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4158771733
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3951841987
/workspace/coverage/default/44.sram_ctrl_alert_test.886740809
/workspace/coverage/default/44.sram_ctrl_bijection.2984472400
/workspace/coverage/default/44.sram_ctrl_executable.805219773
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2222224658
/workspace/coverage/default/44.sram_ctrl_max_throughput.77532251
/workspace/coverage/default/44.sram_ctrl_mem_walk.1233385913
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4291994847
/workspace/coverage/default/44.sram_ctrl_partial_access.2879197292
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3042576787
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2675237080
/workspace/coverage/default/44.sram_ctrl_regwen.3519083886
/workspace/coverage/default/44.sram_ctrl_smoke.4069719972
/workspace/coverage/default/44.sram_ctrl_stress_all.3508172724
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.899881090
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.482646238
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3951233886
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2128573591
/workspace/coverage/default/45.sram_ctrl_alert_test.2827287949
/workspace/coverage/default/45.sram_ctrl_bijection.1458630572
/workspace/coverage/default/45.sram_ctrl_executable.4279103352
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2946576216
/workspace/coverage/default/45.sram_ctrl_max_throughput.1471999030
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3546742938
/workspace/coverage/default/45.sram_ctrl_mem_walk.558624532
/workspace/coverage/default/45.sram_ctrl_multiple_keys.464051617
/workspace/coverage/default/45.sram_ctrl_partial_access.2491976291
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3904406168
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1652874387
/workspace/coverage/default/45.sram_ctrl_regwen.1300455052
/workspace/coverage/default/45.sram_ctrl_smoke.2569247756
/workspace/coverage/default/45.sram_ctrl_stress_all.1589919347
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1714914768
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3499072315
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3334900761
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1965407916
/workspace/coverage/default/46.sram_ctrl_alert_test.2461091887
/workspace/coverage/default/46.sram_ctrl_bijection.2451976081
/workspace/coverage/default/46.sram_ctrl_executable.476638215
/workspace/coverage/default/46.sram_ctrl_lc_escalation.691290120
/workspace/coverage/default/46.sram_ctrl_max_throughput.3338728717
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3201878068
/workspace/coverage/default/46.sram_ctrl_mem_walk.2968433353
/workspace/coverage/default/46.sram_ctrl_multiple_keys.549122114
/workspace/coverage/default/46.sram_ctrl_partial_access.3729656352
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1794596474
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3200336101
/workspace/coverage/default/46.sram_ctrl_regwen.1054399343
/workspace/coverage/default/46.sram_ctrl_smoke.1499782348
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1267770157
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3026463025
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3470325097
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.92766701
/workspace/coverage/default/47.sram_ctrl_alert_test.1477419515
/workspace/coverage/default/47.sram_ctrl_bijection.875187769
/workspace/coverage/default/47.sram_ctrl_executable.1573546688
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1515314828
/workspace/coverage/default/47.sram_ctrl_max_throughput.3731667899
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.395829015
/workspace/coverage/default/47.sram_ctrl_mem_walk.4139878079
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2251269417
/workspace/coverage/default/47.sram_ctrl_partial_access.1097097274
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2077729014
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1975282512
/workspace/coverage/default/47.sram_ctrl_regwen.4144099969
/workspace/coverage/default/47.sram_ctrl_smoke.854817080
/workspace/coverage/default/47.sram_ctrl_stress_all.809091738
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1610484869
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3387306312
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1272125319
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2708225202
/workspace/coverage/default/48.sram_ctrl_alert_test.12135563
/workspace/coverage/default/48.sram_ctrl_bijection.2638843900
/workspace/coverage/default/48.sram_ctrl_executable.4091084333
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2752041836
/workspace/coverage/default/48.sram_ctrl_max_throughput.3329064321
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4177776312
/workspace/coverage/default/48.sram_ctrl_mem_walk.338447012
/workspace/coverage/default/48.sram_ctrl_multiple_keys.262819146
/workspace/coverage/default/48.sram_ctrl_partial_access.48611477
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2667259721
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2400617310
/workspace/coverage/default/48.sram_ctrl_regwen.1193131001
/workspace/coverage/default/48.sram_ctrl_smoke.1387459691
/workspace/coverage/default/48.sram_ctrl_stress_all.3670004657
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3496586367
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1288404400
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3740529975
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2737087255
/workspace/coverage/default/49.sram_ctrl_alert_test.548142479
/workspace/coverage/default/49.sram_ctrl_bijection.2431781053
/workspace/coverage/default/49.sram_ctrl_executable.1596165329
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1696231631
/workspace/coverage/default/49.sram_ctrl_max_throughput.217007000
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1306695605
/workspace/coverage/default/49.sram_ctrl_mem_walk.1866325018
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3664130830
/workspace/coverage/default/49.sram_ctrl_partial_access.318223930
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.811886884
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2340105677
/workspace/coverage/default/49.sram_ctrl_regwen.3960839260
/workspace/coverage/default/49.sram_ctrl_smoke.4079523178
/workspace/coverage/default/49.sram_ctrl_stress_all.570444299
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3989031035
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2060351739
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1960699334
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2028396621
/workspace/coverage/default/5.sram_ctrl_alert_test.3240752513
/workspace/coverage/default/5.sram_ctrl_bijection.1528237297
/workspace/coverage/default/5.sram_ctrl_executable.2828108196
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4101429359
/workspace/coverage/default/5.sram_ctrl_max_throughput.2002773302
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2008930449
/workspace/coverage/default/5.sram_ctrl_mem_walk.1880191845
/workspace/coverage/default/5.sram_ctrl_multiple_keys.969743199
/workspace/coverage/default/5.sram_ctrl_partial_access.1739259598
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3949588430
/workspace/coverage/default/5.sram_ctrl_ram_cfg.4114930026
/workspace/coverage/default/5.sram_ctrl_regwen.2080615228
/workspace/coverage/default/5.sram_ctrl_smoke.4026361753
/workspace/coverage/default/5.sram_ctrl_stress_all.1475988241
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1228457181
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2795335619
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1151854437
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1627334364
/workspace/coverage/default/6.sram_ctrl_alert_test.3141109023
/workspace/coverage/default/6.sram_ctrl_bijection.246247194
/workspace/coverage/default/6.sram_ctrl_executable.1841611009
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1050726781
/workspace/coverage/default/6.sram_ctrl_max_throughput.4202645365
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.4077480858
/workspace/coverage/default/6.sram_ctrl_mem_walk.2560916612
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1743163306
/workspace/coverage/default/6.sram_ctrl_partial_access.974796721
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.354343002
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1353966127
/workspace/coverage/default/6.sram_ctrl_regwen.3391248483
/workspace/coverage/default/6.sram_ctrl_smoke.3057175111
/workspace/coverage/default/6.sram_ctrl_stress_all.2827919913
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3219727858
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2967535300
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1496254030
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2454092499
/workspace/coverage/default/7.sram_ctrl_alert_test.2958893058
/workspace/coverage/default/7.sram_ctrl_bijection.118226011
/workspace/coverage/default/7.sram_ctrl_executable.3962995363
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1504177408
/workspace/coverage/default/7.sram_ctrl_max_throughput.4212871570
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1760384592
/workspace/coverage/default/7.sram_ctrl_mem_walk.1753966722
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2762488914
/workspace/coverage/default/7.sram_ctrl_partial_access.574750045
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3125218127
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3524793563
/workspace/coverage/default/7.sram_ctrl_regwen.3099836120
/workspace/coverage/default/7.sram_ctrl_smoke.326274133
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3202493139
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3400433410
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1536643847
/workspace/coverage/default/8.sram_ctrl_alert_test.512405817
/workspace/coverage/default/8.sram_ctrl_bijection.1076446385
/workspace/coverage/default/8.sram_ctrl_executable.1740290031
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1116021739
/workspace/coverage/default/8.sram_ctrl_max_throughput.284017678
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1034043512
/workspace/coverage/default/8.sram_ctrl_mem_walk.2796737622
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2344929225
/workspace/coverage/default/8.sram_ctrl_partial_access.827856455
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1476562283
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3086881466
/workspace/coverage/default/8.sram_ctrl_regwen.874642539
/workspace/coverage/default/8.sram_ctrl_smoke.4120410422
/workspace/coverage/default/8.sram_ctrl_stress_all.806285993
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.265957099
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1960550478
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2442527680
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1457164702
/workspace/coverage/default/9.sram_ctrl_alert_test.2447392104
/workspace/coverage/default/9.sram_ctrl_bijection.3832622783
/workspace/coverage/default/9.sram_ctrl_executable.2442212804
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1318110658
/workspace/coverage/default/9.sram_ctrl_max_throughput.3433342316
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3350357573
/workspace/coverage/default/9.sram_ctrl_mem_walk.3249787466
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2366763651
/workspace/coverage/default/9.sram_ctrl_partial_access.3313684496
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1024102941
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3873297754
/workspace/coverage/default/9.sram_ctrl_regwen.1717593431
/workspace/coverage/default/9.sram_ctrl_smoke.2823565450
/workspace/coverage/default/9.sram_ctrl_stress_all.1166808307
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2552849490
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1592163324
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3805425985



Total test records in report: 1032
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/27.sram_ctrl_ram_cfg.102570001 Jul 31 07:00:05 PM PDT 24 Jul 31 07:00:09 PM PDT 24 1355592870 ps
T2 /workspace/coverage/default/21.sram_ctrl_multiple_keys.2666194617 Jul 31 06:58:50 PM PDT 24 Jul 31 07:11:49 PM PDT 24 67563742538 ps
T3 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3562594581 Jul 31 07:04:58 PM PDT 24 Jul 31 07:07:04 PM PDT 24 3219219204 ps
T4 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.951266064 Jul 31 07:03:37 PM PDT 24 Jul 31 07:07:34 PM PDT 24 11390437821 ps
T9 /workspace/coverage/default/8.sram_ctrl_mem_walk.2796737622 Jul 31 06:55:01 PM PDT 24 Jul 31 06:59:07 PM PDT 24 15763926299 ps
T10 /workspace/coverage/default/19.sram_ctrl_bijection.2224927902 Jul 31 06:58:28 PM PDT 24 Jul 31 07:25:42 PM PDT 24 46168178997 ps
T5 /workspace/coverage/default/46.sram_ctrl_stress_all.3728066903 Jul 31 07:05:39 PM PDT 24 Jul 31 08:25:48 PM PDT 24 251725418767 ps
T6 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.305086478 Jul 31 06:58:55 PM PDT 24 Jul 31 06:59:05 PM PDT 24 588753547 ps
T11 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.32160252 Jul 31 07:04:18 PM PDT 24 Jul 31 07:06:15 PM PDT 24 7822893560 ps
T12 /workspace/coverage/default/37.sram_ctrl_regwen.1971482396 Jul 31 07:03:00 PM PDT 24 Jul 31 07:18:30 PM PDT 24 3570835902 ps
T7 /workspace/coverage/default/1.sram_ctrl_stress_all.4065694653 Jul 31 06:53:27 PM PDT 24 Jul 31 07:34:29 PM PDT 24 165737049975 ps
T40 /workspace/coverage/default/12.sram_ctrl_multiple_keys.1474072778 Jul 31 06:57:49 PM PDT 24 Jul 31 07:02:40 PM PDT 24 6064005935 ps
T42 /workspace/coverage/default/25.sram_ctrl_mem_walk.1610908459 Jul 31 06:59:41 PM PDT 24 Jul 31 07:04:34 PM PDT 24 10938102635 ps
T43 /workspace/coverage/default/4.sram_ctrl_multiple_keys.2749906088 Jul 31 06:54:05 PM PDT 24 Jul 31 07:09:27 PM PDT 24 74854504392 ps
T24 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1960550478 Jul 31 06:54:54 PM PDT 24 Jul 31 06:59:43 PM PDT 24 20109318525 ps
T66 /workspace/coverage/default/33.sram_ctrl_multiple_keys.551725962 Jul 31 07:01:38 PM PDT 24 Jul 31 07:15:09 PM PDT 24 10857896949 ps
T22 /workspace/coverage/default/35.sram_ctrl_regwen.3709888914 Jul 31 07:02:22 PM PDT 24 Jul 31 07:10:22 PM PDT 24 2748815689 ps
T8 /workspace/coverage/default/46.sram_ctrl_lc_escalation.691290120 Jul 31 07:05:25 PM PDT 24 Jul 31 07:05:41 PM PDT 24 2202505935 ps
T67 /workspace/coverage/default/35.sram_ctrl_multiple_keys.1884211819 Jul 31 07:02:19 PM PDT 24 Jul 31 07:10:57 PM PDT 24 7865775743 ps
T47 /workspace/coverage/default/3.sram_ctrl_executable.1960787452 Jul 31 06:53:55 PM PDT 24 Jul 31 06:56:03 PM PDT 24 1688079970 ps
T68 /workspace/coverage/default/28.sram_ctrl_multiple_keys.3796767837 Jul 31 07:00:12 PM PDT 24 Jul 31 07:08:23 PM PDT 24 12695999555 ps
T69 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2589720728 Jul 31 06:57:40 PM PDT 24 Jul 31 07:04:15 PM PDT 24 6831299055 ps
T49 /workspace/coverage/default/0.sram_ctrl_mem_walk.4102155366 Jul 31 06:53:03 PM PDT 24 Jul 31 06:55:45 PM PDT 24 15362755563 ps
T174 /workspace/coverage/default/35.sram_ctrl_max_throughput.1147523485 Jul 31 07:02:22 PM PDT 24 Jul 31 07:02:43 PM PDT 24 3067160174 ps
T177 /workspace/coverage/default/15.sram_ctrl_smoke.3099973519 Jul 31 06:57:52 PM PDT 24 Jul 31 06:58:09 PM PDT 24 2217324193 ps
T179 /workspace/coverage/default/42.sram_ctrl_bijection.682756412 Jul 31 07:04:14 PM PDT 24 Jul 31 07:12:35 PM PDT 24 52989998783 ps
T129 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.568502142 Jul 31 07:02:37 PM PDT 24 Jul 31 07:07:26 PM PDT 24 4396144108 ps
T41 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2098132819 Jul 31 07:03:42 PM PDT 24 Jul 31 07:24:12 PM PDT 24 19462052785 ps
T86 /workspace/coverage/default/13.sram_ctrl_regwen.3762727151 Jul 31 06:57:48 PM PDT 24 Jul 31 07:09:03 PM PDT 24 14750509426 ps
T180 /workspace/coverage/default/2.sram_ctrl_partial_access.1179472211 Jul 31 06:53:31 PM PDT 24 Jul 31 06:55:50 PM PDT 24 2137211028 ps
T50 /workspace/coverage/default/45.sram_ctrl_mem_walk.558624532 Jul 31 07:05:16 PM PDT 24 Jul 31 07:07:48 PM PDT 24 4963607635 ps
T181 /workspace/coverage/default/11.sram_ctrl_max_throughput.893984024 Jul 31 06:57:47 PM PDT 24 Jul 31 06:58:22 PM PDT 24 5919593845 ps
T176 /workspace/coverage/default/19.sram_ctrl_max_throughput.1439598565 Jul 31 06:58:31 PM PDT 24 Jul 31 06:58:44 PM PDT 24 736503373 ps
T48 /workspace/coverage/default/41.sram_ctrl_executable.2244955691 Jul 31 07:04:05 PM PDT 24 Jul 31 07:19:02 PM PDT 24 13738493660 ps
T25 /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1267770157 Jul 31 07:05:34 PM PDT 24 Jul 31 07:05:55 PM PDT 24 824056957 ps
T101 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3544548496 Jul 31 07:00:24 PM PDT 24 Jul 31 07:03:59 PM PDT 24 33579203838 ps
T87 /workspace/coverage/default/27.sram_ctrl_regwen.321188229 Jul 31 07:00:07 PM PDT 24 Jul 31 07:17:29 PM PDT 24 2325837390 ps
T182 /workspace/coverage/default/43.sram_ctrl_max_throughput.3570867958 Jul 31 07:04:31 PM PDT 24 Jul 31 07:04:39 PM PDT 24 11211122088 ps
T13 /workspace/coverage/default/25.sram_ctrl_alert_test.1756086325 Jul 31 06:59:41 PM PDT 24 Jul 31 06:59:41 PM PDT 24 33868989 ps
T44 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2637330264 Jul 31 06:53:19 PM PDT 24 Jul 31 07:04:33 PM PDT 24 11391223689 ps
T183 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1048549018 Jul 31 06:57:57 PM PDT 24 Jul 31 06:58:13 PM PDT 24 1458504243 ps
T27 /workspace/coverage/default/28.sram_ctrl_ram_cfg.1652643146 Jul 31 07:00:28 PM PDT 24 Jul 31 07:00:32 PM PDT 24 1404412896 ps
T55 /workspace/coverage/default/19.sram_ctrl_mem_walk.1860241220 Jul 31 06:58:29 PM PDT 24 Jul 31 07:01:11 PM PDT 24 28818885107 ps
T184 /workspace/coverage/default/31.sram_ctrl_partial_access.116538456 Jul 31 07:01:08 PM PDT 24 Jul 31 07:01:17 PM PDT 24 8532807535 ps
T175 /workspace/coverage/default/35.sram_ctrl_bijection.1162725181 Jul 31 07:02:18 PM PDT 24 Jul 31 07:19:08 PM PDT 24 239571504134 ps
T130 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1288404400 Jul 31 07:05:46 PM PDT 24 Jul 31 07:08:44 PM PDT 24 3115778466 ps
T26 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3197063361 Jul 31 06:58:37 PM PDT 24 Jul 31 06:58:47 PM PDT 24 2355412151 ps
T28 /workspace/coverage/default/9.sram_ctrl_ram_cfg.3873297754 Jul 31 06:55:13 PM PDT 24 Jul 31 06:55:16 PM PDT 24 357117377 ps
T14 /workspace/coverage/default/17.sram_ctrl_alert_test.459159972 Jul 31 06:58:05 PM PDT 24 Jul 31 06:58:06 PM PDT 24 139499497 ps
T185 /workspace/coverage/default/41.sram_ctrl_max_throughput.1707057735 Jul 31 07:04:00 PM PDT 24 Jul 31 07:05:32 PM PDT 24 756652737 ps
T23 /workspace/coverage/default/7.sram_ctrl_regwen.3099836120 Jul 31 06:54:49 PM PDT 24 Jul 31 06:57:52 PM PDT 24 11291761377 ps
T186 /workspace/coverage/default/25.sram_ctrl_smoke.3451046757 Jul 31 06:59:35 PM PDT 24 Jul 31 06:59:57 PM PDT 24 965861245 ps
T163 /workspace/coverage/default/14.sram_ctrl_executable.1467666676 Jul 31 06:57:49 PM PDT 24 Jul 31 07:15:43 PM PDT 24 8019757223 ps
T56 /workspace/coverage/default/6.sram_ctrl_mem_walk.2560916612 Jul 31 06:54:37 PM PDT 24 Jul 31 06:59:54 PM PDT 24 14408027033 ps
T51 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.806811333 Jul 31 07:02:17 PM PDT 24 Jul 31 07:03:32 PM PDT 24 2892026892 ps
T74 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2648572138 Jul 31 06:54:07 PM PDT 24 Jul 31 06:58:17 PM PDT 24 10822257264 ps
T75 /workspace/coverage/default/17.sram_ctrl_ram_cfg.1506875315 Jul 31 06:58:03 PM PDT 24 Jul 31 06:58:07 PM PDT 24 3742662839 ps
T64 /workspace/coverage/default/22.sram_ctrl_mem_walk.3447628772 Jul 31 06:59:02 PM PDT 24 Jul 31 07:01:33 PM PDT 24 14399546133 ps
T21 /workspace/coverage/default/27.sram_ctrl_lc_escalation.2612785965 Jul 31 07:00:06 PM PDT 24 Jul 31 07:02:00 PM PDT 24 17692365851 ps
T76 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2770633203 Jul 31 07:03:14 PM PDT 24 Jul 31 07:06:33 PM PDT 24 18501067293 ps
T77 /workspace/coverage/default/23.sram_ctrl_executable.251513939 Jul 31 06:59:16 PM PDT 24 Jul 31 07:12:13 PM PDT 24 31799598287 ps
T78 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2663852738 Jul 31 07:03:59 PM PDT 24 Jul 31 07:04:02 PM PDT 24 2782804195 ps
T65 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3668506139 Jul 31 06:58:48 PM PDT 24 Jul 31 07:01:07 PM PDT 24 1563528204 ps
T79 /workspace/coverage/default/45.sram_ctrl_bijection.1458630572 Jul 31 07:05:03 PM PDT 24 Jul 31 07:16:22 PM PDT 24 20688132555 ps
T92 /workspace/coverage/default/6.sram_ctrl_lc_escalation.1050726781 Jul 31 06:54:39 PM PDT 24 Jul 31 06:55:25 PM PDT 24 7131258802 ps
T138 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3805425985 Jul 31 06:55:08 PM PDT 24 Jul 31 06:56:57 PM PDT 24 1581443056 ps
T139 /workspace/coverage/default/37.sram_ctrl_lc_escalation.2493112819 Jul 31 07:03:01 PM PDT 24 Jul 31 07:03:52 PM PDT 24 8005133003 ps
T140 /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1039736826 Jul 31 06:57:54 PM PDT 24 Jul 31 07:04:22 PM PDT 24 32300608414 ps
T141 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3116439279 Jul 31 07:01:19 PM PDT 24 Jul 31 07:05:55 PM PDT 24 20049055906 ps
T142 /workspace/coverage/default/26.sram_ctrl_max_throughput.1493963702 Jul 31 06:59:46 PM PDT 24 Jul 31 07:01:41 PM PDT 24 4492092656 ps
T143 /workspace/coverage/default/32.sram_ctrl_multiple_keys.2235171823 Jul 31 07:01:18 PM PDT 24 Jul 31 07:17:56 PM PDT 24 50721480649 ps
T144 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3488797866 Jul 31 06:59:38 PM PDT 24 Jul 31 07:05:12 PM PDT 24 16721290811 ps
T187 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.936338281 Jul 31 06:52:57 PM PDT 24 Jul 31 06:56:04 PM PDT 24 3434293893 ps
T178 /workspace/coverage/default/34.sram_ctrl_bijection.1782041983 Jul 31 07:02:19 PM PDT 24 Jul 31 07:30:02 PM PDT 24 99716426026 ps
T188 /workspace/coverage/default/33.sram_ctrl_partial_access.280387707 Jul 31 07:01:38 PM PDT 24 Jul 31 07:01:42 PM PDT 24 2091517432 ps
T189 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2828781858 Jul 31 07:00:24 PM PDT 24 Jul 31 07:02:53 PM PDT 24 3130666527 ps
T190 /workspace/coverage/default/31.sram_ctrl_bijection.402400080 Jul 31 07:01:09 PM PDT 24 Jul 31 07:22:51 PM PDT 24 155238837436 ps
T191 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1151606493 Jul 31 06:53:57 PM PDT 24 Jul 31 06:54:44 PM PDT 24 1626531753 ps
T192 /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1456404452 Jul 31 07:02:18 PM PDT 24 Jul 31 07:06:05 PM PDT 24 8325292408 ps
T193 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2492082107 Jul 31 07:03:21 PM PDT 24 Jul 31 07:03:40 PM PDT 24 11607607949 ps
T162 /workspace/coverage/default/21.sram_ctrl_executable.2916087563 Jul 31 06:58:54 PM PDT 24 Jul 31 07:06:30 PM PDT 24 41457170643 ps
T194 /workspace/coverage/default/2.sram_ctrl_bijection.2792017504 Jul 31 06:53:27 PM PDT 24 Jul 31 07:31:23 PM PDT 24 60992996578 ps
T52 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2967690603 Jul 31 06:57:48 PM PDT 24 Jul 31 06:58:44 PM PDT 24 1776840564 ps
T145 /workspace/coverage/default/48.sram_ctrl_lc_escalation.2752041836 Jul 31 07:05:55 PM PDT 24 Jul 31 07:06:11 PM PDT 24 9370335552 ps
T195 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1518111914 Jul 31 06:57:41 PM PDT 24 Jul 31 07:02:20 PM PDT 24 4188912262 ps
T196 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.4006781389 Jul 31 06:59:11 PM PDT 24 Jul 31 06:59:30 PM PDT 24 2931702838 ps
T45 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2725456496 Jul 31 07:00:35 PM PDT 24 Jul 31 07:16:01 PM PDT 24 16600954971 ps
T197 /workspace/coverage/default/16.sram_ctrl_partial_access.345581968 Jul 31 06:58:01 PM PDT 24 Jul 31 06:58:15 PM PDT 24 1700183360 ps
T198 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1960699334 Jul 31 07:06:08 PM PDT 24 Jul 31 07:08:33 PM PDT 24 5211423240 ps
T164 /workspace/coverage/default/16.sram_ctrl_executable.1815492266 Jul 31 06:57:54 PM PDT 24 Jul 31 07:19:56 PM PDT 24 87862356468 ps
T173 /workspace/coverage/default/15.sram_ctrl_lc_escalation.316937084 Jul 31 06:57:54 PM PDT 24 Jul 31 06:58:50 PM PDT 24 8705127252 ps
T199 /workspace/coverage/default/44.sram_ctrl_smoke.4069719972 Jul 31 07:04:43 PM PDT 24 Jul 31 07:04:53 PM PDT 24 3612717527 ps
T200 /workspace/coverage/default/3.sram_ctrl_ram_cfg.2717297754 Jul 31 06:54:03 PM PDT 24 Jul 31 06:54:08 PM PDT 24 6735594452 ps
T18 /workspace/coverage/default/1.sram_ctrl_sec_cm.3070274188 Jul 31 06:53:25 PM PDT 24 Jul 31 06:53:27 PM PDT 24 342896328 ps
T31 /workspace/coverage/default/27.sram_ctrl_smoke.2347914932 Jul 31 06:59:59 PM PDT 24 Jul 31 07:00:19 PM PDT 24 1118146249 ps
T32 /workspace/coverage/default/34.sram_ctrl_mem_walk.2505181170 Jul 31 07:02:16 PM PDT 24 Jul 31 07:04:45 PM PDT 24 2744265578 ps
T33 /workspace/coverage/default/29.sram_ctrl_ram_cfg.2837464455 Jul 31 07:00:48 PM PDT 24 Jul 31 07:00:51 PM PDT 24 363042870 ps
T34 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.341977275 Jul 31 07:03:53 PM PDT 24 Jul 31 07:04:02 PM PDT 24 3089495835 ps
T35 /workspace/coverage/default/29.sram_ctrl_mem_walk.205375852 Jul 31 07:01:02 PM PDT 24 Jul 31 07:05:15 PM PDT 24 4115258981 ps
T36 /workspace/coverage/default/31.sram_ctrl_multiple_keys.3317002370 Jul 31 07:01:01 PM PDT 24 Jul 31 07:28:13 PM PDT 24 20070390452 ps
T37 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1714807470 Jul 31 07:02:23 PM PDT 24 Jul 31 07:03:14 PM PDT 24 766379096 ps
T38 /workspace/coverage/default/18.sram_ctrl_lc_escalation.3450641988 Jul 31 06:58:17 PM PDT 24 Jul 31 06:59:38 PM PDT 24 24595137664 ps
T39 /workspace/coverage/default/49.sram_ctrl_mem_walk.1866325018 Jul 31 07:06:18 PM PDT 24 Jul 31 07:08:51 PM PDT 24 2634740057 ps
T201 /workspace/coverage/default/18.sram_ctrl_mem_walk.3190248604 Jul 31 06:58:32 PM PDT 24 Jul 31 07:04:25 PM PDT 24 65770768559 ps
T202 /workspace/coverage/default/7.sram_ctrl_max_throughput.4212871570 Jul 31 06:54:49 PM PDT 24 Jul 31 06:55:43 PM PDT 24 803780915 ps
T165 /workspace/coverage/default/20.sram_ctrl_regwen.1786306486 Jul 31 06:58:43 PM PDT 24 Jul 31 07:18:59 PM PDT 24 28823191409 ps
T146 /workspace/coverage/default/39.sram_ctrl_lc_escalation.583452626 Jul 31 07:03:38 PM PDT 24 Jul 31 07:04:29 PM PDT 24 31319417625 ps
T15 /workspace/coverage/default/40.sram_ctrl_alert_test.1069317604 Jul 31 07:04:01 PM PDT 24 Jul 31 07:04:02 PM PDT 24 38500470 ps
T46 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.537638097 Jul 31 06:57:40 PM PDT 24 Jul 31 07:18:08 PM PDT 24 16693434470 ps
T16 /workspace/coverage/default/38.sram_ctrl_alert_test.3138499913 Jul 31 07:03:25 PM PDT 24 Jul 31 07:03:25 PM PDT 24 16375976 ps
T53 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3546742938 Jul 31 07:05:15 PM PDT 24 Jul 31 07:06:33 PM PDT 24 5800662645 ps
T203 /workspace/coverage/default/44.sram_ctrl_bijection.2984472400 Jul 31 07:04:51 PM PDT 24 Jul 31 07:21:06 PM PDT 24 53783500051 ps
T110 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1745781740 Jul 31 07:00:08 PM PDT 24 Jul 31 07:17:15 PM PDT 24 12478763289 ps
T60 /workspace/coverage/default/40.sram_ctrl_mem_walk.1165001557 Jul 31 07:03:53 PM PDT 24 Jul 31 07:06:55 PM PDT 24 37475826713 ps
T204 /workspace/coverage/default/32.sram_ctrl_mem_walk.1202623444 Jul 31 07:01:35 PM PDT 24 Jul 31 07:06:29 PM PDT 24 20997708493 ps
T111 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2708225202 Jul 31 07:05:52 PM PDT 24 Jul 31 07:16:25 PM PDT 24 46644236230 ps
T205 /workspace/coverage/default/24.sram_ctrl_ram_cfg.323792812 Jul 31 06:59:24 PM PDT 24 Jul 31 06:59:28 PM PDT 24 363338244 ps
T170 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.4019506645 Jul 31 07:00:48 PM PDT 24 Jul 31 07:08:02 PM PDT 24 27597557346 ps
T206 /workspace/coverage/default/49.sram_ctrl_ram_cfg.2340105677 Jul 31 07:06:16 PM PDT 24 Jul 31 07:06:20 PM PDT 24 357489424 ps
T57 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3373681314 Jul 31 06:57:56 PM PDT 24 Jul 31 06:59:14 PM PDT 24 3092723804 ps
T207 /workspace/coverage/default/34.sram_ctrl_multiple_keys.1850591530 Jul 31 07:02:16 PM PDT 24 Jul 31 07:06:56 PM PDT 24 27518221244 ps
T208 /workspace/coverage/default/20.sram_ctrl_bijection.1248619926 Jul 31 06:58:35 PM PDT 24 Jul 31 07:52:51 PM PDT 24 718509099723 ps
T161 /workspace/coverage/default/17.sram_ctrl_regwen.120613059 Jul 31 06:57:59 PM PDT 24 Jul 31 07:13:04 PM PDT 24 2922127594 ps
T209 /workspace/coverage/default/23.sram_ctrl_mem_walk.1692620025 Jul 31 06:59:21 PM PDT 24 Jul 31 07:03:35 PM PDT 24 4198788623 ps
T112 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.2771029223 Jul 31 06:58:06 PM PDT 24 Jul 31 06:59:28 PM PDT 24 2483038350 ps
T210 /workspace/coverage/default/42.sram_ctrl_max_throughput.2546390476 Jul 31 07:04:20 PM PDT 24 Jul 31 07:04:42 PM PDT 24 727054008 ps
T211 /workspace/coverage/default/7.sram_ctrl_multiple_keys.2762488914 Jul 31 06:54:45 PM PDT 24 Jul 31 07:15:39 PM PDT 24 18281450846 ps
T160 /workspace/coverage/default/45.sram_ctrl_executable.4279103352 Jul 31 07:05:09 PM PDT 24 Jul 31 07:25:49 PM PDT 24 68234289408 ps
T166 /workspace/coverage/default/48.sram_ctrl_stress_all.3670004657 Jul 31 07:05:58 PM PDT 24 Jul 31 09:10:05 PM PDT 24 440765973949 ps
T212 /workspace/coverage/default/40.sram_ctrl_stress_all.605938426 Jul 31 07:03:53 PM PDT 24 Jul 31 07:18:42 PM PDT 24 11890947128 ps
T88 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.212265790 Jul 31 06:58:06 PM PDT 24 Jul 31 06:58:20 PM PDT 24 411798299 ps
T213 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3147210901 Jul 31 06:59:00 PM PDT 24 Jul 31 07:04:34 PM PDT 24 30851745356 ps
T17 /workspace/coverage/default/32.sram_ctrl_alert_test.4047319756 Jul 31 07:01:38 PM PDT 24 Jul 31 07:01:39 PM PDT 24 14453567 ps
T214 /workspace/coverage/default/34.sram_ctrl_smoke.3507039430 Jul 31 07:02:18 PM PDT 24 Jul 31 07:02:42 PM PDT 24 1399425734 ps
T215 /workspace/coverage/default/17.sram_ctrl_stress_all.2831322839 Jul 31 06:58:06 PM PDT 24 Jul 31 07:34:27 PM PDT 24 221451896821 ps
T171 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3125218127 Jul 31 06:54:48 PM PDT 24 Jul 31 07:01:46 PM PDT 24 17820310080 ps
T216 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2425796951 Jul 31 07:01:09 PM PDT 24 Jul 31 07:01:17 PM PDT 24 1429970743 ps
T123 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.3047471200 Jul 31 06:59:26 PM PDT 24 Jul 31 07:21:49 PM PDT 24 24561017651 ps
T217 /workspace/coverage/default/16.sram_ctrl_multiple_keys.449644387 Jul 31 06:57:53 PM PDT 24 Jul 31 07:25:15 PM PDT 24 92012947643 ps
T218 /workspace/coverage/default/18.sram_ctrl_regwen.2255839398 Jul 31 06:58:22 PM PDT 24 Jul 31 07:01:15 PM PDT 24 11144890287 ps
T219 /workspace/coverage/default/18.sram_ctrl_smoke.2110071733 Jul 31 06:58:03 PM PDT 24 Jul 31 06:58:24 PM PDT 24 1591454228 ps
T220 /workspace/coverage/default/45.sram_ctrl_lc_escalation.2946576216 Jul 31 07:05:09 PM PDT 24 Jul 31 07:05:14 PM PDT 24 3514468920 ps
T221 /workspace/coverage/default/29.sram_ctrl_alert_test.403308837 Jul 31 07:00:42 PM PDT 24 Jul 31 07:00:43 PM PDT 24 68495478 ps
T222 /workspace/coverage/default/9.sram_ctrl_multiple_keys.2366763651 Jul 31 06:55:06 PM PDT 24 Jul 31 07:09:57 PM PDT 24 10234721409 ps
T223 /workspace/coverage/default/40.sram_ctrl_max_throughput.2837614222 Jul 31 07:03:48 PM PDT 24 Jul 31 07:04:03 PM PDT 24 1404961842 ps
T224 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1825839414 Jul 31 06:57:49 PM PDT 24 Jul 31 07:03:45 PM PDT 24 21639983362 ps
T167 /workspace/coverage/default/6.sram_ctrl_regwen.3391248483 Jul 31 06:54:38 PM PDT 24 Jul 31 07:13:06 PM PDT 24 89379713853 ps
T225 /workspace/coverage/default/12.sram_ctrl_partial_access.2334842377 Jul 31 06:57:39 PM PDT 24 Jul 31 06:59:22 PM PDT 24 3869821980 ps
T226 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.3030845923 Jul 31 07:03:01 PM PDT 24 Jul 31 07:05:56 PM PDT 24 5652232484 ps
T227 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.92766701 Jul 31 07:05:40 PM PDT 24 Jul 31 07:17:32 PM PDT 24 82399295931 ps
T228 /workspace/coverage/default/25.sram_ctrl_max_throughput.800890755 Jul 31 06:59:39 PM PDT 24 Jul 31 06:59:46 PM PDT 24 6035145777 ps
T229 /workspace/coverage/default/22.sram_ctrl_multiple_keys.1539103261 Jul 31 06:58:55 PM PDT 24 Jul 31 07:03:21 PM PDT 24 8521465824 ps
T230 /workspace/coverage/default/18.sram_ctrl_bijection.2255813690 Jul 31 06:58:09 PM PDT 24 Jul 31 07:19:53 PM PDT 24 230886949971 ps
T231 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1862204440 Jul 31 07:02:17 PM PDT 24 Jul 31 07:03:00 PM PDT 24 746347472 ps
T232 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4158771733 Jul 31 07:04:39 PM PDT 24 Jul 31 07:06:15 PM PDT 24 767803730 ps
T233 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2683501460 Jul 31 06:53:07 PM PDT 24 Jul 31 06:58:38 PM PDT 24 2968267379 ps
T234 /workspace/coverage/default/47.sram_ctrl_bijection.875187769 Jul 31 07:05:36 PM PDT 24 Jul 31 07:43:05 PM PDT 24 34675555928 ps
T89 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.181038748 Jul 31 07:00:11 PM PDT 24 Jul 31 07:02:10 PM PDT 24 1206829198 ps
T235 /workspace/coverage/default/8.sram_ctrl_lc_escalation.1116021739 Jul 31 06:54:54 PM PDT 24 Jul 31 06:55:01 PM PDT 24 682945957 ps
T236 /workspace/coverage/default/5.sram_ctrl_partial_access.1739259598 Jul 31 06:54:19 PM PDT 24 Jul 31 06:54:33 PM PDT 24 563782006 ps
T237 /workspace/coverage/default/13.sram_ctrl_max_throughput.1048542459 Jul 31 06:57:48 PM PDT 24 Jul 31 06:59:46 PM PDT 24 2643833589 ps
T238 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3722621476 Jul 31 06:58:28 PM PDT 24 Jul 31 07:19:35 PM PDT 24 60106676642 ps
T239 /workspace/coverage/default/37.sram_ctrl_max_throughput.3555985200 Jul 31 07:02:59 PM PDT 24 Jul 31 07:03:27 PM PDT 24 2931067939 ps
T240 /workspace/coverage/default/7.sram_ctrl_mem_walk.1753966722 Jul 31 06:54:51 PM PDT 24 Jul 31 06:58:53 PM PDT 24 8568009125 ps
T241 /workspace/coverage/default/32.sram_ctrl_regwen.465568837 Jul 31 07:01:25 PM PDT 24 Jul 31 07:14:56 PM PDT 24 180043115282 ps
T242 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4012130570 Jul 31 07:02:41 PM PDT 24 Jul 31 07:04:52 PM PDT 24 1090797908 ps
T168 /workspace/coverage/default/28.sram_ctrl_stress_all.4023759982 Jul 31 07:00:29 PM PDT 24 Jul 31 09:18:34 PM PDT 24 350696173870 ps
T243 /workspace/coverage/default/14.sram_ctrl_partial_access.1634972505 Jul 31 06:57:47 PM PDT 24 Jul 31 06:58:08 PM PDT 24 2372430751 ps
T244 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3766856841 Jul 31 06:57:43 PM PDT 24 Jul 31 06:57:50 PM PDT 24 695561293 ps
T245 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3400433410 Jul 31 06:54:49 PM PDT 24 Jul 31 06:54:59 PM PDT 24 1570013725 ps
T169 /workspace/coverage/default/7.sram_ctrl_stress_all.2620996034 Jul 31 06:54:49 PM PDT 24 Jul 31 08:19:27 PM PDT 24 66984425927 ps
T246 /workspace/coverage/default/45.sram_ctrl_stress_all.1589919347 Jul 31 07:05:15 PM PDT 24 Jul 31 07:57:15 PM PDT 24 117123593218 ps
T247 /workspace/coverage/default/43.sram_ctrl_stress_all.2844414637 Jul 31 07:04:43 PM PDT 24 Jul 31 09:12:30 PM PDT 24 1222794413556 ps
T90 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4028113386 Jul 31 07:01:02 PM PDT 24 Jul 31 07:02:11 PM PDT 24 1286431967 ps
T248 /workspace/coverage/default/35.sram_ctrl_partial_access.3430862938 Jul 31 07:02:18 PM PDT 24 Jul 31 07:02:30 PM PDT 24 2653842247 ps
T249 /workspace/coverage/default/43.sram_ctrl_smoke.2271407980 Jul 31 07:04:32 PM PDT 24 Jul 31 07:04:45 PM PDT 24 944031180 ps
T250 /workspace/coverage/default/28.sram_ctrl_lc_escalation.2284242193 Jul 31 07:00:29 PM PDT 24 Jul 31 07:01:25 PM PDT 24 8617823674 ps
T251 /workspace/coverage/default/36.sram_ctrl_smoke.1188076596 Jul 31 07:02:37 PM PDT 24 Jul 31 07:02:44 PM PDT 24 4853040707 ps
T172 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1794596474 Jul 31 07:05:24 PM PDT 24 Jul 31 07:09:50 PM PDT 24 50250489517 ps
T252 /workspace/coverage/default/17.sram_ctrl_executable.3125980307 Jul 31 06:57:59 PM PDT 24 Jul 31 07:05:07 PM PDT 24 24551013010 ps
T253 /workspace/coverage/default/8.sram_ctrl_max_throughput.284017678 Jul 31 06:54:55 PM PDT 24 Jul 31 06:55:04 PM PDT 24 710165298 ps
T254 /workspace/coverage/default/21.sram_ctrl_mem_walk.1327296062 Jul 31 06:58:53 PM PDT 24 Jul 31 07:01:39 PM PDT 24 19776394325 ps
T255 /workspace/coverage/default/32.sram_ctrl_ram_cfg.3182253872 Jul 31 07:01:32 PM PDT 24 Jul 31 07:01:35 PM PDT 24 1206955862 ps
T256 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3005648624 Jul 31 06:57:07 PM PDT 24 Jul 31 07:03:01 PM PDT 24 45434399205 ps
T257 /workspace/coverage/default/30.sram_ctrl_max_throughput.2982739441 Jul 31 07:00:47 PM PDT 24 Jul 31 07:02:12 PM PDT 24 791527938 ps
T258 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1998145599 Jul 31 07:02:21 PM PDT 24 Jul 31 07:17:57 PM PDT 24 12448173195 ps
T259 /workspace/coverage/default/28.sram_ctrl_mem_walk.3489106938 Jul 31 07:00:30 PM PDT 24 Jul 31 07:03:03 PM PDT 24 14746276758 ps
T260 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.112946954 Jul 31 06:53:02 PM PDT 24 Jul 31 06:54:21 PM PDT 24 788124213 ps
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T316 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3518108906 Jul 31 06:59:28 PM PDT 24 Jul 31 07:06:54 PM PDT 24 20847638308 ps
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