Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	149427121	1			T2	139502		T3	3159		T4	179506
triple_byte_access	2799321	1			T2	2826		T3	7042		T4	3593
halfword_access	4291322	1			T2	4123		T3	13501		T4	5284
byte_access	6002400	1			T2	5607		T3	25340		T4	7093
zero_access	1815758	1			T2	1436		T3	14932		T4	1729

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81997567

1

T2

76727

T3

31812

T4

98606

auto[1]

82338355

1

T2

76767

T3

32162

T4

98599

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	74396899	1			T2	69655		T3	271		T4	89912
auto[0]	triple_byte_access	1336802	1			T2	1429		T3	1292		T4	1760
auto[0]	halfword_access	2098947	1			T2	2048		T3	4593		T4	2538
auto[0]	byte_access	3080432	1			T2	2874		T3	13643		T4	3534
auto[0]	zero_access	1084487	1			T2	721		T3	12013		T4	862
auto[1]	word_access	75030222	1			T2	69847		T3	2888		T4	89594
auto[1]	triple_byte_access	1462519	1			T2	1397		T3	5750		T4	1833
auto[1]	halfword_access	2192375	1			T2	2075		T3	8908		T4	2746
auto[1]	byte_access	2921968	1			T2	2733		T3	11697		T4	3559
auto[1]	zero_access	731271	1			T2	715		T3	2919		T4	867