Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16728761	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

168913178

1

T1

144751

T2

2613

T3

27907

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	91532948	1			T1	79582		T2	1448		T3	76582
values[0x0]	45390334	1			T1	38635		T2	684		T3	25848
values[0x1]	48718657	1			T1	41126		T2	756		T3	50763

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8497011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

177144928

1

T1

152051

T2

2749

T3

90981

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	656758	1			T1	585		T2	17		T3	596
valid_sources[0x01]	652022	1			T1	586		T2	2		T3	625
valid_sources[0x02]	609349	1			T1	600		T3	555		T4	8
valid_sources[0x03]	650582	1			T1	626		T2	7		T3	600
valid_sources[0x04]	609914	1			T1	634		T2	27		T3	589
valid_sources[0x05]	635415	1			T1	664		T2	31		T3	604
valid_sources[0x06]	621647	1			T1	606		T2	5		T3	601
valid_sources[0x07]	3129464	1			T1	647		T2	1		T3	544
valid_sources[0x08]	628126	1			T1	598		T2	7		T3	620
valid_sources[0x09]	618174	1			T1	669		T2	22		T3	583
valid_sources[0x0a]	1783962	1			T1	627		T2	51		T3	576
valid_sources[0x0b]	629591	1			T1	606		T2	5		T3	639
valid_sources[0x0c]	639236	1			T1	676		T3	624		T4	57
valid_sources[0x0d]	616824	1			T1	646		T2	3		T3	593
valid_sources[0x0e]	643494	1			T1	636		T3	623		T4	24
valid_sources[0x0f]	631894	1			T1	586		T2	12		T3	604
valid_sources[0x10]	623573	1			T1	590		T2	11		T3	627
valid_sources[0x11]	640786	1			T1	611		T2	14		T3	583
valid_sources[0x12]	1790457	1			T1	542		T2	34		T3	613
valid_sources[0x13]	634363	1			T1	599		T3	548		T4	3
valid_sources[0x14]	1719039	1			T1	617		T2	15		T3	578
valid_sources[0x15]	593434	1			T1	610		T2	16		T3	563
valid_sources[0x16]	683807	1			T1	591		T2	41		T3	592
valid_sources[0x17]	642812	1			T1	644		T2	8		T3	599
valid_sources[0x18]	606033	1			T1	659		T2	1		T3	631
valid_sources[0x19]	610108	1			T1	643		T2	16		T3	596
valid_sources[0x1a]	602077	1			T1	642		T2	1		T3	581
valid_sources[0x1b]	609989	1			T1	628		T2	5		T3	603
valid_sources[0x1c]	612700	1			T1	639		T2	23		T3	580
valid_sources[0x1d]	641050	1			T1	619		T2	13		T3	600
valid_sources[0x1e]	611369	1			T1	568		T2	8		T3	633
valid_sources[0x1f]	608470	1			T1	603		T2	16		T3	654
valid_sources[0x20]	671098	1			T1	598		T2	3		T3	576
valid_sources[0x21]	696333	1			T1	592		T2	5		T3	559
valid_sources[0x22]	645416	1			T1	658		T2	5		T3	603
valid_sources[0x23]	623748	1			T1	576		T2	2		T3	597
valid_sources[0x24]	660920	1			T1	575		T3	614		T4	10
valid_sources[0x25]	615156	1			T1	591		T3	613		T4	1
valid_sources[0x26]	678861	1			T1	612		T2	9		T3	603
valid_sources[0x27]	609783	1			T1	585		T2	4		T3	518
valid_sources[0x28]	617739	1			T1	648		T2	11		T3	552
valid_sources[0x29]	632961	1			T1	673		T2	15		T3	560
valid_sources[0x2a]	599496	1			T1	605		T2	1		T3	600
valid_sources[0x2b]	602317	1			T1	620		T3	603		T4	7
valid_sources[0x2c]	674541	1			T1	580		T2	26		T3	581
valid_sources[0x2d]	639314	1			T1	638		T2	49		T3	580
valid_sources[0x2e]	722802	1			T1	610		T2	21		T3	603
valid_sources[0x2f]	613422	1			T1	664		T2	2		T3	595
valid_sources[0x30]	2275081	1			T1	536		T2	11		T3	616
valid_sources[0x31]	1749197	1			T1	684		T2	3		T3	607
valid_sources[0x32]	648257	1			T1	643		T2	6		T3	603
valid_sources[0x33]	623329	1			T1	600		T3	592		T4	18
valid_sources[0x34]	620660	1			T1	661		T2	17		T3	638
valid_sources[0x35]	613652	1			T1	643		T2	11		T3	596
valid_sources[0x36]	610313	1			T1	591		T2	2		T3	641
valid_sources[0x37]	635843	1			T1	676		T2	1		T3	663
valid_sources[0x38]	624416	1			T1	619		T2	32		T3	564
valid_sources[0x39]	671989	1			T1	619		T3	546		T4	4
valid_sources[0x3a]	599058	1			T1	577		T3	613		T4	12
valid_sources[0x3b]	615485	1			T1	693		T2	8		T3	603
valid_sources[0x3c]	645724	1			T1	588		T2	16		T3	611
valid_sources[0x3d]	616852	1			T1	618		T2	10		T3	595
valid_sources[0x3e]	669341	1			T1	541		T2	3		T3	588
valid_sources[0x3f]	626844	1			T1	618		T2	1		T3	613
valid_sources[0x40]	651600	1			T1	630		T2	20		T3	565
valid_sources[0x41]	641793	1			T1	606		T3	597		T4	12
valid_sources[0x42]	639067	1			T1	605		T2	31		T3	637
valid_sources[0x43]	617579	1			T1	573		T2	46		T3	564
valid_sources[0x44]	617994	1			T1	600		T2	2		T3	665
valid_sources[0x45]	1857952	1			T1	605		T2	12		T3	583
valid_sources[0x46]	636635	1			T1	606		T2	11		T3	620
valid_sources[0x47]	731455	1			T1	673		T2	75		T3	547
valid_sources[0x48]	642392	1			T1	628		T3	594		T4	33
valid_sources[0x49]	656233	1			T1	656		T3	588		T4	11
valid_sources[0x4a]	606222	1			T1	566		T3	592		T4	15
valid_sources[0x4b]	608626	1			T1	592		T2	8		T3	604
valid_sources[0x4c]	602776	1			T1	610		T2	15		T3	589
valid_sources[0x4d]	690751	1			T1	637		T2	5		T3	643
valid_sources[0x4e]	631370	1			T1	664		T2	11		T3	580
valid_sources[0x4f]	858261	1			T1	647		T2	16		T3	642
valid_sources[0x50]	599867	1			T1	615		T3	593		T4	15
valid_sources[0x51]	698661	1			T1	659		T2	11		T3	623
valid_sources[0x52]	698606	1			T1	609		T2	31		T3	564
valid_sources[0x53]	639340	1			T1	609		T2	12		T3	607
valid_sources[0x54]	653971	1			T1	564		T2	38		T3	639
valid_sources[0x55]	639056	1			T1	538		T2	2		T3	584
valid_sources[0x56]	634637	1			T1	660		T2	1		T3	614
valid_sources[0x57]	663433	1			T1	597		T2	37		T3	642
valid_sources[0x58]	611543	1			T1	557		T3	640		T4	8
valid_sources[0x59]	601545	1			T1	676		T2	14		T3	610
valid_sources[0x5a]	611031	1			T1	576		T2	3		T3	585
valid_sources[0x5b]	651991	1			T1	603		T2	15		T3	634
valid_sources[0x5c]	686649	1			T1	683		T2	7		T3	582
valid_sources[0x5d]	614132	1			T1	600		T2	9		T3	629
valid_sources[0x5e]	629836	1			T1	708		T2	5		T3	542
valid_sources[0x5f]	603967	1			T1	605		T2	23		T3	574
valid_sources[0x60]	1472619	1			T1	546		T2	15		T3	621
valid_sources[0x61]	641424	1			T1	657		T3	616		T4	22
valid_sources[0x62]	1401302	1			T1	564		T2	12		T3	581
valid_sources[0x63]	1817654	1			T1	619		T2	8		T3	601
valid_sources[0x64]	605168	1			T1	655		T2	23		T3	607
valid_sources[0x65]	658428	1			T1	635		T2	12		T3	563
valid_sources[0x66]	659276	1			T1	621		T2	36		T3	583
valid_sources[0x67]	680924	1			T1	630		T3	609		T4	9
valid_sources[0x68]	664748	1			T1	663		T2	21		T3	607
valid_sources[0x69]	598777	1			T1	642		T2	1		T3	593
valid_sources[0x6a]	2248712	1			T1	641		T3	629		T4	28
valid_sources[0x6b]	664406	1			T1	629		T2	21		T3	595
valid_sources[0x6c]	617151	1			T1	631		T3	569		T4	5
valid_sources[0x6d]	618872	1			T1	607		T2	10		T3	613
valid_sources[0x6e]	668394	1			T1	641		T3	576		T4	12
valid_sources[0x6f]	608014	1			T1	614		T2	29		T3	594
valid_sources[0x70]	667640	1			T1	588		T2	2		T3	554
valid_sources[0x71]	636849	1			T1	638		T3	645		T4	23
valid_sources[0x72]	607345	1			T1	676		T2	16		T3	603
valid_sources[0x73]	595669	1			T1	593		T2	7		T3	630
valid_sources[0x74]	625538	1			T1	611		T2	7		T3	618
valid_sources[0x75]	600854	1			T1	590		T2	25		T3	643
valid_sources[0x76]	635742	1			T1	576		T3	598		T4	9
valid_sources[0x77]	612530	1			T1	588		T2	43		T3	622
valid_sources[0x78]	645163	1			T1	621		T3	615		T4	11
valid_sources[0x79]	626645	1			T1	645		T2	24		T3	599
valid_sources[0x7a]	618002	1			T1	598		T3	606		T4	11
valid_sources[0x7b]	639572	1			T1	632		T2	2		T3	571
valid_sources[0x7c]	1142770	1			T1	636		T2	3		T3	607
valid_sources[0x7d]	715368	1			T1	639		T2	6		T3	606
valid_sources[0x7e]	642486	1			T1	673		T2	13		T3	600
valid_sources[0x7f]	653191	1			T1	636		T3	627		T4	16
valid_sources[0x80]	621883	1			T1	625		T2	6		T3	615

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

83126256

1

T1

72250

T2

1304

T3

13934

values[0x0]

all_enables

biggest_size

42892175

1

T1

36421

T2

643

T3

7074

values[0x1]

all_enables

biggest_size

42894747

1

T1

36080

T2

666

T3

6899

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148484

1

T1

9

T2

20

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52999	1			T2	28		T8	640		T5	23
values[0x0]	68132	1			T1	13		T2	19		T3	4
values[0x1]	72619	1			T1	16		T2	10		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158651

1

T1

12

T2

23

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	757	1			T8	9		T55	1		T41	2
valid_sources[0x01]	760	1			T8	10		T41	1		T18	1
valid_sources[0x02]	1039	1			T8	8		T41	5		T18	1
valid_sources[0x03]	774	1			T8	5		T64	2		T18	1
valid_sources[0x04]	641	1			T8	14		T5	7		T55	1
valid_sources[0x05]	1390	1			T8	1		T55	1		T41	1
valid_sources[0x06]	879	1			T1	1		T8	17		T18	1
valid_sources[0x07]	957	1			T8	1		T18	2		T21	7
valid_sources[0x08]	1000	1			T8	30		T64	1		T18	2
valid_sources[0x09]	684	1			T8	24		T18	1		T143	1
valid_sources[0x0a]	537	1			T8	9		T6	26		T41	2
valid_sources[0x0b]	560	1			T8	4		T18	1		T21	13
valid_sources[0x0c]	722	1			T8	2		T41	2		T40	1
valid_sources[0x0d]	679	1			T8	1		T11	1		T21	7
valid_sources[0x0e]	772	1			T8	29		T40	1		T20	7
valid_sources[0x0f]	668	1			T8	3		T41	3		T40	1
valid_sources[0x10]	661	1			T8	9		T41	2		T21	18
valid_sources[0x11]	905	1			T8	10		T41	1		T18	1
valid_sources[0x12]	649	1			T8	1		T41	1		T18	2
valid_sources[0x13]	1125	1			T8	14		T41	2		T20	4
valid_sources[0x14]	793	1			T8	9		T41	2		T64	1
valid_sources[0x15]	688	1			T8	7		T41	1		T40	1
valid_sources[0x16]	934	1			T8	9		T55	1		T6	1
valid_sources[0x17]	667	1			T8	6		T40	1		T18	2
valid_sources[0x18]	716	1			T8	3		T41	1		T18	2
valid_sources[0x19]	648	1			T8	11		T38	1		T23	24
valid_sources[0x1a]	693	1			T8	5		T24	6		T143	1
valid_sources[0x1b]	675	1			T8	4		T5	2		T41	4
valid_sources[0x1c]	1187	1			T8	20		T41	2		T18	1
valid_sources[0x1d]	506	1			T8	3		T55	1		T41	1
valid_sources[0x1e]	827	1			T8	11		T41	2		T20	5
valid_sources[0x1f]	989	1			T8	1		T18	2		T21	17
valid_sources[0x20]	718	1			T8	3		T55	1		T41	1
valid_sources[0x21]	670	1			T8	4		T41	1		T20	4
valid_sources[0x22]	628	1			T8	8		T55	1		T38	1
valid_sources[0x23]	834	1			T8	7		T38	2		T41	2
valid_sources[0x24]	676	1			T8	4		T55	1		T41	2
valid_sources[0x25]	1020	1			T8	8		T41	4		T18	2
valid_sources[0x26]	630	1			T8	17		T55	2		T41	1
valid_sources[0x27]	604	1			T8	7		T9	6		T41	3
valid_sources[0x28]	751	1			T8	12		T41	1		T18	4
valid_sources[0x29]	818	1			T8	4		T41	2		T18	1
valid_sources[0x2a]	692	1			T8	17		T41	1		T18	1
valid_sources[0x2b]	929	1			T8	9		T55	2		T64	1
valid_sources[0x2c]	554	1			T8	17		T40	2		T20	1
valid_sources[0x2d]	1232	1			T8	16		T41	1		T64	1
valid_sources[0x2e]	727	1			T8	9		T144	2		T41	2
valid_sources[0x2f]	658	1			T8	8		T38	1		T20	1
valid_sources[0x30]	768	1			T8	3		T20	2		T18	2
valid_sources[0x31]	1147	1			T8	23		T41	1		T40	1
valid_sources[0x32]	725	1			T8	5		T145	5		T21	6
valid_sources[0x33]	709	1			T8	21		T18	3		T21	16
valid_sources[0x34]	776	1			T8	10		T41	2		T134	11
valid_sources[0x35]	567	1			T8	16		T64	1		T20	11
valid_sources[0x36]	633	1			T1	5		T8	7		T105	2
valid_sources[0x37]	701	1			T1	1		T8	7		T55	2
valid_sources[0x38]	465	1			T8	1		T41	1		T64	1
valid_sources[0x39]	502	1			T8	11		T55	2		T41	3
valid_sources[0x3a]	770	1			T8	7		T64	1		T146	2
valid_sources[0x3b]	633	1			T8	12		T18	1		T21	10
valid_sources[0x3c]	896	1			T8	13		T41	3		T18	5
valid_sources[0x3d]	860	1			T8	4		T41	4		T18	1
valid_sources[0x3e]	667	1			T8	6		T5	3		T41	2
valid_sources[0x3f]	908	1			T8	8		T20	1		T18	2
valid_sources[0x40]	1154	1			T8	10		T41	1		T18	1
valid_sources[0x41]	1124	1			T8	6		T41	7		T18	2
valid_sources[0x42]	513	1			T8	1		T40	1		T18	2
valid_sources[0x43]	530	1			T8	5		T55	3		T20	2
valid_sources[0x44]	872	1			T8	2		T5	3		T38	1
valid_sources[0x45]	697	1			T8	6		T147	1		T41	2
valid_sources[0x46]	1020	1			T8	19		T55	1		T21	5
valid_sources[0x47]	646	1			T8	20		T5	2		T146	3
valid_sources[0x48]	846	1			T8	4		T6	9		T41	2
valid_sources[0x49]	742	1			T8	20		T55	1		T38	1
valid_sources[0x4a]	546	1			T8	4		T134	2		T68	6
valid_sources[0x4b]	711	1			T8	23		T41	1		T64	1
valid_sources[0x4c]	559	1			T8	4		T55	1		T41	2
valid_sources[0x4d]	605	1			T8	1		T40	4		T21	11
valid_sources[0x4e]	676	1			T4	1		T8	13		T41	6
valid_sources[0x4f]	700	1			T8	12		T20	2		T21	20
valid_sources[0x50]	673	1			T8	5		T55	1		T41	2
valid_sources[0x51]	1096	1			T8	8		T55	2		T41	3
valid_sources[0x52]	754	1			T8	14		T55	2		T41	2
valid_sources[0x53]	758	1			T8	23		T55	1		T6	47
valid_sources[0x54]	1029	1			T8	30		T21	11		T22	13
valid_sources[0x55]	792	1			T8	1		T18	2		T91	1
valid_sources[0x56]	555	1			T8	1		T55	2		T68	1
valid_sources[0x57]	543	1			T8	32		T6	6		T41	1
valid_sources[0x58]	929	1			T8	4		T64	1		T20	3
valid_sources[0x59]	565	1			T8	7		T5	2		T55	1
valid_sources[0x5a]	1043	1			T8	4		T41	2		T18	2
valid_sources[0x5b]	672	1			T8	12		T55	1		T41	1
valid_sources[0x5c]	797	1			T8	6		T55	1		T21	7
valid_sources[0x5d]	771	1			T8	17		T41	1		T18	2
valid_sources[0x5e]	990	1			T8	6		T55	1		T41	4
valid_sources[0x5f]	717	1			T1	1		T8	25		T41	3
valid_sources[0x60]	593	1			T8	17		T41	1		T40	1
valid_sources[0x61]	771	1			T8	10		T64	1		T18	5
valid_sources[0x62]	996	1			T8	21		T41	1		T21	13
valid_sources[0x63]	580	1			T4	1		T8	10		T6	1
valid_sources[0x64]	873	1			T8	17		T10	1		T41	2
valid_sources[0x65]	863	1			T8	11		T41	4		T146	1
valid_sources[0x66]	862	1			T8	12		T20	5		T21	14
valid_sources[0x67]	616	1			T8	4		T41	1		T18	1
valid_sources[0x68]	946	1			T8	4		T20	4		T148	2
valid_sources[0x69]	699	1			T1	3		T8	7		T41	1
valid_sources[0x6a]	775	1			T8	12		T5	1		T55	2
valid_sources[0x6b]	563	1			T8	1		T6	1		T20	5
valid_sources[0x6c]	738	1			T41	1		T134	3		T21	8
valid_sources[0x6d]	817	1			T8	4		T21	12		T116	3
valid_sources[0x6e]	856	1			T1	1		T8	4		T18	2
valid_sources[0x6f]	663	1			T8	3		T55	1		T41	1
valid_sources[0x70]	902	1			T8	10		T11	1		T6	2
valid_sources[0x71]	489	1			T8	2		T68	3		T21	1
valid_sources[0x72]	777	1			T8	8		T38	2		T41	1
valid_sources[0x73]	723	1			T8	2		T41	3		T20	5
valid_sources[0x74]	535	1			T8	8		T55	1		T41	1
valid_sources[0x75]	710	1			T8	8		T55	1		T6	14
valid_sources[0x76]	960	1			T8	6		T55	2		T64	1
valid_sources[0x77]	826	1			T8	7		T38	1		T41	2
valid_sources[0x78]	639	1			T8	11		T21	7		T114	2
valid_sources[0x79]	723	1			T8	9		T41	1		T64	1
valid_sources[0x7a]	576	1			T1	1		T8	8		T55	1
valid_sources[0x7b]	713	1			T8	25		T41	1		T18	1
valid_sources[0x7c]	555	1			T8	7		T55	1		T41	1
valid_sources[0x7d]	598	1			T8	15		T40	1		T143	1
valid_sources[0x7e]	534	1			T8	11		T18	2		T21	10
valid_sources[0x7f]	712	1			T8	20		T41	1		T40	1
valid_sources[0x80]	957	1			T8	3		T41	2		T18	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39909

1

T2

12

T8

596

T5

12

values[0x0]

all_enables

biggest_size

55862

1

T1

5

T2

6

T3

1

values[0x1]

all_enables

biggest_size

52713

1

T1

4

T2

2

T8

871