Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16585661

1

T1

14592

T2

27

T3

125286

full_word

165408971

1

T1

144751

T2

237

T3

27907

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	181994292	1			T1	159343		T2	264		T3	153193
auto[TlIntgErrCmd]	124	1			T61	5		T62	4		T63	7
auto[TlIntgErrData]	100	1			T61	7		T62	5		T63	6
auto[TlIntgErrBoth]	116	1			T61	8		T62	1		T63	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87809824

1

T1

79582

T2

130

T3

76582

auto[1]

94184808

1

T1

79761

T2

134

T3

76611

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8107117	1			T1	7332		T2	14		T3	62648
auto[TlIntgErrNone]	partial	auto[1]	8478230	1			T1	7260		T2	13		T3	62638
auto[TlIntgErrNone]	full_word	auto[0]	79702549	1			T1	72250		T2	116		T3	13934
auto[TlIntgErrNone]	full_word	auto[1]	85706396	1			T1	72501		T2	121		T3	13973
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T61	3		T62	2		T63	4
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T61	2		T62	2		T63	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T120	1		T124	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T120	1		T121	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T61	4		T62	2		T63	3
auto[TlIntgErrData]	partial	auto[1]	47	1			T61	2		T62	3		T63	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T128	1		T129	1		T130	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T61	1		T131	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T61	4		T63	1		T131	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T61	3		T62	1		T63	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	1		T125	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T61	1		T121	1		T124	1