Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	918858	1			T2	13		T7	4339		T11	4395
auto[1]	11107514	1			T1	42289		T2	11		T3	59366
auto[2]	703827	1			T2	8		T7	3540		T11	3540
auto[3]	10748528	1			T1	42663		T2	5		T3	59164

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15123428	1			T1	70722		T2	21		T3	4253
auto[1]	2155047	1			T1	6773		T2	6		T3	18303
auto[2]	2194154	1			T1	6776		T2	9		T3	18195
auto[3]	4006098	1			T1	681		T2	1		T3	77779

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10725682

1

T1

84947

T2

37

T3

16

auto[1]

12753045

1

T1

5

T3

118514

T7

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	360209	1			T2	7		T5	15		T6	9000
auto[0]	auto[0]	auto[1]	38017	1			T2	4		T7	34		T11	46
auto[0]	auto[0]	auto[2]	37605	1			T2	2		T7	36		T11	32
auto[0]	auto[0]	auto[3]	88060	1			T7	4267		T11	4317		T6	85
auto[0]	auto[1]	auto[0]	3874418	1			T1	35148		T2	8		T3	1
auto[0]	auto[1]	auto[1]	398847	1			T1	3235		T2	1		T3	1
auto[0]	auto[1]	auto[2]	413400	1			T1	3589		T2	1		T3	1
auto[0]	auto[1]	auto[3]	356602	1			T1	317		T2	1		T3	3
auto[0]	auto[2]	auto[0]	266208	1			T2	4		T7	4		T11	5
auto[0]	auto[2]	auto[1]	33146	1			T2	1		T7	423		T11	379
auto[0]	auto[2]	auto[2]	30558	1			T2	3		T7	24		T11	29
auto[0]	auto[2]	auto[3]	62092	1			T7	3089		T11	3127		T6	59
auto[0]	auto[3]	auto[0]	3661069	1			T1	35569		T2	2		T3	1
auto[0]	auto[3]	auto[1]	387464	1			T1	3538		T3	3		T4	3
auto[0]	auto[3]	auto[2]	401133	1			T1	3187		T2	3		T3	2
auto[0]	auto[3]	auto[3]	316854	1			T1	364		T3	4		T4	10
auto[1]	auto[0]	auto[0]	13243	1			T103	88		T118	210		T137	1
auto[1]	auto[0]	auto[1]	58836	1			T7	1		T103	455		T118	854
auto[1]	auto[0]	auto[2]	58691	1			T103	440		T118	853		T138	950
auto[1]	auto[0]	auto[3]	264197	1			T7	1		T103	2011		T92	5
auto[1]	auto[1]	auto[0]	3472733	1			T3	2162		T56	77318		T90	1
auto[1]	auto[1]	auto[1]	620720	1			T3	8712		T56	7021		T101	4845
auto[1]	auto[1]	auto[2]	595352	1			T3	9492		T56	7961		T18	1
auto[1]	auto[1]	auto[3]	1375442	1			T3	38994		T11	2		T12	1
auto[1]	auto[2]	auto[0]	9028	1			T19	1		T73	2		T137	2
auto[1]	auto[2]	auto[1]	40628	1			T139	3395		T140	1		T141	2847
auto[1]	auto[2]	auto[2]	47951	1			T103	412		T118	774		T138	867
auto[1]	auto[2]	auto[3]	214216	1			T103	1867		T118	3370		T138	3978
auto[1]	auto[3]	auto[0]	3466520	1			T1	5		T3	2089		T56	77066
auto[1]	auto[3]	auto[1]	577389	1			T3	9587		T56	7849		T101	5403
auto[1]	auto[3]	auto[2]	609464	1			T3	8700		T56	7032		T101	4878
auto[1]	auto[3]	auto[3]	1328635	1			T3	38778		T56	676		T101	522