Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1190915468	220198	0	0
ctrl_regwen_rd_A	1190915468	4619	0	0
exec_rd_A	1190915468	4431	0	0
exec_regwen_rd_A	1190915468	4478	0	0
readback_rd_A	1190915468	3099	0	0
readback_regwen_rd_A	1190915468	2642	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190915468	220198	0	0
T5	110057	0	0	0
T6	184365	0	0	0
T8	88113	4192	0	0
T9	1076	0	0	0
T10	53034	0	0	0
T11	263294	0	0	0
T12	76804	0	0	0
T21	0	3200	0	0
T22	0	2662	0	0
T48	0	3002	0	0
T49	0	10432	0	0
T50	0	7588	0	0
T52	0	9286	0	0
T54	74012	0	0	0
T55	394003	0	0	0
T56	395159	0	0	0
T70	0	2358	0	0
T71	0	9001	0	0
T72	0	2617	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190915468	4619	0	0
T21	63030	161	0	0
T31	0	345	0	0
T42	139738	0	0	0
T44	0	452	0	0
T46	179934	0	0	0
T50	0	509	0	0
T107	214998	0	0	0
T108	0	224	0	0
T109	0	256	0	0
T110	0	281	0	0
T111	0	123	0	0
T112	0	149	0	0
T113	0	184	0	0
T114	489811	0	0	0
T115	46177	0	0	0
T116	145549	0	0	0
T117	394537	0	0	0
T118	191315	0	0	0
T119	43325	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190915468	4431	0	0
T21	63030	142	0	0
T31	0	414	0	0
T42	139738	0	0	0
T44	0	455	0	0
T46	179934	0	0	0
T50	0	442	0	0
T107	214998	0	0	0
T108	0	247	0	0
T109	0	237	0	0
T110	0	236	0	0
T111	0	85	0	0
T112	0	222	0	0
T113	0	105	0	0
T114	489811	0	0	0
T115	46177	0	0	0
T116	145549	0	0	0
T117	394537	0	0	0
T118	191315	0	0	0
T119	43325	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190915468	4478	0	0
T21	63030	167	0	0
T31	0	403	0	0
T42	139738	0	0	0
T44	0	458	0	0
T46	179934	0	0	0
T50	0	522	0	0
T107	214998	0	0	0
T108	0	197	0	0
T109	0	215	0	0
T110	0	209	0	0
T111	0	123	0	0
T112	0	212	0	0
T113	0	172	0	0
T114	489811	0	0	0
T115	46177	0	0	0
T116	145549	0	0	0
T117	394537	0	0	0
T118	191315	0	0	0
T119	43325	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190915468	3099	0	0
T21	63030	128	0	0
T31	0	362	0	0
T42	139738	0	0	0
T44	0	373	0	0
T46	179934	0	0	0
T50	0	565	0	0
T107	214998	0	0	0
T108	0	207	0	0
T109	0	170	0	0
T110	0	197	0	0
T111	0	78	0	0
T112	0	162	0	0
T113	0	129	0	0
T114	489811	0	0	0
T115	46177	0	0	0
T116	145549	0	0	0
T117	394537	0	0	0
T118	191315	0	0	0
T119	43325	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1190915468	2642	0	0
T21	63030	83	0	0
T31	0	248	0	0
T42	139738	0	0	0
T44	0	350	0	0
T46	179934	0	0	0
T50	0	469	0	0
T107	214998	0	0	0
T108	0	172	0	0
T109	0	125	0	0
T110	0	155	0	0
T111	0	85	0	0
T112	0	148	0	0
T113	0	163	0	0
T114	489811	0	0	0
T115	46177	0	0	0
T116	145549	0	0	0
T117	394537	0	0	0
T118	191315	0	0	0
T119	43325	0	0	0