Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	338144456	1			T1	264178		T2	20000		T3	8020
instr_valid_dis	299394474	1			T1	264178		T2	20000		T3	8020
instr_en	25714426	1			T7	427106		T20	270372		T26	103298

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13535918	1			T7	65460		T20	182258		T26	22480
sram_ifetch_valid_disable	300001450	1			T1	264178		T2	20000		T3	8020
sram_ifetch_enable	24607088	1			T7	278170		T20	16502		T26	98794

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	338144456	1			T1	264178		T2	20000		T3	8020
hw_debug_en_valid_off	294459460	1			T1	264178		T2	20000		T3	8020
hw_debug_en_on	26690833	1			T7	226898		T20	162724		T26	56342

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	300001450	1			T1	264178		T2	20000		T3	8020
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	285404447	1			T1	264178		T2	20000		T3	8020
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8179321	1			T7	218276		T20	71612		T26	17088
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6496790	1			T7	33296		T20	53260		T26	22480
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1597110	1			T26	22480		T153	100764		T9	18502
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3917796	1			T7	33296		T20	53260		T9	1482
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4336450	1			T7	21786		T20	128998		T153	17546
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1896650	1			T7	20000		T153	17546		T80	11528
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1611444	1			T20	128998		T9	1842		T10	89882
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	12938010	1			T7	91292		T20	33726		T26	30076
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5616022	1			T26	30076		T9	42540		T45	14800
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3188936	1			T7	55718		T20	33726		T153	44070

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11059641	1			T7	168144		T20	16502		T26	86210
lc_exec_en	9416373	1			T7	113820		T26	26266		T153	73360
valid_exec_dis	285975691	1			T1	264178		T2	20000		T3	8020
invalid_exec_dis	38143006	1			T7	343630		T20	198760		T26	121274