Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	139541670	1			T1	120080		T2	10000		T3	3281
triple_byte_access	2786237	1			T1	2392		T3	143		T12	3505
halfword_access	4274768	1			T1	3624		T3	228		T12	5425
byte_access	5977762	1			T1	4770		T3	272		T12	6911
zero_access	1811640	1			T1	1223		T3	86		T12	1765

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76802433

1

T1

66034

T2

4903

T3

2042

auto[1]

77589644

1

T1

66055

T2

5097

T3

1968

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	69246363	1			T1	60025		T2	4903		T3	1650
auto[0]	triple_byte_access	1327625	1			T1	1237		T3	77		T12	1753
auto[0]	halfword_access	2085043	1			T1	1743		T3	139		T12	2683
auto[0]	byte_access	3061321	1			T1	2395		T3	134		T12	3426
auto[0]	zero_access	1082081	1			T1	634		T3	42		T12	886
auto[1]	word_access	70295307	1			T1	60055		T2	5097		T3	1631
auto[1]	triple_byte_access	1458612	1			T1	1155		T3	66		T12	1752
auto[1]	halfword_access	2189725	1			T1	1881		T3	89		T12	2742
auto[1]	byte_access	2916441	1			T1	2375		T3	138		T12	3485
auto[1]	zero_access	729559	1			T1	589		T3	44		T12	879