| T799 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2668129553 |
|
|
Aug 02 07:37:42 PM PDT 24 |
Aug 02 07:41:31 PM PDT 24 |
3277051283 ps |
| T800 |
/workspace/coverage/default/6.sram_ctrl_stress_all.3564633573 |
|
|
Aug 02 07:26:03 PM PDT 24 |
Aug 02 07:55:46 PM PDT 24 |
94228762614 ps |
| T801 |
/workspace/coverage/default/40.sram_ctrl_executable.1341360413 |
|
|
Aug 02 07:34:45 PM PDT 24 |
Aug 02 07:40:17 PM PDT 24 |
22179203721 ps |
| T802 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1653419866 |
|
|
Aug 02 07:25:48 PM PDT 24 |
Aug 02 09:54:29 PM PDT 24 |
3036404742764 ps |
| T803 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3551894313 |
|
|
Aug 02 07:37:40 PM PDT 24 |
Aug 02 07:43:45 PM PDT 24 |
69700173955 ps |
| T804 |
/workspace/coverage/default/18.sram_ctrl_executable.528498037 |
|
|
Aug 02 07:28:03 PM PDT 24 |
Aug 02 07:41:08 PM PDT 24 |
43766111658 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3490291269 |
|
|
Aug 02 07:27:17 PM PDT 24 |
Aug 02 07:43:13 PM PDT 24 |
27017783853 ps |
| T806 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2726942374 |
|
|
Aug 02 07:26:01 PM PDT 24 |
Aug 02 07:26:22 PM PDT 24 |
1358421263 ps |
| T807 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1230275855 |
|
|
Aug 02 07:34:20 PM PDT 24 |
Aug 02 07:35:04 PM PDT 24 |
7907504832 ps |
| T808 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3772086152 |
|
|
Aug 02 07:37:40 PM PDT 24 |
Aug 02 07:40:22 PM PDT 24 |
14097781023 ps |
| T809 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.3372163454 |
|
|
Aug 02 07:27:06 PM PDT 24 |
Aug 02 07:31:13 PM PDT 24 |
11452187363 ps |
| T810 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.1005816898 |
|
|
Aug 02 07:28:14 PM PDT 24 |
Aug 02 07:29:10 PM PDT 24 |
25991304798 ps |
| T811 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4289803753 |
|
|
Aug 02 07:30:34 PM PDT 24 |
Aug 02 07:32:46 PM PDT 24 |
3255471518 ps |
| T812 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.2076909261 |
|
|
Aug 02 07:32:40 PM PDT 24 |
Aug 02 07:32:54 PM PDT 24 |
2550148770 ps |
| T30 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1380489336 |
|
|
Aug 02 07:25:44 PM PDT 24 |
Aug 02 07:25:48 PM PDT 24 |
735815893 ps |
| T813 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.4155985211 |
|
|
Aug 02 07:27:29 PM PDT 24 |
Aug 02 07:28:47 PM PDT 24 |
1397244381 ps |
| T814 |
/workspace/coverage/default/10.sram_ctrl_smoke.3950242488 |
|
|
Aug 02 07:26:24 PM PDT 24 |
Aug 02 07:27:11 PM PDT 24 |
1398857897 ps |
| T815 |
/workspace/coverage/default/37.sram_ctrl_executable.1817691323 |
|
|
Aug 02 07:33:47 PM PDT 24 |
Aug 02 07:51:04 PM PDT 24 |
23410326955 ps |
| T816 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.675118037 |
|
|
Aug 02 07:27:52 PM PDT 24 |
Aug 02 07:43:30 PM PDT 24 |
32324396224 ps |
| T817 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.416158701 |
|
|
Aug 02 07:34:39 PM PDT 24 |
Aug 02 07:35:11 PM PDT 24 |
1589320865 ps |
| T818 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2597878874 |
|
|
Aug 02 07:25:47 PM PDT 24 |
Aug 02 07:26:07 PM PDT 24 |
1595719614 ps |
| T819 |
/workspace/coverage/default/16.sram_ctrl_partial_access.4164851575 |
|
|
Aug 02 07:27:18 PM PDT 24 |
Aug 02 07:27:37 PM PDT 24 |
1323353605 ps |
| T820 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1534058574 |
|
|
Aug 02 07:28:12 PM PDT 24 |
Aug 02 07:31:24 PM PDT 24 |
3157765425 ps |
| T821 |
/workspace/coverage/default/44.sram_ctrl_bijection.2327648164 |
|
|
Aug 02 07:35:46 PM PDT 24 |
Aug 02 08:05:44 PM PDT 24 |
870018783221 ps |
| T822 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.3338061059 |
|
|
Aug 02 07:35:05 PM PDT 24 |
Aug 02 07:36:09 PM PDT 24 |
102539315300 ps |
| T823 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3221598348 |
|
|
Aug 02 07:36:14 PM PDT 24 |
Aug 02 07:36:18 PM PDT 24 |
4804226921 ps |
| T824 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4202696729 |
|
|
Aug 02 07:37:39 PM PDT 24 |
Aug 02 07:37:43 PM PDT 24 |
5573825783 ps |
| T825 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.354421152 |
|
|
Aug 02 07:35:57 PM PDT 24 |
Aug 02 07:38:34 PM PDT 24 |
11003085506 ps |
| T826 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2538662136 |
|
|
Aug 02 07:25:47 PM PDT 24 |
Aug 02 07:30:02 PM PDT 24 |
3758562213 ps |
| T827 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.849322584 |
|
|
Aug 02 07:27:14 PM PDT 24 |
Aug 02 07:28:29 PM PDT 24 |
9451590052 ps |
| T828 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.728804232 |
|
|
Aug 02 07:34:26 PM PDT 24 |
Aug 02 07:49:07 PM PDT 24 |
10806825598 ps |
| T829 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.512337422 |
|
|
Aug 02 07:26:06 PM PDT 24 |
Aug 02 07:26:09 PM PDT 24 |
769227959 ps |
| T830 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1645688180 |
|
|
Aug 02 07:34:49 PM PDT 24 |
Aug 02 07:34:53 PM PDT 24 |
1866814623 ps |
| T831 |
/workspace/coverage/default/28.sram_ctrl_smoke.3418927694 |
|
|
Aug 02 07:30:48 PM PDT 24 |
Aug 02 07:31:06 PM PDT 24 |
2190309284 ps |
| T832 |
/workspace/coverage/default/19.sram_ctrl_bijection.1271746404 |
|
|
Aug 02 07:28:02 PM PDT 24 |
Aug 02 08:02:51 PM PDT 24 |
236724795128 ps |
| T833 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2485876068 |
|
|
Aug 02 07:32:16 PM PDT 24 |
Aug 02 08:05:06 PM PDT 24 |
353027330046 ps |
| T834 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2943193506 |
|
|
Aug 02 07:28:13 PM PDT 24 |
Aug 02 07:28:44 PM PDT 24 |
438067124 ps |
| T835 |
/workspace/coverage/default/44.sram_ctrl_smoke.2404532665 |
|
|
Aug 02 07:35:47 PM PDT 24 |
Aug 02 07:37:12 PM PDT 24 |
427707326 ps |
| T836 |
/workspace/coverage/default/27.sram_ctrl_bijection.828066400 |
|
|
Aug 02 07:30:20 PM PDT 24 |
Aug 02 08:14:42 PM PDT 24 |
547933026774 ps |
| T837 |
/workspace/coverage/default/29.sram_ctrl_executable.4139658978 |
|
|
Aug 02 07:31:22 PM PDT 24 |
Aug 02 07:50:42 PM PDT 24 |
29800663042 ps |
| T838 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.44270091 |
|
|
Aug 02 07:35:49 PM PDT 24 |
Aug 02 07:36:24 PM PDT 24 |
23159369834 ps |
| T839 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3482915590 |
|
|
Aug 02 07:28:43 PM PDT 24 |
Aug 02 07:42:13 PM PDT 24 |
10308484311 ps |
| T50 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3293941623 |
|
|
Aug 02 07:28:57 PM PDT 24 |
Aug 02 07:29:50 PM PDT 24 |
5912778633 ps |
| T840 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2170928858 |
|
|
Aug 02 07:34:53 PM PDT 24 |
Aug 02 07:39:10 PM PDT 24 |
8212505917 ps |
| T841 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3431793086 |
|
|
Aug 02 07:30:49 PM PDT 24 |
Aug 02 07:33:30 PM PDT 24 |
17489678436 ps |
| T842 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3203527930 |
|
|
Aug 02 07:30:20 PM PDT 24 |
Aug 02 07:30:21 PM PDT 24 |
22739528 ps |
| T843 |
/workspace/coverage/default/41.sram_ctrl_smoke.2215128303 |
|
|
Aug 02 07:34:51 PM PDT 24 |
Aug 02 07:37:15 PM PDT 24 |
2596823464 ps |
| T844 |
/workspace/coverage/default/8.sram_ctrl_executable.2194520603 |
|
|
Aug 02 07:26:09 PM PDT 24 |
Aug 02 07:39:48 PM PDT 24 |
5237279533 ps |
| T845 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.1751607674 |
|
|
Aug 02 07:29:49 PM PDT 24 |
Aug 02 07:34:04 PM PDT 24 |
8046399547 ps |
| T846 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3689162437 |
|
|
Aug 02 07:27:51 PM PDT 24 |
Aug 02 07:27:52 PM PDT 24 |
46309537 ps |
| T847 |
/workspace/coverage/default/31.sram_ctrl_regwen.668389626 |
|
|
Aug 02 07:32:17 PM PDT 24 |
Aug 02 07:32:49 PM PDT 24 |
1602731837 ps |
| T848 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.4148852084 |
|
|
Aug 02 07:28:02 PM PDT 24 |
Aug 02 07:28:06 PM PDT 24 |
376078452 ps |
| T849 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2319995040 |
|
|
Aug 02 07:26:24 PM PDT 24 |
Aug 02 07:26:32 PM PDT 24 |
6745642936 ps |
| T850 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.2083448790 |
|
|
Aug 02 07:27:17 PM PDT 24 |
Aug 02 07:28:15 PM PDT 24 |
42210645166 ps |
| T851 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.1657811028 |
|
|
Aug 02 07:34:15 PM PDT 24 |
Aug 02 07:34:19 PM PDT 24 |
1405311592 ps |
| T852 |
/workspace/coverage/default/26.sram_ctrl_smoke.3038617635 |
|
|
Aug 02 07:30:00 PM PDT 24 |
Aug 02 07:30:06 PM PDT 24 |
477790678 ps |
| T853 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.723821628 |
|
|
Aug 02 07:37:02 PM PDT 24 |
Aug 02 07:38:44 PM PDT 24 |
1553223182 ps |
| T854 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3910863044 |
|
|
Aug 02 07:36:47 PM PDT 24 |
Aug 02 07:48:05 PM PDT 24 |
21388628428 ps |
| T855 |
/workspace/coverage/default/44.sram_ctrl_alert_test.2017265707 |
|
|
Aug 02 07:35:57 PM PDT 24 |
Aug 02 07:35:58 PM PDT 24 |
36291525 ps |
| T856 |
/workspace/coverage/default/8.sram_ctrl_bijection.3071050091 |
|
|
Aug 02 07:26:12 PM PDT 24 |
Aug 02 08:04:02 PM PDT 24 |
100703228568 ps |
| T857 |
/workspace/coverage/default/41.sram_ctrl_bijection.3897150671 |
|
|
Aug 02 07:34:54 PM PDT 24 |
Aug 02 07:50:33 PM PDT 24 |
323291584253 ps |
| T858 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3666437376 |
|
|
Aug 02 07:26:14 PM PDT 24 |
Aug 02 07:30:27 PM PDT 24 |
17828833933 ps |
| T859 |
/workspace/coverage/default/49.sram_ctrl_smoke.661824873 |
|
|
Aug 02 07:37:40 PM PDT 24 |
Aug 02 07:38:16 PM PDT 24 |
4575025208 ps |
| T860 |
/workspace/coverage/default/26.sram_ctrl_executable.901576299 |
|
|
Aug 02 07:30:11 PM PDT 24 |
Aug 02 07:35:46 PM PDT 24 |
10181501912 ps |
| T861 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1833234890 |
|
|
Aug 02 07:28:03 PM PDT 24 |
Aug 02 08:34:16 PM PDT 24 |
73337860745 ps |
| T862 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3377784272 |
|
|
Aug 02 07:31:07 PM PDT 24 |
Aug 02 07:31:41 PM PDT 24 |
11410326437 ps |
| T863 |
/workspace/coverage/default/31.sram_ctrl_partial_access.2573842340 |
|
|
Aug 02 07:32:18 PM PDT 24 |
Aug 02 07:33:41 PM PDT 24 |
6154314698 ps |
| T864 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3585889167 |
|
|
Aug 02 07:26:20 PM PDT 24 |
Aug 02 07:31:35 PM PDT 24 |
26322452765 ps |
| T865 |
/workspace/coverage/default/10.sram_ctrl_partial_access.48144910 |
|
|
Aug 02 07:26:24 PM PDT 24 |
Aug 02 07:26:33 PM PDT 24 |
3398053225 ps |
| T866 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3561991692 |
|
|
Aug 02 07:36:32 PM PDT 24 |
Aug 02 07:36:42 PM PDT 24 |
492251354 ps |
| T867 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1685156904 |
|
|
Aug 02 07:29:59 PM PDT 24 |
Aug 02 07:34:55 PM PDT 24 |
51687774780 ps |
| T868 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1774020904 |
|
|
Aug 02 07:29:18 PM PDT 24 |
Aug 02 07:29:51 PM PDT 24 |
22325230301 ps |
| T869 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3563599984 |
|
|
Aug 02 07:36:51 PM PDT 24 |
Aug 02 07:41:40 PM PDT 24 |
4962796295 ps |
| T870 |
/workspace/coverage/default/33.sram_ctrl_stress_all.2421751475 |
|
|
Aug 02 07:32:51 PM PDT 24 |
Aug 02 08:57:00 PM PDT 24 |
301025306949 ps |
| T871 |
/workspace/coverage/default/45.sram_ctrl_regwen.2603055423 |
|
|
Aug 02 07:36:16 PM PDT 24 |
Aug 02 07:56:18 PM PDT 24 |
4275053333 ps |
| T872 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.4034938279 |
|
|
Aug 02 07:27:28 PM PDT 24 |
Aug 02 07:40:07 PM PDT 24 |
11137955033 ps |
| T873 |
/workspace/coverage/default/23.sram_ctrl_partial_access.4260080280 |
|
|
Aug 02 07:29:18 PM PDT 24 |
Aug 02 07:29:32 PM PDT 24 |
1009136155 ps |
| T874 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1061919765 |
|
|
Aug 02 07:27:17 PM PDT 24 |
Aug 02 07:34:41 PM PDT 24 |
73806226555 ps |
| T875 |
/workspace/coverage/default/34.sram_ctrl_alert_test.3114142593 |
|
|
Aug 02 07:33:13 PM PDT 24 |
Aug 02 07:33:13 PM PDT 24 |
15829583 ps |
| T876 |
/workspace/coverage/default/39.sram_ctrl_bijection.525664888 |
|
|
Aug 02 07:34:16 PM PDT 24 |
Aug 02 07:43:43 PM PDT 24 |
8938843218 ps |
| T877 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.206144822 |
|
|
Aug 02 07:31:50 PM PDT 24 |
Aug 02 07:31:56 PM PDT 24 |
144967900 ps |
| T878 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3509797496 |
|
|
Aug 02 07:31:32 PM PDT 24 |
Aug 02 07:35:24 PM PDT 24 |
12092468860 ps |
| T879 |
/workspace/coverage/default/42.sram_ctrl_stress_all.1764941758 |
|
|
Aug 02 07:35:30 PM PDT 24 |
Aug 02 08:04:32 PM PDT 24 |
22192764511 ps |
| T880 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1594360874 |
|
|
Aug 02 07:26:21 PM PDT 24 |
Aug 02 07:26:25 PM PDT 24 |
359489759 ps |
| T881 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1920080322 |
|
|
Aug 02 07:35:44 PM PDT 24 |
Aug 02 07:39:10 PM PDT 24 |
38582649368 ps |
| T882 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2822244843 |
|
|
Aug 02 07:32:51 PM PDT 24 |
Aug 02 07:32:52 PM PDT 24 |
35966513 ps |
| T883 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1965687916 |
|
|
Aug 02 07:26:33 PM PDT 24 |
Aug 02 07:32:25 PM PDT 24 |
172702181699 ps |
| T884 |
/workspace/coverage/default/9.sram_ctrl_regwen.3375676103 |
|
|
Aug 02 07:26:21 PM PDT 24 |
Aug 02 07:56:41 PM PDT 24 |
18126337117 ps |
| T885 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1675406832 |
|
|
Aug 02 07:26:45 PM PDT 24 |
Aug 02 07:26:58 PM PDT 24 |
9178652224 ps |
| T886 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2200851952 |
|
|
Aug 02 07:30:01 PM PDT 24 |
Aug 02 07:49:28 PM PDT 24 |
6767286553 ps |
| T887 |
/workspace/coverage/default/27.sram_ctrl_smoke.3901863908 |
|
|
Aug 02 07:30:22 PM PDT 24 |
Aug 02 07:30:42 PM PDT 24 |
923677585 ps |
| T888 |
/workspace/coverage/default/42.sram_ctrl_partial_access.3728597672 |
|
|
Aug 02 07:35:19 PM PDT 24 |
Aug 02 07:35:35 PM PDT 24 |
2440054622 ps |
| T889 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.2587574292 |
|
|
Aug 02 07:25:38 PM PDT 24 |
Aug 02 07:26:26 PM PDT 24 |
766072485 ps |
| T890 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.121733496 |
|
|
Aug 02 07:29:09 PM PDT 24 |
Aug 02 07:30:37 PM PDT 24 |
28887988742 ps |
| T891 |
/workspace/coverage/default/39.sram_ctrl_executable.3701974049 |
|
|
Aug 02 07:34:27 PM PDT 24 |
Aug 02 07:53:42 PM PDT 24 |
19899971131 ps |
| T892 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3253737411 |
|
|
Aug 02 07:33:26 PM PDT 24 |
Aug 02 08:52:31 PM PDT 24 |
199630735925 ps |
| T893 |
/workspace/coverage/default/12.sram_ctrl_executable.3715480893 |
|
|
Aug 02 07:26:46 PM PDT 24 |
Aug 02 07:39:47 PM PDT 24 |
4932127118 ps |
| T894 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.306556025 |
|
|
Aug 02 07:37:26 PM PDT 24 |
Aug 02 07:37:52 PM PDT 24 |
976741076 ps |
| T895 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2305769317 |
|
|
Aug 02 07:34:13 PM PDT 24 |
Aug 02 07:34:49 PM PDT 24 |
767007530 ps |
| T896 |
/workspace/coverage/default/22.sram_ctrl_stress_all.351891769 |
|
|
Aug 02 07:29:08 PM PDT 24 |
Aug 02 07:54:13 PM PDT 24 |
162223433277 ps |
| T897 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2038254750 |
|
|
Aug 02 07:32:50 PM PDT 24 |
Aug 02 07:32:56 PM PDT 24 |
815727180 ps |
| T898 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1611053519 |
|
|
Aug 02 07:36:38 PM PDT 24 |
Aug 02 07:38:30 PM PDT 24 |
772651126 ps |
| T899 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.135717668 |
|
|
Aug 02 07:26:04 PM PDT 24 |
Aug 02 07:26:17 PM PDT 24 |
3831619237 ps |
| T900 |
/workspace/coverage/default/2.sram_ctrl_bijection.143944274 |
|
|
Aug 02 07:25:50 PM PDT 24 |
Aug 02 07:48:16 PM PDT 24 |
19480180833 ps |
| T901 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2142029687 |
|
|
Aug 02 07:35:16 PM PDT 24 |
Aug 02 07:41:31 PM PDT 24 |
15624306060 ps |
| T902 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.716591196 |
|
|
Aug 02 07:27:04 PM PDT 24 |
Aug 02 07:35:20 PM PDT 24 |
19859742648 ps |
| T903 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3929948661 |
|
|
Aug 02 07:34:26 PM PDT 24 |
Aug 02 07:39:50 PM PDT 24 |
20649126512 ps |
| T904 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.875264318 |
|
|
Aug 02 07:36:09 PM PDT 24 |
Aug 02 07:36:34 PM PDT 24 |
719099203 ps |
| T905 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1218169343 |
|
|
Aug 02 07:26:08 PM PDT 24 |
Aug 02 07:26:12 PM PDT 24 |
1347776211 ps |
| T906 |
/workspace/coverage/default/26.sram_ctrl_stress_all.504749006 |
|
|
Aug 02 07:30:23 PM PDT 24 |
Aug 02 08:46:34 PM PDT 24 |
536686406137 ps |
| T907 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1776285858 |
|
|
Aug 02 07:30:48 PM PDT 24 |
Aug 02 07:30:49 PM PDT 24 |
13900775 ps |
| T908 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2307389028 |
|
|
Aug 02 07:35:46 PM PDT 24 |
Aug 02 07:36:20 PM PDT 24 |
2879449233 ps |
| T909 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1063817625 |
|
|
Aug 02 07:35:03 PM PDT 24 |
Aug 02 07:37:37 PM PDT 24 |
7076540475 ps |
| T910 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2817348784 |
|
|
Aug 02 07:29:50 PM PDT 24 |
Aug 02 07:29:51 PM PDT 24 |
17726652 ps |
| T911 |
/workspace/coverage/default/23.sram_ctrl_alert_test.325631221 |
|
|
Aug 02 07:29:26 PM PDT 24 |
Aug 02 07:29:27 PM PDT 24 |
36481213 ps |
| T912 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1395372635 |
|
|
Aug 02 07:37:41 PM PDT 24 |
Aug 02 07:40:12 PM PDT 24 |
17511421973 ps |
| T913 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2372118260 |
|
|
Aug 02 07:30:33 PM PDT 24 |
Aug 02 07:37:52 PM PDT 24 |
30578033082 ps |
| T914 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2579850911 |
|
|
Aug 02 07:32:29 PM PDT 24 |
Aug 02 07:37:28 PM PDT 24 |
11421332538 ps |
| T915 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.4131287452 |
|
|
Aug 02 07:25:59 PM PDT 24 |
Aug 02 07:26:03 PM PDT 24 |
1766521350 ps |
| T916 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.1858426822 |
|
|
Aug 02 07:35:28 PM PDT 24 |
Aug 02 07:37:16 PM PDT 24 |
3348657680 ps |
| T917 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1251056230 |
|
|
Aug 02 07:25:34 PM PDT 24 |
Aug 02 07:25:36 PM PDT 24 |
40692003 ps |
| T918 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3329182067 |
|
|
Aug 02 07:36:33 PM PDT 24 |
Aug 02 09:30:31 PM PDT 24 |
236596313321 ps |
| T919 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1702607119 |
|
|
Aug 02 07:25:34 PM PDT 24 |
Aug 02 07:26:09 PM PDT 24 |
5804102769 ps |
| T920 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2838600438 |
|
|
Aug 02 07:29:51 PM PDT 24 |
Aug 02 07:29:55 PM PDT 24 |
352093031 ps |
| T921 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1907617701 |
|
|
Aug 02 07:25:50 PM PDT 24 |
Aug 02 07:28:21 PM PDT 24 |
2464980909 ps |
| T922 |
/workspace/coverage/default/4.sram_ctrl_stress_all.1596936707 |
|
|
Aug 02 07:25:59 PM PDT 24 |
Aug 02 09:02:12 PM PDT 24 |
1040347972133 ps |
| T923 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.81865487 |
|
|
Aug 02 07:27:18 PM PDT 24 |
Aug 02 07:28:08 PM PDT 24 |
7477420202 ps |
| T924 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.360036439 |
|
|
Aug 02 07:32:39 PM PDT 24 |
Aug 02 07:32:42 PM PDT 24 |
691894489 ps |
| T925 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3959998769 |
|
|
Aug 02 07:25:52 PM PDT 24 |
Aug 02 07:32:23 PM PDT 24 |
44200314115 ps |
| T926 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1280615101 |
|
|
Aug 02 07:31:06 PM PDT 24 |
Aug 02 07:38:07 PM PDT 24 |
70541398558 ps |
| T927 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.590742492 |
|
|
Aug 02 07:34:15 PM PDT 24 |
Aug 02 07:35:19 PM PDT 24 |
1941345664 ps |
| T928 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.745577860 |
|
|
Aug 02 07:31:31 PM PDT 24 |
Aug 02 07:31:40 PM PDT 24 |
1314103024 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2973814464 |
|
|
Aug 02 07:34:13 PM PDT 24 |
Aug 02 07:34:30 PM PDT 24 |
2077897134 ps |
| T930 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3870256092 |
|
|
Aug 02 07:28:02 PM PDT 24 |
Aug 02 07:35:12 PM PDT 24 |
6553926848 ps |
| T931 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1254944220 |
|
|
Aug 02 07:26:03 PM PDT 24 |
Aug 02 07:26:06 PM PDT 24 |
359222966 ps |
| T932 |
/workspace/coverage/default/48.sram_ctrl_smoke.1944490138 |
|
|
Aug 02 07:37:26 PM PDT 24 |
Aug 02 07:39:40 PM PDT 24 |
769105834 ps |
| T933 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.2830262093 |
|
|
Aug 02 07:26:02 PM PDT 24 |
Aug 02 07:26:53 PM PDT 24 |
16518755451 ps |
| T934 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1297342822 |
|
|
Aug 02 07:32:31 PM PDT 24 |
Aug 02 08:44:42 PM PDT 24 |
310559186292 ps |
| T935 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2958066567 |
|
|
Aug 02 07:25:34 PM PDT 24 |
Aug 02 07:32:23 PM PDT 24 |
12098674272 ps |
| T936 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2534521294 |
|
|
Aug 02 07:28:34 PM PDT 24 |
Aug 02 07:32:55 PM PDT 24 |
13538649531 ps |
| T937 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2310830123 |
|
|
Aug 02 07:37:02 PM PDT 24 |
Aug 02 07:38:42 PM PDT 24 |
62352337281 ps |
| T31 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.3393216666 |
|
|
Aug 02 07:25:51 PM PDT 24 |
Aug 02 07:25:53 PM PDT 24 |
1009905289 ps |
| T938 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1396662788 |
|
|
Aug 02 07:25:36 PM PDT 24 |
Aug 02 07:25:39 PM PDT 24 |
1401624150 ps |
| T939 |
/workspace/coverage/default/30.sram_ctrl_partial_access.719280912 |
|
|
Aug 02 07:31:31 PM PDT 24 |
Aug 02 07:31:48 PM PDT 24 |
2315347852 ps |
| T940 |
/workspace/coverage/default/4.sram_ctrl_partial_access.2004933265 |
|
|
Aug 02 07:25:46 PM PDT 24 |
Aug 02 07:26:08 PM PDT 24 |
3507248686 ps |
| T941 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.645836173 |
|
|
Aug 02 07:27:19 PM PDT 24 |
Aug 02 07:27:22 PM PDT 24 |
345951477 ps |
| T942 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.4255693252 |
|
|
Aug 02 07:28:04 PM PDT 24 |
Aug 02 07:28:13 PM PDT 24 |
1389057763 ps |
| T77 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1643959666 |
|
|
Aug 02 07:21:58 PM PDT 24 |
Aug 02 07:21:58 PM PDT 24 |
24517749 ps |
| T943 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1530281479 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:03 PM PDT 24 |
356494630 ps |
| T78 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3003947229 |
|
|
Aug 02 07:22:03 PM PDT 24 |
Aug 02 07:22:34 PM PDT 24 |
13680877800 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4260095709 |
|
|
Aug 02 07:21:33 PM PDT 24 |
Aug 02 07:21:34 PM PDT 24 |
30179836 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4183957768 |
|
|
Aug 02 07:22:05 PM PDT 24 |
Aug 02 07:22:09 PM PDT 24 |
125380117 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.993666559 |
|
|
Aug 02 07:21:32 PM PDT 24 |
Aug 02 07:21:34 PM PDT 24 |
27423600 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4009305554 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
74530240 ps |
| T86 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4254100259 |
|
|
Aug 02 07:22:03 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
12791880 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1708199967 |
|
|
Aug 02 07:21:33 PM PDT 24 |
Aug 02 07:21:34 PM PDT 24 |
17789210 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.643801000 |
|
|
Aug 02 07:21:56 PM PDT 24 |
Aug 02 07:22:20 PM PDT 24 |
7744014668 ps |
| T947 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3794279014 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:01 PM PDT 24 |
27926756 ps |
| T948 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.56725431 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:05 PM PDT 24 |
454513543 ps |
| T89 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.804498710 |
|
|
Aug 02 07:22:03 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
79462868 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.10064279 |
|
|
Aug 02 07:21:58 PM PDT 24 |
Aug 02 07:22:02 PM PDT 24 |
370904941 ps |
| T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1296100337 |
|
|
Aug 02 07:22:02 PM PDT 24 |
Aug 02 07:22:03 PM PDT 24 |
21735096 ps |
| T120 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3847352314 |
|
|
Aug 02 07:22:02 PM PDT 24 |
Aug 02 07:22:54 PM PDT 24 |
14733674787 ps |
| T74 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1570852679 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:21:59 PM PDT 24 |
144163890 ps |
| T91 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1705976371 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:26 PM PDT 24 |
7718042442 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1902052844 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
357683376 ps |
| T92 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1201754934 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:28 PM PDT 24 |
14733848832 ps |
| T93 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1740897624 |
|
|
Aug 02 07:21:56 PM PDT 24 |
Aug 02 07:21:57 PM PDT 24 |
17754703 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1038002206 |
|
|
Aug 02 07:22:02 PM PDT 24 |
Aug 02 07:22:02 PM PDT 24 |
19498036 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.801346492 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:05 PM PDT 24 |
39818336 ps |
| T953 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3083569087 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
23345287 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3561850681 |
|
|
Aug 02 07:22:00 PM PDT 24 |
Aug 02 07:22:02 PM PDT 24 |
124652100 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1449488224 |
|
|
Aug 02 07:21:58 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
394330009 ps |
| T955 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4246280892 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:32 PM PDT 24 |
9147166085 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2770078634 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:23:00 PM PDT 24 |
33485740065 ps |
| T75 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3696203789 |
|
|
Aug 02 07:21:55 PM PDT 24 |
Aug 02 07:21:57 PM PDT 24 |
771679270 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.483129854 |
|
|
Aug 02 07:21:30 PM PDT 24 |
Aug 02 07:21:58 PM PDT 24 |
7842107349 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2303910240 |
|
|
Aug 02 07:21:13 PM PDT 24 |
Aug 02 07:21:14 PM PDT 24 |
14008839 ps |
| T76 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1154856745 |
|
|
Aug 02 07:22:03 PM PDT 24 |
Aug 02 07:22:05 PM PDT 24 |
130031656 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3678909050 |
|
|
Aug 02 07:22:00 PM PDT 24 |
Aug 02 07:22:01 PM PDT 24 |
87727709 ps |
| T140 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2801519870 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:21:59 PM PDT 24 |
1480165546 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2898663854 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:07 PM PDT 24 |
364635809 ps |
| T111 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.919979624 |
|
|
Aug 02 07:21:56 PM PDT 24 |
Aug 02 07:22:57 PM PDT 24 |
100657781210 ps |
| T97 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1938224501 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:26 PM PDT 24 |
3859357469 ps |
| T958 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2585907512 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:21:58 PM PDT 24 |
21268860 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.203365566 |
|
|
Aug 02 07:21:17 PM PDT 24 |
Aug 02 07:21:17 PM PDT 24 |
18617667 ps |
| T145 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.132779559 |
|
|
Aug 02 07:21:17 PM PDT 24 |
Aug 02 07:21:18 PM PDT 24 |
456995133 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1145679280 |
|
|
Aug 02 07:22:03 PM PDT 24 |
Aug 02 07:22:06 PM PDT 24 |
363947959 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.843976113 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:22:01 PM PDT 24 |
495648182 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3810038993 |
|
|
Aug 02 07:21:31 PM PDT 24 |
Aug 02 07:21:32 PM PDT 24 |
52680170 ps |
| T962 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2679201384 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
42259656 ps |
| T963 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3993319785 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
17894343 ps |
| T964 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1886114344 |
|
|
Aug 02 07:22:03 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
38788121 ps |
| T965 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.608418354 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
76337262 ps |
| T143 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.545308552 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:05 PM PDT 24 |
136853292 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1349389210 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:05 PM PDT 24 |
202608919 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1843706598 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:05 PM PDT 24 |
65491969 ps |
| T141 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2538686500 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:21:59 PM PDT 24 |
202824932 ps |
| T968 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2060311574 |
|
|
Aug 02 07:21:55 PM PDT 24 |
Aug 02 07:21:56 PM PDT 24 |
22563961 ps |
| T99 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.278002658 |
|
|
Aug 02 07:21:03 PM PDT 24 |
Aug 02 07:21:53 PM PDT 24 |
7146744066 ps |
| T969 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1749777791 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:03 PM PDT 24 |
76478732 ps |
| T100 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3514994756 |
|
|
Aug 02 07:21:56 PM PDT 24 |
Aug 02 07:22:28 PM PDT 24 |
14222052551 ps |
| T970 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4052774603 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:21:58 PM PDT 24 |
12552933 ps |
| T142 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1621323429 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:07 PM PDT 24 |
2504826850 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2963853687 |
|
|
Aug 02 07:21:11 PM PDT 24 |
Aug 02 07:21:12 PM PDT 24 |
28682670 ps |
| T972 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2612278158 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
92243649 ps |
| T144 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2744216564 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:03 PM PDT 24 |
623419626 ps |
| T973 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.16818102 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:02 PM PDT 24 |
72579954 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2729991634 |
|
|
Aug 02 07:21:17 PM PDT 24 |
Aug 02 07:21:17 PM PDT 24 |
22144032 ps |
| T101 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2004007869 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:22:47 PM PDT 24 |
8146424504 ps |
| T975 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3329099762 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:02 PM PDT 24 |
84733781 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.293632981 |
|
|
Aug 02 07:21:20 PM PDT 24 |
Aug 02 07:21:21 PM PDT 24 |
69989301 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3893220817 |
|
|
Aug 02 07:22:02 PM PDT 24 |
Aug 02 07:22:06 PM PDT 24 |
1316961489 ps |
| T978 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2622568071 |
|
|
Aug 02 07:21:32 PM PDT 24 |
Aug 02 07:21:36 PM PDT 24 |
1831262171 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3854636614 |
|
|
Aug 02 07:21:08 PM PDT 24 |
Aug 02 07:21:08 PM PDT 24 |
39431413 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.366906190 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
16868141 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4260091586 |
|
|
Aug 02 07:21:16 PM PDT 24 |
Aug 02 07:21:18 PM PDT 24 |
20394684 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3405687065 |
|
|
Aug 02 07:21:58 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
58381598 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3781601741 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
411924133 ps |
| T113 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4179274235 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:05 PM PDT 24 |
13015288 ps |
| T983 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3372744714 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
24025002 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4237120296 |
|
|
Aug 02 07:21:58 PM PDT 24 |
Aug 02 07:22:02 PM PDT 24 |
663472346 ps |
| T114 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1890092129 |
|
|
Aug 02 07:21:20 PM PDT 24 |
Aug 02 07:21:21 PM PDT 24 |
14933624 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2292190517 |
|
|
Aug 02 07:21:32 PM PDT 24 |
Aug 02 07:21:33 PM PDT 24 |
61359363 ps |
| T146 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1353476787 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
1990283664 ps |
| T148 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2764831475 |
|
|
Aug 02 07:21:32 PM PDT 24 |
Aug 02 07:21:35 PM PDT 24 |
188790834 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1022256114 |
|
|
Aug 02 07:22:00 PM PDT 24 |
Aug 02 07:22:03 PM PDT 24 |
247586819 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1047863186 |
|
|
Aug 02 07:21:52 PM PDT 24 |
Aug 02 07:21:53 PM PDT 24 |
21442013 ps |
| T988 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2545230167 |
|
|
Aug 02 07:21:58 PM PDT 24 |
Aug 02 07:22:01 PM PDT 24 |
80891920 ps |
| T149 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3938646281 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:06 PM PDT 24 |
182409955 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1073621011 |
|
|
Aug 02 07:22:02 PM PDT 24 |
Aug 02 07:22:05 PM PDT 24 |
177092090 ps |
| T990 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1743581195 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:07 PM PDT 24 |
39711527 ps |
| T991 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2164498810 |
|
|
Aug 02 07:21:58 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
146269319 ps |
| T992 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2242224729 |
|
|
Aug 02 07:21:32 PM PDT 24 |
Aug 02 07:21:35 PM PDT 24 |
61538530 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2503286894 |
|
|
Aug 02 07:21:17 PM PDT 24 |
Aug 02 07:21:21 PM PDT 24 |
1487776667 ps |
| T994 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2203205668 |
|
|
Aug 02 07:22:05 PM PDT 24 |
Aug 02 07:22:06 PM PDT 24 |
20680164 ps |
| T147 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2210584259 |
|
|
Aug 02 07:22:01 PM PDT 24 |
Aug 02 07:22:03 PM PDT 24 |
408940916 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1697610959 |
|
|
Aug 02 07:21:17 PM PDT 24 |
Aug 02 07:21:21 PM PDT 24 |
1426444122 ps |
| T152 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3821028306 |
|
|
Aug 02 07:22:04 PM PDT 24 |
Aug 02 07:22:06 PM PDT 24 |
362847548 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2939221187 |
|
|
Aug 02 07:21:56 PM PDT 24 |
Aug 02 07:21:57 PM PDT 24 |
83254933 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.342082114 |
|
|
Aug 02 07:22:00 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
441159679 ps |
| T998 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3181919539 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:00 PM PDT 24 |
20737759 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2319095127 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:01 PM PDT 24 |
41252456 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.605464447 |
|
|
Aug 02 07:21:32 PM PDT 24 |
Aug 02 07:21:34 PM PDT 24 |
130959576 ps |
| T1001 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1005533120 |
|
|
Aug 02 07:21:57 PM PDT 24 |
Aug 02 07:21:58 PM PDT 24 |
138118823 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1325774490 |
|
|
Aug 02 07:21:56 PM PDT 24 |
Aug 02 07:21:56 PM PDT 24 |
13915799 ps |
| T1003 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4089997846 |
|
|
Aug 02 07:21:07 PM PDT 24 |
Aug 02 07:21:10 PM PDT 24 |
129689777 ps |
| T150 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1941682338 |
|
|
Aug 02 07:22:00 PM PDT 24 |
Aug 02 07:22:02 PM PDT 24 |
352246751 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2020248345 |
|
|
Aug 02 07:21:58 PM PDT 24 |
Aug 02 07:21:58 PM PDT 24 |
38558705 ps |
| T1005 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1195701931 |
|
|
Aug 02 07:21:59 PM PDT 24 |
Aug 02 07:22:04 PM PDT 24 |
2889025106 ps |