Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	330151626	1			T1	16976		T3	393212		T5	6100
instr_valid_dis	293604709	1			T1	16976		T3	393212		T5	6100
instr_en	27093907	1			T12	288910		T28	296652		T29	137876

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12331804	1			T12	62978		T28	28022		T29	20000
sram_ifetch_valid_disable	290020276	1			T1	16976		T3	393212		T5	6100
sram_ifetch_enable	27799546	1			T12	283382		T28	175976		T29	110840

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	330151626	1			T1	16976		T3	393212		T5	6100
hw_debug_en_valid_off	292771256	1			T1	16976		T3	393212		T5	6100
hw_debug_en_on	24754822	1			T12	103378		T28	130712		T29	38400

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	290020276	1			T1	16976		T3	393212		T5	6100
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	274794161	1			T1	16976		T3	393212		T5	6100
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11583219	1			T12	113378		T28	92654		T29	117876
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6455728	1			T12	16452		T28	2288		T22	41224
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1616016	1			T22	1340		T23	88368		T136	30186
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4040296	1			T12	16452		T28	2288		T22	39884
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3686332	1			T12	20430		T28	25734		T29	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1689966	1			T22	53106		T23	49174		T138	6918
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1478816	1			T12	20000		T28	25734		T29	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10811404	1			T12	63410		T28	47450		T29	18400
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5765550	1			T22	34912		T47	2204		T136	1796
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3492046	1			T12	51522		T28	23522		T29	18400

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9239122	1			T12	112984		T28	175976		T22	97486
lc_exec_en	10257086	1			T12	19538		T28	57528		T22	162038
valid_exec_dis	289934428	1			T1	16976		T3	393212		T5	6100
invalid_exec_dis	40131350	1			T12	346360		T28	203998		T29	130840