Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	135953021	1			T1	1382		T3	196606		T5	3050
triple_byte_access	2798570	1			T1	28		T6	3086		T11	3385
halfword_access	4285395	1			T1	39		T6	4733		T11	5091
byte_access	5983539	1			T1	50		T6	6283		T11	7046
zero_access	1801049	1			T1	7		T6	1670		T11	1677

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75059136

1

T1

764

T3

65536

T5

1563

auto[1]

75762438

1

T1

742

T3

131070

T5

1487

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	67493732	1			T1	711		T3	65536		T5	1563
auto[0]	triple_byte_access	1336929	1			T1	15		T6	1557		T11	1690
auto[0]	halfword_access	2093604	1			T1	15		T6	2310		T11	2582
auto[0]	byte_access	3064097	1			T1	20		T6	3104		T11	3515
auto[0]	zero_access	1070774	1			T1	3		T6	844		T11	818
auto[1]	word_access	68459289	1			T1	671		T3	131070		T5	1487
auto[1]	triple_byte_access	1461641	1			T1	13		T6	1529		T11	1695
auto[1]	halfword_access	2191791	1			T1	24		T6	2423		T11	2509
auto[1]	byte_access	2919442	1			T1	30		T6	3179		T11	3531
auto[1]	zero_access	730275	1			T1	4		T6	826		T11	859