| T794 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1352207363 |
|
|
Aug 03 06:09:11 PM PDT 24 |
Aug 03 06:14:02 PM PDT 24 |
6454228970 ps |
| T795 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3656670187 |
|
|
Aug 03 06:20:50 PM PDT 24 |
Aug 03 06:23:07 PM PDT 24 |
8331660086 ps |
| T796 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1222991929 |
|
|
Aug 03 06:16:55 PM PDT 24 |
Aug 03 06:20:47 PM PDT 24 |
3128132815 ps |
| T797 |
/workspace/coverage/default/45.sram_ctrl_bijection.2270310397 |
|
|
Aug 03 06:19:22 PM PDT 24 |
Aug 03 06:57:47 PM PDT 24 |
144105053614 ps |
| T798 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.4193668732 |
|
|
Aug 03 06:10:06 PM PDT 24 |
Aug 03 06:32:27 PM PDT 24 |
40113814845 ps |
| T799 |
/workspace/coverage/default/10.sram_ctrl_smoke.3349579912 |
|
|
Aug 03 06:09:07 PM PDT 24 |
Aug 03 06:09:31 PM PDT 24 |
6703203901 ps |
| T800 |
/workspace/coverage/default/24.sram_ctrl_executable.1478037076 |
|
|
Aug 03 06:13:20 PM PDT 24 |
Aug 03 06:23:34 PM PDT 24 |
14594772046 ps |
| T801 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.4259455540 |
|
|
Aug 03 06:20:23 PM PDT 24 |
Aug 03 06:35:15 PM PDT 24 |
8370833716 ps |
| T802 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2163867740 |
|
|
Aug 03 06:08:39 PM PDT 24 |
Aug 03 06:09:27 PM PDT 24 |
32341147638 ps |
| T803 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2122651543 |
|
|
Aug 03 06:09:43 PM PDT 24 |
Aug 03 06:10:14 PM PDT 24 |
2966059911 ps |
| T804 |
/workspace/coverage/default/49.sram_ctrl_executable.1970093178 |
|
|
Aug 03 06:20:50 PM PDT 24 |
Aug 03 06:53:44 PM PDT 24 |
124830600864 ps |
| T805 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2669375611 |
|
|
Aug 03 06:14:11 PM PDT 24 |
Aug 03 06:14:31 PM PDT 24 |
4112567366 ps |
| T806 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.1851999294 |
|
|
Aug 03 06:15:22 PM PDT 24 |
Aug 03 06:19:49 PM PDT 24 |
49245969517 ps |
| T807 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2137085909 |
|
|
Aug 03 06:12:11 PM PDT 24 |
Aug 03 06:12:31 PM PDT 24 |
1550296584 ps |
| T808 |
/workspace/coverage/default/6.sram_ctrl_regwen.1857730695 |
|
|
Aug 03 06:07:55 PM PDT 24 |
Aug 03 06:15:46 PM PDT 24 |
10025620733 ps |
| T809 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1201288745 |
|
|
Aug 03 06:11:22 PM PDT 24 |
Aug 03 06:12:34 PM PDT 24 |
2994196401 ps |
| T810 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3530367631 |
|
|
Aug 03 06:14:21 PM PDT 24 |
Aug 03 06:17:21 PM PDT 24 |
22343661969 ps |
| T811 |
/workspace/coverage/default/46.sram_ctrl_bijection.2116691003 |
|
|
Aug 03 06:19:38 PM PDT 24 |
Aug 03 06:51:20 PM PDT 24 |
53316011121 ps |
| T812 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3606057886 |
|
|
Aug 03 06:20:23 PM PDT 24 |
Aug 03 06:25:56 PM PDT 24 |
10710804458 ps |
| T813 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1906877291 |
|
|
Aug 03 06:11:35 PM PDT 24 |
Aug 03 06:14:19 PM PDT 24 |
1019096121 ps |
| T814 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.2713402567 |
|
|
Aug 03 06:18:03 PM PDT 24 |
Aug 03 06:18:31 PM PDT 24 |
12008935851 ps |
| T815 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3867053799 |
|
|
Aug 03 06:19:45 PM PDT 24 |
Aug 03 06:23:04 PM PDT 24 |
11953609220 ps |
| T816 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.390858750 |
|
|
Aug 03 06:05:54 PM PDT 24 |
Aug 03 06:06:11 PM PDT 24 |
2691950277 ps |
| T817 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3159342450 |
|
|
Aug 03 06:15:10 PM PDT 24 |
Aug 03 06:15:17 PM PDT 24 |
701014588 ps |
| T818 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1127676242 |
|
|
Aug 03 06:08:44 PM PDT 24 |
Aug 03 06:10:55 PM PDT 24 |
2062690493 ps |
| T819 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2166796165 |
|
|
Aug 03 06:09:42 PM PDT 24 |
Aug 03 06:37:23 PM PDT 24 |
18739992223 ps |
| T820 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2378148908 |
|
|
Aug 03 06:17:31 PM PDT 24 |
Aug 03 06:20:35 PM PDT 24 |
34981456755 ps |
| T821 |
/workspace/coverage/default/1.sram_ctrl_executable.1195719790 |
|
|
Aug 03 06:06:14 PM PDT 24 |
Aug 03 06:15:20 PM PDT 24 |
9215173790 ps |
| T822 |
/workspace/coverage/default/0.sram_ctrl_alert_test.778114430 |
|
|
Aug 03 06:06:00 PM PDT 24 |
Aug 03 06:06:00 PM PDT 24 |
15377704 ps |
| T823 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1202751709 |
|
|
Aug 03 06:09:24 PM PDT 24 |
Aug 03 06:10:58 PM PDT 24 |
776772782 ps |
| T824 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1223869612 |
|
|
Aug 03 06:13:29 PM PDT 24 |
Aug 03 06:13:46 PM PDT 24 |
1061066131 ps |
| T825 |
/workspace/coverage/default/26.sram_ctrl_regwen.513130470 |
|
|
Aug 03 06:13:53 PM PDT 24 |
Aug 03 06:37:41 PM PDT 24 |
21087150371 ps |
| T826 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.4220621792 |
|
|
Aug 03 06:13:32 PM PDT 24 |
Aug 03 06:13:58 PM PDT 24 |
4379512780 ps |
| T827 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2659725005 |
|
|
Aug 03 06:16:36 PM PDT 24 |
Aug 03 06:34:14 PM PDT 24 |
41810490009 ps |
| T828 |
/workspace/coverage/default/30.sram_ctrl_executable.696000518 |
|
|
Aug 03 06:14:54 PM PDT 24 |
Aug 03 06:20:26 PM PDT 24 |
19563206639 ps |
| T829 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3666485402 |
|
|
Aug 03 06:08:52 PM PDT 24 |
Aug 03 06:12:37 PM PDT 24 |
15912169750 ps |
| T830 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3568153887 |
|
|
Aug 03 06:14:44 PM PDT 24 |
Aug 03 06:16:32 PM PDT 24 |
59882652296 ps |
| T831 |
/workspace/coverage/default/32.sram_ctrl_alert_test.570342713 |
|
|
Aug 03 06:15:48 PM PDT 24 |
Aug 03 06:15:49 PM PDT 24 |
23264802 ps |
| T832 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2028106967 |
|
|
Aug 03 06:11:50 PM PDT 24 |
Aug 03 06:11:50 PM PDT 24 |
44218862 ps |
| T833 |
/workspace/coverage/default/4.sram_ctrl_smoke.410017115 |
|
|
Aug 03 06:07:15 PM PDT 24 |
Aug 03 06:07:35 PM PDT 24 |
2279853376 ps |
| T834 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1141809248 |
|
|
Aug 03 06:20:46 PM PDT 24 |
Aug 03 06:20:55 PM PDT 24 |
1316943021 ps |
| T835 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3853655057 |
|
|
Aug 03 06:14:20 PM PDT 24 |
Aug 03 07:21:47 PM PDT 24 |
56209487996 ps |
| T836 |
/workspace/coverage/default/33.sram_ctrl_stress_all.4120865037 |
|
|
Aug 03 06:15:59 PM PDT 24 |
Aug 03 07:36:48 PM PDT 24 |
165742525626 ps |
| T837 |
/workspace/coverage/default/46.sram_ctrl_alert_test.4025290955 |
|
|
Aug 03 06:20:03 PM PDT 24 |
Aug 03 06:20:04 PM PDT 24 |
40333251 ps |
| T838 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.1140918722 |
|
|
Aug 03 06:11:45 PM PDT 24 |
Aug 03 06:13:55 PM PDT 24 |
793355122 ps |
| T839 |
/workspace/coverage/default/19.sram_ctrl_stress_all.311906993 |
|
|
Aug 03 06:11:47 PM PDT 24 |
Aug 03 07:01:09 PM PDT 24 |
43539741297 ps |
| T840 |
/workspace/coverage/default/0.sram_ctrl_regwen.3272695662 |
|
|
Aug 03 06:06:01 PM PDT 24 |
Aug 03 06:14:10 PM PDT 24 |
5253950871 ps |
| T841 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1068297957 |
|
|
Aug 03 06:19:45 PM PDT 24 |
Aug 03 06:25:00 PM PDT 24 |
12024906833 ps |
| T842 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2273809967 |
|
|
Aug 03 06:15:25 PM PDT 24 |
Aug 03 07:15:30 PM PDT 24 |
33749646563 ps |
| T843 |
/workspace/coverage/default/13.sram_ctrl_executable.1820009908 |
|
|
Aug 03 06:09:58 PM PDT 24 |
Aug 03 06:21:35 PM PDT 24 |
5302418367 ps |
| T844 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.220669143 |
|
|
Aug 03 06:15:37 PM PDT 24 |
Aug 03 06:17:10 PM PDT 24 |
54245006967 ps |
| T845 |
/workspace/coverage/default/10.sram_ctrl_executable.1544227851 |
|
|
Aug 03 06:09:11 PM PDT 24 |
Aug 03 06:10:47 PM PDT 24 |
4829000893 ps |
| T846 |
/workspace/coverage/default/9.sram_ctrl_partial_access.1022244876 |
|
|
Aug 03 06:08:52 PM PDT 24 |
Aug 03 06:09:14 PM PDT 24 |
1353831028 ps |
| T847 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.279044645 |
|
|
Aug 03 06:11:34 PM PDT 24 |
Aug 03 06:17:57 PM PDT 24 |
25261291244 ps |
| T848 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.130875798 |
|
|
Aug 03 06:13:25 PM PDT 24 |
Aug 03 06:23:26 PM PDT 24 |
42286904281 ps |
| T849 |
/workspace/coverage/default/3.sram_ctrl_executable.2476744175 |
|
|
Aug 03 06:07:00 PM PDT 24 |
Aug 03 06:29:51 PM PDT 24 |
21783213909 ps |
| T850 |
/workspace/coverage/default/36.sram_ctrl_stress_all.4181436092 |
|
|
Aug 03 06:16:49 PM PDT 24 |
Aug 03 08:27:46 PM PDT 24 |
265836185592 ps |
| T851 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2392749009 |
|
|
Aug 03 06:09:10 PM PDT 24 |
Aug 03 06:10:16 PM PDT 24 |
800058844 ps |
| T852 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2970261339 |
|
|
Aug 03 06:15:42 PM PDT 24 |
Aug 03 06:15:45 PM PDT 24 |
1423494913 ps |
| T853 |
/workspace/coverage/default/29.sram_ctrl_partial_access.2358586232 |
|
|
Aug 03 06:14:46 PM PDT 24 |
Aug 03 06:15:09 PM PDT 24 |
930434815 ps |
| T854 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1515445602 |
|
|
Aug 03 06:09:23 PM PDT 24 |
Aug 03 06:19:44 PM PDT 24 |
7217077291 ps |
| T855 |
/workspace/coverage/default/48.sram_ctrl_executable.959751679 |
|
|
Aug 03 06:20:30 PM PDT 24 |
Aug 03 06:32:31 PM PDT 24 |
60154337150 ps |
| T856 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.2353220128 |
|
|
Aug 03 06:12:29 PM PDT 24 |
Aug 03 06:12:34 PM PDT 24 |
4204004622 ps |
| T857 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4023648699 |
|
|
Aug 03 06:09:29 PM PDT 24 |
Aug 03 06:11:59 PM PDT 24 |
20487683057 ps |
| T858 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.836660884 |
|
|
Aug 03 06:18:13 PM PDT 24 |
Aug 03 06:22:45 PM PDT 24 |
26260549864 ps |
| T859 |
/workspace/coverage/default/40.sram_ctrl_smoke.2048204782 |
|
|
Aug 03 06:17:57 PM PDT 24 |
Aug 03 06:18:10 PM PDT 24 |
1597380441 ps |
| T860 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2628247654 |
|
|
Aug 03 06:06:12 PM PDT 24 |
Aug 03 06:06:16 PM PDT 24 |
363172611 ps |
| T861 |
/workspace/coverage/default/46.sram_ctrl_partial_access.316022349 |
|
|
Aug 03 06:19:45 PM PDT 24 |
Aug 03 06:19:54 PM PDT 24 |
728138580 ps |
| T862 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2628420925 |
|
|
Aug 03 06:10:11 PM PDT 24 |
Aug 03 06:12:15 PM PDT 24 |
1624322558 ps |
| T863 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3895239610 |
|
|
Aug 03 06:12:06 PM PDT 24 |
Aug 03 06:15:14 PM PDT 24 |
43114276351 ps |
| T864 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1544510942 |
|
|
Aug 03 06:06:42 PM PDT 24 |
Aug 03 06:06:55 PM PDT 24 |
615989373 ps |
| T865 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.4129988335 |
|
|
Aug 03 06:05:55 PM PDT 24 |
Aug 03 06:13:56 PM PDT 24 |
82073075204 ps |
| T866 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.4204937022 |
|
|
Aug 03 06:12:13 PM PDT 24 |
Aug 03 06:19:53 PM PDT 24 |
13241004410 ps |
| T867 |
/workspace/coverage/default/3.sram_ctrl_smoke.497044125 |
|
|
Aug 03 06:06:48 PM PDT 24 |
Aug 03 06:06:57 PM PDT 24 |
1871467528 ps |
| T868 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3031289167 |
|
|
Aug 03 06:10:09 PM PDT 24 |
Aug 03 06:10:10 PM PDT 24 |
18263143 ps |
| T869 |
/workspace/coverage/default/6.sram_ctrl_partial_access.3972821482 |
|
|
Aug 03 06:07:52 PM PDT 24 |
Aug 03 06:09:39 PM PDT 24 |
1292371898 ps |
| T870 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3735560728 |
|
|
Aug 03 06:06:52 PM PDT 24 |
Aug 03 06:18:57 PM PDT 24 |
103496547325 ps |
| T871 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.163005294 |
|
|
Aug 03 06:13:55 PM PDT 24 |
Aug 03 06:13:58 PM PDT 24 |
490894573 ps |
| T872 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1539870261 |
|
|
Aug 03 06:12:11 PM PDT 24 |
Aug 03 07:24:19 PM PDT 24 |
123534948573 ps |
| T873 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3622727335 |
|
|
Aug 03 06:10:41 PM PDT 24 |
Aug 03 06:10:45 PM PDT 24 |
1405940363 ps |
| T874 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.659490487 |
|
|
Aug 03 06:17:01 PM PDT 24 |
Aug 03 06:18:44 PM PDT 24 |
796903205 ps |
| T875 |
/workspace/coverage/default/12.sram_ctrl_executable.3449939569 |
|
|
Aug 03 06:09:43 PM PDT 24 |
Aug 03 06:24:47 PM PDT 24 |
22075333574 ps |
| T876 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1007241185 |
|
|
Aug 03 06:14:46 PM PDT 24 |
Aug 03 06:14:50 PM PDT 24 |
1880470737 ps |
| T877 |
/workspace/coverage/default/23.sram_ctrl_bijection.2992591904 |
|
|
Aug 03 06:12:59 PM PDT 24 |
Aug 03 07:03:58 PM PDT 24 |
344848253557 ps |
| T878 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.3830337666 |
|
|
Aug 03 06:13:03 PM PDT 24 |
Aug 03 06:19:17 PM PDT 24 |
37429139909 ps |
| T879 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3647286591 |
|
|
Aug 03 06:16:15 PM PDT 24 |
Aug 03 06:18:52 PM PDT 24 |
7061309202 ps |
| T880 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.255003531 |
|
|
Aug 03 06:10:55 PM PDT 24 |
Aug 03 06:43:33 PM PDT 24 |
43890646852 ps |
| T881 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.870610064 |
|
|
Aug 03 06:14:16 PM PDT 24 |
Aug 03 06:14:53 PM PDT 24 |
15264667242 ps |
| T882 |
/workspace/coverage/default/35.sram_ctrl_regwen.2299079502 |
|
|
Aug 03 06:16:24 PM PDT 24 |
Aug 03 06:26:28 PM PDT 24 |
23236166936 ps |
| T883 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.4011884172 |
|
|
Aug 03 06:19:12 PM PDT 24 |
Aug 03 06:20:26 PM PDT 24 |
22606256228 ps |
| T884 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2772732272 |
|
|
Aug 03 06:17:06 PM PDT 24 |
Aug 03 06:17:22 PM PDT 24 |
9766775634 ps |
| T885 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1702831303 |
|
|
Aug 03 06:13:29 PM PDT 24 |
Aug 03 06:49:55 PM PDT 24 |
146715200851 ps |
| T886 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1056860250 |
|
|
Aug 03 06:17:46 PM PDT 24 |
Aug 03 06:19:04 PM PDT 24 |
51597223841 ps |
| T887 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2612982203 |
|
|
Aug 03 06:19:58 PM PDT 24 |
Aug 03 06:22:06 PM PDT 24 |
3799156537 ps |
| T888 |
/workspace/coverage/default/9.sram_ctrl_smoke.3022940790 |
|
|
Aug 03 06:08:48 PM PDT 24 |
Aug 03 06:10:03 PM PDT 24 |
1298504784 ps |
| T889 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.2224319421 |
|
|
Aug 03 06:14:42 PM PDT 24 |
Aug 03 06:30:59 PM PDT 24 |
340080760905 ps |
| T890 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.529104438 |
|
|
Aug 03 06:12:35 PM PDT 24 |
Aug 03 06:20:21 PM PDT 24 |
20009292252 ps |
| T891 |
/workspace/coverage/default/42.sram_ctrl_stress_all.767448806 |
|
|
Aug 03 06:18:53 PM PDT 24 |
Aug 03 07:59:50 PM PDT 24 |
83161716529 ps |
| T892 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2858631079 |
|
|
Aug 03 06:18:40 PM PDT 24 |
Aug 03 06:18:54 PM PDT 24 |
3637989329 ps |
| T893 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3805028601 |
|
|
Aug 03 06:09:54 PM PDT 24 |
Aug 03 06:26:27 PM PDT 24 |
10333382416 ps |
| T894 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.284501407 |
|
|
Aug 03 06:08:25 PM PDT 24 |
Aug 03 06:09:49 PM PDT 24 |
11455804365 ps |
| T895 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2590896123 |
|
|
Aug 03 06:15:05 PM PDT 24 |
Aug 03 06:17:32 PM PDT 24 |
5093314561 ps |
| T896 |
/workspace/coverage/default/26.sram_ctrl_smoke.3273594763 |
|
|
Aug 03 06:13:53 PM PDT 24 |
Aug 03 06:14:18 PM PDT 24 |
17385578164 ps |
| T897 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.3265793024 |
|
|
Aug 03 06:14:44 PM PDT 24 |
Aug 03 06:20:44 PM PDT 24 |
42289572452 ps |
| T898 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1125781228 |
|
|
Aug 03 06:19:33 PM PDT 24 |
Aug 03 06:19:36 PM PDT 24 |
361701650 ps |
| T899 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1212110853 |
|
|
Aug 03 06:06:06 PM PDT 24 |
Aug 03 06:14:56 PM PDT 24 |
23345192369 ps |
| T900 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.368665407 |
|
|
Aug 03 06:14:05 PM PDT 24 |
Aug 03 06:35:11 PM PDT 24 |
52066289435 ps |
| T901 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3066005062 |
|
|
Aug 03 06:15:54 PM PDT 24 |
Aug 03 06:23:30 PM PDT 24 |
36997616008 ps |
| T902 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3144288147 |
|
|
Aug 03 06:11:40 PM PDT 24 |
Aug 03 06:12:37 PM PDT 24 |
31502540606 ps |
| T903 |
/workspace/coverage/default/2.sram_ctrl_executable.37466342 |
|
|
Aug 03 06:06:34 PM PDT 24 |
Aug 03 06:08:04 PM PDT 24 |
7390044212 ps |
| T904 |
/workspace/coverage/default/17.sram_ctrl_regwen.4275527090 |
|
|
Aug 03 06:11:26 PM PDT 24 |
Aug 03 06:20:02 PM PDT 24 |
35920464068 ps |
| T905 |
/workspace/coverage/default/39.sram_ctrl_bijection.3825100112 |
|
|
Aug 03 06:17:41 PM PDT 24 |
Aug 03 06:28:56 PM PDT 24 |
111438458576 ps |
| T906 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.2744225723 |
|
|
Aug 03 06:15:32 PM PDT 24 |
Aug 03 06:15:49 PM PDT 24 |
2779525746 ps |
| T907 |
/workspace/coverage/default/19.sram_ctrl_partial_access.4214558560 |
|
|
Aug 03 06:11:47 PM PDT 24 |
Aug 03 06:11:57 PM PDT 24 |
2484805922 ps |
| T908 |
/workspace/coverage/default/6.sram_ctrl_smoke.3759045170 |
|
|
Aug 03 06:07:51 PM PDT 24 |
Aug 03 06:09:05 PM PDT 24 |
4489041125 ps |
| T909 |
/workspace/coverage/default/34.sram_ctrl_smoke.3782837951 |
|
|
Aug 03 06:16:00 PM PDT 24 |
Aug 03 06:16:11 PM PDT 24 |
2032005738 ps |
| T910 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.429274891 |
|
|
Aug 03 06:17:52 PM PDT 24 |
Aug 03 06:18:49 PM PDT 24 |
6279015440 ps |
| T911 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.2982365078 |
|
|
Aug 03 06:18:21 PM PDT 24 |
Aug 03 06:19:30 PM PDT 24 |
83157784225 ps |
| T912 |
/workspace/coverage/default/13.sram_ctrl_regwen.1437639048 |
|
|
Aug 03 06:10:01 PM PDT 24 |
Aug 03 06:42:45 PM PDT 24 |
4653025771 ps |
| T913 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2835112157 |
|
|
Aug 03 06:07:33 PM PDT 24 |
Aug 03 06:08:42 PM PDT 24 |
3095186035 ps |
| T914 |
/workspace/coverage/default/49.sram_ctrl_partial_access.4223396493 |
|
|
Aug 03 06:20:44 PM PDT 24 |
Aug 03 06:21:04 PM PDT 24 |
1082580244 ps |
| T915 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.19770733 |
|
|
Aug 03 06:14:53 PM PDT 24 |
Aug 03 06:23:33 PM PDT 24 |
25371532864 ps |
| T916 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.670484483 |
|
|
Aug 03 06:14:01 PM PDT 24 |
Aug 03 06:16:38 PM PDT 24 |
13855966159 ps |
| T917 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.303383616 |
|
|
Aug 03 06:12:04 PM PDT 24 |
Aug 03 06:12:08 PM PDT 24 |
362370825 ps |
| T918 |
/workspace/coverage/default/25.sram_ctrl_regwen.1537248248 |
|
|
Aug 03 06:13:36 PM PDT 24 |
Aug 03 06:27:41 PM PDT 24 |
26680377925 ps |
| T919 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.985469464 |
|
|
Aug 03 06:07:56 PM PDT 24 |
Aug 03 06:08:53 PM PDT 24 |
980569238 ps |
| T920 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.79466447 |
|
|
Aug 03 06:16:15 PM PDT 24 |
Aug 03 06:31:37 PM PDT 24 |
48760263347 ps |
| T921 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2564975906 |
|
|
Aug 03 06:19:00 PM PDT 24 |
Aug 03 06:21:39 PM PDT 24 |
4934328606 ps |
| T922 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1116593476 |
|
|
Aug 03 06:20:14 PM PDT 24 |
Aug 03 06:20:24 PM PDT 24 |
724962924 ps |
| T923 |
/workspace/coverage/default/49.sram_ctrl_smoke.2190238748 |
|
|
Aug 03 06:20:45 PM PDT 24 |
Aug 03 06:20:54 PM PDT 24 |
2920417462 ps |
| T924 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1204341182 |
|
|
Aug 03 06:06:06 PM PDT 24 |
Aug 03 06:10:25 PM PDT 24 |
15158172372 ps |
| T925 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1332877849 |
|
|
Aug 03 06:20:41 PM PDT 24 |
Aug 03 06:20:59 PM PDT 24 |
685112049 ps |
| T926 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1366145595 |
|
|
Aug 03 06:13:28 PM PDT 24 |
Aug 03 06:13:32 PM PDT 24 |
353754007 ps |
| T927 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.526622011 |
|
|
Aug 03 06:20:30 PM PDT 24 |
Aug 03 06:33:56 PM PDT 24 |
44749131371 ps |
| T928 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.921720521 |
|
|
Aug 03 06:17:19 PM PDT 24 |
Aug 03 06:17:29 PM PDT 24 |
2533294229 ps |
| T929 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1994051567 |
|
|
Aug 03 06:12:19 PM PDT 24 |
Aug 03 06:16:13 PM PDT 24 |
11658297945 ps |
| T930 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1992552576 |
|
|
Aug 03 06:19:23 PM PDT 24 |
Aug 03 06:32:32 PM PDT 24 |
5871496323 ps |
| T931 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2242178900 |
|
|
Aug 03 06:14:27 PM PDT 24 |
Aug 03 06:14:31 PM PDT 24 |
1404404521 ps |
| T932 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.1372601739 |
|
|
Aug 03 06:20:14 PM PDT 24 |
Aug 03 06:21:02 PM PDT 24 |
8815907438 ps |
| T933 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1185478266 |
|
|
Aug 03 06:10:20 PM PDT 24 |
Aug 03 06:10:42 PM PDT 24 |
865839137 ps |
| T934 |
/workspace/coverage/default/46.sram_ctrl_regwen.1223869010 |
|
|
Aug 03 06:19:54 PM PDT 24 |
Aug 03 06:28:46 PM PDT 24 |
19577957450 ps |
| T935 |
/workspace/coverage/default/42.sram_ctrl_bijection.212337781 |
|
|
Aug 03 06:18:36 PM PDT 24 |
Aug 03 06:37:11 PM PDT 24 |
66938939029 ps |
| T936 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1502994945 |
|
|
Aug 03 06:09:38 PM PDT 24 |
Aug 03 06:40:45 PM PDT 24 |
54195366618 ps |
| T937 |
/workspace/coverage/default/47.sram_ctrl_smoke.1119575128 |
|
|
Aug 03 06:20:04 PM PDT 24 |
Aug 03 06:22:20 PM PDT 24 |
1821124529 ps |
| T938 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.4161737258 |
|
|
Aug 03 06:19:34 PM PDT 24 |
Aug 03 06:20:39 PM PDT 24 |
1132047237 ps |
| T939 |
/workspace/coverage/default/12.sram_ctrl_bijection.619642185 |
|
|
Aug 03 06:09:36 PM PDT 24 |
Aug 03 06:36:35 PM PDT 24 |
72036974278 ps |
| T940 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2226267715 |
|
|
Aug 03 06:08:08 PM PDT 24 |
Aug 03 06:50:07 PM PDT 24 |
48930365919 ps |
| T941 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3024580927 |
|
|
Aug 03 06:18:08 PM PDT 24 |
Aug 03 06:18:09 PM PDT 24 |
17414270 ps |
| T942 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1160751274 |
|
|
Aug 03 06:09:06 PM PDT 24 |
Aug 03 06:21:47 PM PDT 24 |
63799024177 ps |
| T943 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.2043774671 |
|
|
Aug 03 06:10:43 PM PDT 24 |
Aug 03 06:14:47 PM PDT 24 |
4239198614 ps |
| T65 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3765553246 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:49:48 PM PDT 24 |
119142701 ps |
| T66 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3711399093 |
|
|
Aug 03 04:49:36 PM PDT 24 |
Aug 03 04:49:38 PM PDT 24 |
54016364 ps |
| T67 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2187490946 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:50:15 PM PDT 24 |
7403588057 ps |
| T82 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.340964467 |
|
|
Aug 03 04:50:02 PM PDT 24 |
Aug 03 04:50:02 PM PDT 24 |
26180261 ps |
| T83 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1691534422 |
|
|
Aug 03 04:49:57 PM PDT 24 |
Aug 03 04:49:58 PM PDT 24 |
15297607 ps |
| T115 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2017513782 |
|
|
Aug 03 04:49:56 PM PDT 24 |
Aug 03 04:49:57 PM PDT 24 |
15475735 ps |
| T944 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2237892874 |
|
|
Aug 03 04:49:37 PM PDT 24 |
Aug 03 04:49:40 PM PDT 24 |
371389560 ps |
| T945 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2148041726 |
|
|
Aug 03 04:49:56 PM PDT 24 |
Aug 03 04:50:00 PM PDT 24 |
3082778420 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3789726740 |
|
|
Aug 03 04:50:01 PM PDT 24 |
Aug 03 04:50:05 PM PDT 24 |
594291125 ps |
| T62 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.567479982 |
|
|
Aug 03 04:49:52 PM PDT 24 |
Aug 03 04:49:55 PM PDT 24 |
357089515 ps |
| T63 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.427552577 |
|
|
Aug 03 04:49:50 PM PDT 24 |
Aug 03 04:49:51 PM PDT 24 |
221643598 ps |
| T116 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2570252817 |
|
|
Aug 03 04:49:33 PM PDT 24 |
Aug 03 04:49:34 PM PDT 24 |
33855790 ps |
| T84 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2833879081 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:50:15 PM PDT 24 |
14758854723 ps |
| T117 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2396762231 |
|
|
Aug 03 04:49:34 PM PDT 24 |
Aug 03 04:49:35 PM PDT 24 |
16283761 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.213748180 |
|
|
Aug 03 04:49:44 PM PDT 24 |
Aug 03 04:49:45 PM PDT 24 |
528433542 ps |
| T947 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1271261445 |
|
|
Aug 03 04:49:59 PM PDT 24 |
Aug 03 04:50:02 PM PDT 24 |
3788870635 ps |
| T85 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2242526764 |
|
|
Aug 03 04:49:46 PM PDT 24 |
Aug 03 04:49:47 PM PDT 24 |
35779849 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.297607682 |
|
|
Aug 03 04:49:41 PM PDT 24 |
Aug 03 04:49:42 PM PDT 24 |
104079414 ps |
| T948 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1028576809 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:49:51 PM PDT 24 |
1490786848 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.141785953 |
|
|
Aug 03 04:49:35 PM PDT 24 |
Aug 03 04:50:28 PM PDT 24 |
14406265933 ps |
| T949 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2956742469 |
|
|
Aug 03 04:49:37 PM PDT 24 |
Aug 03 04:49:41 PM PDT 24 |
111954489 ps |
| T88 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1113797649 |
|
|
Aug 03 04:50:04 PM PDT 24 |
Aug 03 04:50:05 PM PDT 24 |
43086739 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2639417202 |
|
|
Aug 03 04:49:57 PM PDT 24 |
Aug 03 04:50:45 PM PDT 24 |
14443442035 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3731296562 |
|
|
Aug 03 04:49:40 PM PDT 24 |
Aug 03 04:49:44 PM PDT 24 |
4969523388 ps |
| T90 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2086919965 |
|
|
Aug 03 04:49:48 PM PDT 24 |
Aug 03 04:49:48 PM PDT 24 |
25835931 ps |
| T125 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1666859265 |
|
|
Aug 03 04:49:57 PM PDT 24 |
Aug 03 04:49:59 PM PDT 24 |
96124391 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1430449063 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:49:49 PM PDT 24 |
242286887 ps |
| T110 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.851653448 |
|
|
Aug 03 04:50:01 PM PDT 24 |
Aug 03 04:50:02 PM PDT 24 |
52982509 ps |
| T93 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2507733167 |
|
|
Aug 03 04:50:02 PM PDT 24 |
Aug 03 04:50:57 PM PDT 24 |
21382722124 ps |
| T126 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.952181338 |
|
|
Aug 03 04:49:50 PM PDT 24 |
Aug 03 04:49:52 PM PDT 24 |
350533151 ps |
| T127 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3896718194 |
|
|
Aug 03 04:49:50 PM PDT 24 |
Aug 03 04:49:51 PM PDT 24 |
221985614 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4237060462 |
|
|
Aug 03 04:50:02 PM PDT 24 |
Aug 03 04:50:03 PM PDT 24 |
24455174 ps |
| T952 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.565375768 |
|
|
Aug 03 04:49:36 PM PDT 24 |
Aug 03 04:49:37 PM PDT 24 |
44002530 ps |
| T953 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2097452186 |
|
|
Aug 03 04:49:48 PM PDT 24 |
Aug 03 04:49:50 PM PDT 24 |
296287108 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1647933364 |
|
|
Aug 03 04:49:54 PM PDT 24 |
Aug 03 04:49:55 PM PDT 24 |
36023670 ps |
| T128 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3512004706 |
|
|
Aug 03 04:49:58 PM PDT 24 |
Aug 03 04:50:00 PM PDT 24 |
107904040 ps |
| T955 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3322225733 |
|
|
Aug 03 04:50:00 PM PDT 24 |
Aug 03 04:50:03 PM PDT 24 |
55497620 ps |
| T956 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3842706669 |
|
|
Aug 03 04:49:46 PM PDT 24 |
Aug 03 04:49:47 PM PDT 24 |
16831812 ps |
| T94 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2399377560 |
|
|
Aug 03 04:49:40 PM PDT 24 |
Aug 03 04:49:41 PM PDT 24 |
14853078 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2945491857 |
|
|
Aug 03 04:50:01 PM PDT 24 |
Aug 03 04:50:05 PM PDT 24 |
2315301901 ps |
| T958 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.956379458 |
|
|
Aug 03 04:49:34 PM PDT 24 |
Aug 03 04:49:35 PM PDT 24 |
19541591 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3126823606 |
|
|
Aug 03 04:49:37 PM PDT 24 |
Aug 03 04:49:38 PM PDT 24 |
44196675 ps |
| T960 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3887391716 |
|
|
Aug 03 04:49:54 PM PDT 24 |
Aug 03 04:49:57 PM PDT 24 |
1410394897 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1278990884 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:49:50 PM PDT 24 |
356478158 ps |
| T962 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.245791292 |
|
|
Aug 03 04:49:52 PM PDT 24 |
Aug 03 04:49:53 PM PDT 24 |
66161249 ps |
| T963 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.894283291 |
|
|
Aug 03 04:49:50 PM PDT 24 |
Aug 03 04:49:54 PM PDT 24 |
289514134 ps |
| T964 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2438437008 |
|
|
Aug 03 04:49:52 PM PDT 24 |
Aug 03 04:49:57 PM PDT 24 |
627405697 ps |
| T965 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1528177757 |
|
|
Aug 03 04:49:59 PM PDT 24 |
Aug 03 04:50:04 PM PDT 24 |
229995202 ps |
| T129 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3551643328 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:49:49 PM PDT 24 |
307332193 ps |
| T966 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1277429972 |
|
|
Aug 03 04:49:36 PM PDT 24 |
Aug 03 04:49:38 PM PDT 24 |
258055683 ps |
| T133 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1420281795 |
|
|
Aug 03 04:49:40 PM PDT 24 |
Aug 03 04:49:43 PM PDT 24 |
643267439 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1169798357 |
|
|
Aug 03 04:49:40 PM PDT 24 |
Aug 03 04:49:40 PM PDT 24 |
31397975 ps |
| T95 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1870829697 |
|
|
Aug 03 04:49:41 PM PDT 24 |
Aug 03 04:50:26 PM PDT 24 |
7231391765 ps |
| T968 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.931447953 |
|
|
Aug 03 04:49:58 PM PDT 24 |
Aug 03 04:49:59 PM PDT 24 |
15018357 ps |
| T96 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2526032151 |
|
|
Aug 03 04:50:00 PM PDT 24 |
Aug 03 04:50:50 PM PDT 24 |
7429141443 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1477985411 |
|
|
Aug 03 04:49:52 PM PDT 24 |
Aug 03 04:49:53 PM PDT 24 |
161475767 ps |
| T970 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2311723616 |
|
|
Aug 03 04:49:36 PM PDT 24 |
Aug 03 04:49:38 PM PDT 24 |
81687746 ps |
| T97 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2054686128 |
|
|
Aug 03 04:49:36 PM PDT 24 |
Aug 03 04:49:37 PM PDT 24 |
45018612 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4146121789 |
|
|
Aug 03 04:49:57 PM PDT 24 |
Aug 03 04:50:00 PM PDT 24 |
435606760 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1582700574 |
|
|
Aug 03 04:50:01 PM PDT 24 |
Aug 03 04:50:02 PM PDT 24 |
97599334 ps |
| T973 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1886893775 |
|
|
Aug 03 04:49:57 PM PDT 24 |
Aug 03 04:50:00 PM PDT 24 |
155634230 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1627275739 |
|
|
Aug 03 04:49:42 PM PDT 24 |
Aug 03 04:49:43 PM PDT 24 |
88133028 ps |
| T975 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.613854696 |
|
|
Aug 03 04:50:00 PM PDT 24 |
Aug 03 04:50:04 PM PDT 24 |
428040334 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.11982240 |
|
|
Aug 03 04:49:37 PM PDT 24 |
Aug 03 04:50:08 PM PDT 24 |
61372371526 ps |
| T102 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2075170612 |
|
|
Aug 03 04:50:00 PM PDT 24 |
Aug 03 04:50:38 PM PDT 24 |
33479676979 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1223124041 |
|
|
Aug 03 04:49:37 PM PDT 24 |
Aug 03 04:49:40 PM PDT 24 |
222196939 ps |
| T131 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2098425606 |
|
|
Aug 03 04:49:52 PM PDT 24 |
Aug 03 04:49:54 PM PDT 24 |
789105087 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1973010111 |
|
|
Aug 03 04:49:40 PM PDT 24 |
Aug 03 04:49:44 PM PDT 24 |
3081991263 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.771948264 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:49:48 PM PDT 24 |
31432007 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3572410715 |
|
|
Aug 03 04:49:41 PM PDT 24 |
Aug 03 04:49:45 PM PDT 24 |
139961897 ps |
| T103 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1378770434 |
|
|
Aug 03 04:49:47 PM PDT 24 |
Aug 03 04:50:20 PM PDT 24 |
16755620915 ps |
| T104 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1330259222 |
|
|
Aug 03 04:50:00 PM PDT 24 |
Aug 03 04:50:53 PM PDT 24 |
29321746003 ps |
| T130 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.495576552 |
|
|
Aug 03 04:50:04 PM PDT 24 |
Aug 03 04:50:06 PM PDT 24 |
268559934 ps |
| T105 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.196496161 |
|
|
Aug 03 04:49:53 PM PDT 24 |
Aug 03 04:50:45 PM PDT 24 |
8226197688 ps |
| T980 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.95140845 |
|
|
Aug 03 04:49:48 PM PDT 24 |
Aug 03 04:49:49 PM PDT 24 |
49021836 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1767359079 |
|
|
Aug 03 04:49:40 PM PDT 24 |
Aug 03 04:50:09 PM PDT 24 |
3864225272 ps |
| T106 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3214799606 |
|
|
Aug 03 04:49:46 PM PDT 24 |
Aug 03 04:50:36 PM PDT 24 |
14757011311 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.178484517 |
|
|
Aug 03 04:49:34 PM PDT 24 |
Aug 03 04:50:20 PM PDT 24 |
7537254319 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1203953176 |
|
|
Aug 03 04:49:35 PM PDT 24 |
Aug 03 04:49:37 PM PDT 24 |
104478319 ps |
| T983 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3915375082 |
|
|
Aug 03 04:49:56 PM PDT 24 |
Aug 03 04:49:59 PM PDT 24 |
728830140 ps |
| T984 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3139717417 |
|
|
Aug 03 04:49:52 PM PDT 24 |
Aug 03 04:49:53 PM PDT 24 |
70719216 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1717282734 |
|
|
Aug 03 04:49:54 PM PDT 24 |
Aug 03 04:50:47 PM PDT 24 |
19549123455 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3335515285 |
|
|
Aug 03 04:49:56 PM PDT 24 |
Aug 03 04:49:57 PM PDT 24 |
27429136 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.570044354 |
|
|
Aug 03 04:49:40 PM PDT 24 |
Aug 03 04:49:41 PM PDT 24 |
20775724 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.600390696 |
|
|
Aug 03 04:49:43 PM PDT 24 |
Aug 03 04:49:47 PM PDT 24 |
4331586420 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.259117878 |
|
|
Aug 03 04:49:49 PM PDT 24 |
Aug 03 04:49:50 PM PDT 24 |
81850295 ps |
| T990 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1937767325 |
|
|
Aug 03 04:50:04 PM PDT 24 |
Aug 03 04:50:05 PM PDT 24 |
24992960 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2517469629 |
|
|
Aug 03 04:49:48 PM PDT 24 |
Aug 03 04:49:48 PM PDT 24 |
21672143 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3855624314 |
|
|
Aug 03 04:49:43 PM PDT 24 |
Aug 03 04:49:45 PM PDT 24 |
685042236 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2290610563 |
|
|
Aug 03 04:49:39 PM PDT 24 |
Aug 03 04:49:40 PM PDT 24 |
51876342 ps |
| T994 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2337514270 |
|
|
Aug 03 04:49:46 PM PDT 24 |
Aug 03 04:50:44 PM PDT 24 |
8112102818 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2413592435 |
|
|
Aug 03 04:49:37 PM PDT 24 |
Aug 03 04:49:38 PM PDT 24 |
36768493 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4201800928 |
|
|
Aug 03 04:50:02 PM PDT 24 |
Aug 03 04:50:06 PM PDT 24 |
4311162164 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.607808726 |
|
|
Aug 03 04:49:53 PM PDT 24 |
Aug 03 04:49:53 PM PDT 24 |
38618086 ps |
| T998 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2644853075 |
|
|
Aug 03 04:49:42 PM PDT 24 |
Aug 03 04:49:44 PM PDT 24 |
82955271 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3817150140 |
|
|
Aug 03 04:50:01 PM PDT 24 |
Aug 03 04:50:04 PM PDT 24 |
714950635 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3091015780 |
|
|
Aug 03 04:49:43 PM PDT 24 |
Aug 03 04:49:43 PM PDT 24 |
19480228 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2921758122 |
|
|
Aug 03 04:49:40 PM PDT 24 |
Aug 03 04:49:43 PM PDT 24 |
205339105 ps |
| T1002 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3416327095 |
|
|
Aug 03 04:49:48 PM PDT 24 |
Aug 03 04:49:52 PM PDT 24 |
1418558408 ps |
| T1003 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1281870068 |
|
|
Aug 03 04:49:46 PM PDT 24 |
Aug 03 04:49:50 PM PDT 24 |
1465477534 ps |