Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	357426000	1			T1	465270		T3	424426		T4	7476
instr_valid_dis	318270910	1			T1	465270		T3	424426		T4	7476
instr_en	27276059	1			T25	76394		T27	41170		T30	472344

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15817764	1			T25	3136		T27	79924		T30	87572
sram_ifetch_valid_disable	316508506	1			T1	465270		T3	424426		T4	7476
sram_ifetch_enable	25099730	1			T25	218342		T27	101970		T30	109730

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	357426000	1			T1	465270		T3	424426		T4	7476
hw_debug_en_valid_off	317851453	1			T1	465270		T3	424426		T4	7476
hw_debug_en_on	24056007	1			T25	221990		T27	158848		T30	104560

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	316508506	1			T1	465270		T3	424426		T4	7476
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	301612790	1			T1	465270		T3	424426		T4	7476
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8502055	1			T25	40896		T30	275042		T18	163474
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	9384660	1			T25	3136		T30	26466		T18	288695
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4547584	1			T18	252614		T47	12698		T74	4350
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4220874	1			T25	3136		T30	26466		T18	360808
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4216484	1			T27	79924		T30	19936		T18	40140
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1972812	1			T27	79924		T18	11062		T146	62
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1582194	1			T30	19936		T18	29078		T116	12162
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9228851	1			T25	149896		T27	48154		T30	58846
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3026513	1			T25	106434		T27	48154		T147	13148
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3497468	1			T25	62		T30	58846		T18	40986

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	12188404	1			T25	32362		T27	41170		T30	109730
lc_exec_en	10610672	1			T25	72094		T27	30770		T30	25778
valid_exec_dis	307665177	1			T1	465270		T3	424426		T4	7476
invalid_exec_dis	40917494	1			T25	221478		T27	181894		T30	197302