Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	148329511	1			T1	211518		T3	192754		T4	3058
triple_byte_access	2917511	1			T1	4224		T3	3944		T4	124
halfword_access	4475115	1			T1	6325		T3	5770		T4	201
byte_access	6245431	1			T1	8478		T3	7811		T4	271
zero_access	1880341	1			T1	2090		T3	1934		T4	84

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81630398

1

T1

116034

T3

105925

T4

1848

auto[1]

82217511

1

T1

116601

T3

106288

T4

1890

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	73732419	1			T1	105435		T3	96189		T4	1509
auto[0]	triple_byte_access	1394508	1			T1	2118		T3	2020		T4	68
auto[0]	halfword_access	2188912	1			T1	3144		T3	2887		T4	86
auto[0]	byte_access	3196173	1			T1	4272		T3	3840		T4	129
auto[0]	zero_access	1118386	1			T1	1065		T3	989		T4	56
auto[1]	word_access	74597092	1			T1	106083		T3	96565		T4	1549
auto[1]	triple_byte_access	1523003	1			T1	2106		T3	1924		T4	56
auto[1]	halfword_access	2286203	1			T1	3181		T3	2883		T4	115
auto[1]	byte_access	3049258	1			T1	4206		T3	3971		T4	142
auto[1]	zero_access	761955	1			T1	1025		T3	945		T4	28