| T797 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3370396102 |
|
|
Aug 04 05:48:36 PM PDT 24 |
Aug 04 05:49:46 PM PDT 24 |
45596271611 ps |
| T798 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3865186433 |
|
|
Aug 04 05:54:10 PM PDT 24 |
Aug 04 05:55:59 PM PDT 24 |
3006596373 ps |
| T799 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.1309167225 |
|
|
Aug 04 05:55:42 PM PDT 24 |
Aug 04 05:59:13 PM PDT 24 |
3069982616 ps |
| T800 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3845106445 |
|
|
Aug 04 05:48:51 PM PDT 24 |
Aug 04 05:49:28 PM PDT 24 |
5836092518 ps |
| T801 |
/workspace/coverage/default/11.sram_ctrl_partial_access.2837160367 |
|
|
Aug 04 05:48:00 PM PDT 24 |
Aug 04 05:48:19 PM PDT 24 |
1424642285 ps |
| T802 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1595819205 |
|
|
Aug 04 05:53:20 PM PDT 24 |
Aug 04 05:53:24 PM PDT 24 |
1345164395 ps |
| T803 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3540932072 |
|
|
Aug 04 05:48:37 PM PDT 24 |
Aug 04 05:48:47 PM PDT 24 |
699397891 ps |
| T804 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2142382399 |
|
|
Aug 04 05:55:34 PM PDT 24 |
Aug 04 05:55:53 PM PDT 24 |
7464184433 ps |
| T805 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3274176856 |
|
|
Aug 04 05:49:12 PM PDT 24 |
Aug 04 05:51:12 PM PDT 24 |
37191598350 ps |
| T806 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1951752389 |
|
|
Aug 04 05:46:42 PM PDT 24 |
Aug 04 05:59:37 PM PDT 24 |
39149174825 ps |
| T807 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2885238712 |
|
|
Aug 04 05:53:50 PM PDT 24 |
Aug 04 05:59:03 PM PDT 24 |
14566756715 ps |
| T808 |
/workspace/coverage/default/36.sram_ctrl_regwen.504998163 |
|
|
Aug 04 05:53:19 PM PDT 24 |
Aug 04 06:03:21 PM PDT 24 |
57669685204 ps |
| T809 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3840423989 |
|
|
Aug 04 05:46:53 PM PDT 24 |
Aug 04 05:47:03 PM PDT 24 |
4524619342 ps |
| T810 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2530774681 |
|
|
Aug 04 05:46:20 PM PDT 24 |
Aug 04 05:51:04 PM PDT 24 |
3975744927 ps |
| T811 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.3883162363 |
|
|
Aug 04 05:47:16 PM PDT 24 |
Aug 04 05:49:21 PM PDT 24 |
9418900535 ps |
| T812 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.796697476 |
|
|
Aug 04 05:46:52 PM PDT 24 |
Aug 04 05:47:05 PM PDT 24 |
9324178209 ps |
| T813 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3354104934 |
|
|
Aug 04 05:46:25 PM PDT 24 |
Aug 04 05:49:01 PM PDT 24 |
1636402340 ps |
| T814 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.3634297781 |
|
|
Aug 04 05:51:03 PM PDT 24 |
Aug 04 05:53:39 PM PDT 24 |
10200481804 ps |
| T815 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.3757138180 |
|
|
Aug 04 05:54:02 PM PDT 24 |
Aug 04 05:54:06 PM PDT 24 |
360766743 ps |
| T816 |
/workspace/coverage/default/19.sram_ctrl_stress_all.4159137481 |
|
|
Aug 04 05:49:37 PM PDT 24 |
Aug 04 06:49:00 PM PDT 24 |
62610970985 ps |
| T817 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.427980417 |
|
|
Aug 04 05:50:51 PM PDT 24 |
Aug 04 05:53:47 PM PDT 24 |
6948079794 ps |
| T818 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1376411768 |
|
|
Aug 04 05:46:20 PM PDT 24 |
Aug 04 05:59:04 PM PDT 24 |
66283497568 ps |
| T819 |
/workspace/coverage/default/35.sram_ctrl_bijection.314436619 |
|
|
Aug 04 05:52:56 PM PDT 24 |
Aug 04 06:07:39 PM PDT 24 |
463703144118 ps |
| T820 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2234150950 |
|
|
Aug 04 05:52:09 PM PDT 24 |
Aug 04 05:52:13 PM PDT 24 |
1404261925 ps |
| T821 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1094804507 |
|
|
Aug 04 05:47:09 PM PDT 24 |
Aug 04 05:52:27 PM PDT 24 |
13986513616 ps |
| T822 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1251968252 |
|
|
Aug 04 05:49:20 PM PDT 24 |
Aug 04 05:57:40 PM PDT 24 |
45882545080 ps |
| T823 |
/workspace/coverage/default/10.sram_ctrl_alert_test.699160417 |
|
|
Aug 04 05:47:59 PM PDT 24 |
Aug 04 05:48:00 PM PDT 24 |
22843506 ps |
| T824 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2669776636 |
|
|
Aug 04 05:55:51 PM PDT 24 |
Aug 04 05:58:37 PM PDT 24 |
23179285784 ps |
| T825 |
/workspace/coverage/default/39.sram_ctrl_bijection.960868490 |
|
|
Aug 04 05:53:54 PM PDT 24 |
Aug 04 06:03:01 PM PDT 24 |
59661226091 ps |
| T826 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4119598506 |
|
|
Aug 04 05:47:40 PM PDT 24 |
Aug 04 05:47:59 PM PDT 24 |
1903642367 ps |
| T827 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.775418723 |
|
|
Aug 04 05:51:59 PM PDT 24 |
Aug 04 05:56:15 PM PDT 24 |
15753546777 ps |
| T828 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1364214139 |
|
|
Aug 04 05:51:15 PM PDT 24 |
Aug 04 05:51:42 PM PDT 24 |
2677261618 ps |
| T829 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2269196058 |
|
|
Aug 04 05:49:25 PM PDT 24 |
Aug 04 05:51:57 PM PDT 24 |
9186444120 ps |
| T830 |
/workspace/coverage/default/26.sram_ctrl_smoke.3727273027 |
|
|
Aug 04 05:50:52 PM PDT 24 |
Aug 04 05:51:09 PM PDT 24 |
1859454360 ps |
| T831 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3674101446 |
|
|
Aug 04 05:51:11 PM PDT 24 |
Aug 04 05:59:23 PM PDT 24 |
78112035003 ps |
| T832 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1227247006 |
|
|
Aug 04 05:54:25 PM PDT 24 |
Aug 04 05:54:28 PM PDT 24 |
414488853 ps |
| T833 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1701231864 |
|
|
Aug 04 05:47:58 PM PDT 24 |
Aug 04 06:56:40 PM PDT 24 |
184434315097 ps |
| T834 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2813703992 |
|
|
Aug 04 05:56:02 PM PDT 24 |
Aug 04 06:01:05 PM PDT 24 |
5473322408 ps |
| T835 |
/workspace/coverage/default/27.sram_ctrl_partial_access.2886792207 |
|
|
Aug 04 05:51:11 PM PDT 24 |
Aug 04 05:51:33 PM PDT 24 |
17749677144 ps |
| T836 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1477030502 |
|
|
Aug 04 05:50:35 PM PDT 24 |
Aug 04 05:50:42 PM PDT 24 |
740932409 ps |
| T837 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.169717396 |
|
|
Aug 04 05:51:26 PM PDT 24 |
Aug 04 05:51:33 PM PDT 24 |
5120950594 ps |
| T838 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.95170011 |
|
|
Aug 04 05:50:20 PM PDT 24 |
Aug 04 05:51:16 PM PDT 24 |
755642952 ps |
| T839 |
/workspace/coverage/default/38.sram_ctrl_regwen.181174758 |
|
|
Aug 04 05:53:48 PM PDT 24 |
Aug 04 06:06:48 PM PDT 24 |
43936222431 ps |
| T840 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2426051390 |
|
|
Aug 04 05:48:25 PM PDT 24 |
Aug 04 05:48:59 PM PDT 24 |
9825591192 ps |
| T841 |
/workspace/coverage/default/30.sram_ctrl_stress_all.961793267 |
|
|
Aug 04 05:52:02 PM PDT 24 |
Aug 04 07:18:39 PM PDT 24 |
245706171846 ps |
| T842 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.1754433539 |
|
|
Aug 04 05:50:53 PM PDT 24 |
Aug 04 05:55:12 PM PDT 24 |
56300083819 ps |
| T843 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3171143097 |
|
|
Aug 04 05:50:28 PM PDT 24 |
Aug 04 05:51:08 PM PDT 24 |
17200531679 ps |
| T844 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1634048293 |
|
|
Aug 04 05:52:44 PM PDT 24 |
Aug 04 05:54:22 PM PDT 24 |
227670866748 ps |
| T845 |
/workspace/coverage/default/42.sram_ctrl_regwen.1254866689 |
|
|
Aug 04 05:54:40 PM PDT 24 |
Aug 04 06:23:57 PM PDT 24 |
95864189702 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.3355918728 |
|
|
Aug 04 05:53:09 PM PDT 24 |
Aug 04 05:54:40 PM PDT 24 |
11600289375 ps |
| T847 |
/workspace/coverage/default/44.sram_ctrl_alert_test.538013197 |
|
|
Aug 04 05:55:15 PM PDT 24 |
Aug 04 05:55:16 PM PDT 24 |
18798429 ps |
| T132 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3897797260 |
|
|
Aug 04 05:47:33 PM PDT 24 |
Aug 04 05:47:42 PM PDT 24 |
237805804 ps |
| T848 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1573068188 |
|
|
Aug 04 05:47:09 PM PDT 24 |
Aug 04 05:48:18 PM PDT 24 |
1607756092 ps |
| T849 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1405191496 |
|
|
Aug 04 05:52:02 PM PDT 24 |
Aug 04 05:52:11 PM PDT 24 |
228842211 ps |
| T850 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2015428519 |
|
|
Aug 04 05:49:59 PM PDT 24 |
Aug 04 05:50:10 PM PDT 24 |
2856571379 ps |
| T851 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.3995263634 |
|
|
Aug 04 05:52:33 PM PDT 24 |
Aug 04 05:52:46 PM PDT 24 |
693425591 ps |
| T852 |
/workspace/coverage/default/32.sram_ctrl_alert_test.3209463825 |
|
|
Aug 04 05:52:27 PM PDT 24 |
Aug 04 05:52:27 PM PDT 24 |
61656614 ps |
| T853 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.281242113 |
|
|
Aug 04 05:47:52 PM PDT 24 |
Aug 04 05:48:42 PM PDT 24 |
13500496599 ps |
| T854 |
/workspace/coverage/default/26.sram_ctrl_stress_all.539409044 |
|
|
Aug 04 05:51:07 PM PDT 24 |
Aug 04 07:28:49 PM PDT 24 |
394313597259 ps |
| T855 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.241376732 |
|
|
Aug 04 05:48:12 PM PDT 24 |
Aug 04 05:52:26 PM PDT 24 |
2183346235 ps |
| T856 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.2355665643 |
|
|
Aug 04 05:53:53 PM PDT 24 |
Aug 04 06:14:50 PM PDT 24 |
7421762878 ps |
| T857 |
/workspace/coverage/default/36.sram_ctrl_partial_access.588475689 |
|
|
Aug 04 05:53:15 PM PDT 24 |
Aug 04 05:54:08 PM PDT 24 |
2234687035 ps |
| T858 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.4009085601 |
|
|
Aug 04 05:55:37 PM PDT 24 |
Aug 04 06:01:04 PM PDT 24 |
20740828503 ps |
| T859 |
/workspace/coverage/default/35.sram_ctrl_smoke.2564472521 |
|
|
Aug 04 05:52:56 PM PDT 24 |
Aug 04 05:53:05 PM PDT 24 |
1742716684 ps |
| T860 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.194147658 |
|
|
Aug 04 05:51:40 PM PDT 24 |
Aug 04 06:00:37 PM PDT 24 |
4681161475 ps |
| T861 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2741477357 |
|
|
Aug 04 05:52:37 PM PDT 24 |
Aug 04 05:52:52 PM PDT 24 |
5074501721 ps |
| T862 |
/workspace/coverage/default/33.sram_ctrl_bijection.1673880452 |
|
|
Aug 04 05:52:30 PM PDT 24 |
Aug 04 06:23:42 PM PDT 24 |
102936728734 ps |
| T863 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1156563960 |
|
|
Aug 04 05:47:53 PM PDT 24 |
Aug 04 06:05:24 PM PDT 24 |
16881668069 ps |
| T864 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1606265092 |
|
|
Aug 04 05:48:03 PM PDT 24 |
Aug 04 05:52:54 PM PDT 24 |
5691404992 ps |
| T865 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3227589728 |
|
|
Aug 04 05:51:41 PM PDT 24 |
Aug 04 05:53:16 PM PDT 24 |
793743557 ps |
| T866 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2805923734 |
|
|
Aug 04 05:56:11 PM PDT 24 |
Aug 04 06:08:51 PM PDT 24 |
32712128454 ps |
| T867 |
/workspace/coverage/default/23.sram_ctrl_bijection.3148706603 |
|
|
Aug 04 05:50:19 PM PDT 24 |
Aug 04 06:04:29 PM PDT 24 |
80573891575 ps |
| T868 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1628902277 |
|
|
Aug 04 05:48:03 PM PDT 24 |
Aug 04 05:49:27 PM PDT 24 |
1485347512 ps |
| T869 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.4244399486 |
|
|
Aug 04 05:46:50 PM PDT 24 |
Aug 04 05:47:24 PM PDT 24 |
1612212465 ps |
| T870 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.60260172 |
|
|
Aug 04 05:53:28 PM PDT 24 |
Aug 04 05:55:09 PM PDT 24 |
3442464861 ps |
| T871 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3627114938 |
|
|
Aug 04 05:52:11 PM PDT 24 |
Aug 04 05:52:25 PM PDT 24 |
451295932 ps |
| T872 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.890068051 |
|
|
Aug 04 05:55:36 PM PDT 24 |
Aug 04 05:57:59 PM PDT 24 |
7559581605 ps |
| T873 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3478657060 |
|
|
Aug 04 05:48:22 PM PDT 24 |
Aug 04 05:48:38 PM PDT 24 |
497629963 ps |
| T874 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1197169630 |
|
|
Aug 04 05:55:35 PM PDT 24 |
Aug 04 05:55:56 PM PDT 24 |
714130268 ps |
| T875 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2597019997 |
|
|
Aug 04 05:55:52 PM PDT 24 |
Aug 04 05:56:10 PM PDT 24 |
531140531 ps |
| T876 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.627161360 |
|
|
Aug 04 05:52:44 PM PDT 24 |
Aug 04 05:56:50 PM PDT 24 |
4124261909 ps |
| T877 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1836121193 |
|
|
Aug 04 05:48:13 PM PDT 24 |
Aug 04 05:49:30 PM PDT 24 |
2545194687 ps |
| T878 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3120196238 |
|
|
Aug 04 05:48:15 PM PDT 24 |
Aug 04 05:49:25 PM PDT 24 |
1495007712 ps |
| T879 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.363081015 |
|
|
Aug 04 05:49:32 PM PDT 24 |
Aug 04 05:53:47 PM PDT 24 |
8597271017 ps |
| T880 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.575492338 |
|
|
Aug 04 05:51:45 PM PDT 24 |
Aug 04 05:54:42 PM PDT 24 |
5011542147 ps |
| T881 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1419183930 |
|
|
Aug 04 05:48:50 PM PDT 24 |
Aug 04 05:48:54 PM PDT 24 |
345299280 ps |
| T882 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.2518458000 |
|
|
Aug 04 05:48:52 PM PDT 24 |
Aug 04 05:51:33 PM PDT 24 |
11798514484 ps |
| T883 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1536942885 |
|
|
Aug 04 05:52:23 PM PDT 24 |
Aug 04 05:55:19 PM PDT 24 |
43048918673 ps |
| T884 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2098605679 |
|
|
Aug 04 05:54:53 PM PDT 24 |
Aug 04 05:56:56 PM PDT 24 |
1586883780 ps |
| T885 |
/workspace/coverage/default/13.sram_ctrl_stress_all.322291366 |
|
|
Aug 04 05:48:31 PM PDT 24 |
Aug 04 07:13:53 PM PDT 24 |
532202233139 ps |
| T886 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.331428321 |
|
|
Aug 04 05:48:48 PM PDT 24 |
Aug 04 05:49:22 PM PDT 24 |
4250533947 ps |
| T887 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.4217682245 |
|
|
Aug 04 05:50:05 PM PDT 24 |
Aug 04 05:52:42 PM PDT 24 |
6017843260 ps |
| T888 |
/workspace/coverage/default/5.sram_ctrl_smoke.177146697 |
|
|
Aug 04 05:47:00 PM PDT 24 |
Aug 04 05:47:05 PM PDT 24 |
383901831 ps |
| T889 |
/workspace/coverage/default/32.sram_ctrl_bijection.1881648752 |
|
|
Aug 04 05:52:14 PM PDT 24 |
Aug 04 06:23:25 PM PDT 24 |
531963136356 ps |
| T890 |
/workspace/coverage/default/25.sram_ctrl_stress_all.1137226837 |
|
|
Aug 04 05:50:53 PM PDT 24 |
Aug 04 07:02:22 PM PDT 24 |
16405386461 ps |
| T891 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1252962140 |
|
|
Aug 04 05:52:14 PM PDT 24 |
Aug 04 05:54:16 PM PDT 24 |
3389726178 ps |
| T892 |
/workspace/coverage/default/45.sram_ctrl_smoke.2195794045 |
|
|
Aug 04 05:55:16 PM PDT 24 |
Aug 04 05:55:34 PM PDT 24 |
569056682 ps |
| T893 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3860922155 |
|
|
Aug 04 05:53:16 PM PDT 24 |
Aug 04 05:55:25 PM PDT 24 |
794447464 ps |
| T894 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.1196466812 |
|
|
Aug 04 05:49:12 PM PDT 24 |
Aug 04 05:52:01 PM PDT 24 |
6991934452 ps |
| T895 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3956605046 |
|
|
Aug 04 05:54:00 PM PDT 24 |
Aug 04 05:55:26 PM PDT 24 |
56566824757 ps |
| T896 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1715329797 |
|
|
Aug 04 05:46:23 PM PDT 24 |
Aug 04 05:47:39 PM PDT 24 |
475174325 ps |
| T897 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1789417396 |
|
|
Aug 04 05:49:35 PM PDT 24 |
Aug 04 05:49:55 PM PDT 24 |
3188485928 ps |
| T898 |
/workspace/coverage/default/28.sram_ctrl_regwen.905747049 |
|
|
Aug 04 05:51:33 PM PDT 24 |
Aug 04 06:03:21 PM PDT 24 |
10492420927 ps |
| T899 |
/workspace/coverage/default/7.sram_ctrl_partial_access.467764457 |
|
|
Aug 04 05:47:16 PM PDT 24 |
Aug 04 05:47:44 PM PDT 24 |
6783228624 ps |
| T900 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.54223032 |
|
|
Aug 04 05:46:27 PM PDT 24 |
Aug 04 05:46:30 PM PDT 24 |
360274075 ps |
| T901 |
/workspace/coverage/default/27.sram_ctrl_executable.2355728595 |
|
|
Aug 04 05:51:15 PM PDT 24 |
Aug 04 06:14:42 PM PDT 24 |
15288341803 ps |
| T902 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2251762977 |
|
|
Aug 04 05:50:19 PM PDT 24 |
Aug 04 05:50:37 PM PDT 24 |
598654961 ps |
| T903 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2719476518 |
|
|
Aug 04 05:50:02 PM PDT 24 |
Aug 04 06:06:53 PM PDT 24 |
27189781673 ps |
| T904 |
/workspace/coverage/default/5.sram_ctrl_executable.257716928 |
|
|
Aug 04 05:46:59 PM PDT 24 |
Aug 04 05:49:46 PM PDT 24 |
3407189061 ps |
| T905 |
/workspace/coverage/default/4.sram_ctrl_smoke.4048768359 |
|
|
Aug 04 05:46:46 PM PDT 24 |
Aug 04 05:49:04 PM PDT 24 |
586861709 ps |
| T906 |
/workspace/coverage/default/47.sram_ctrl_executable.3977015742 |
|
|
Aug 04 05:55:47 PM PDT 24 |
Aug 04 06:04:05 PM PDT 24 |
24840500581 ps |
| T907 |
/workspace/coverage/default/48.sram_ctrl_executable.337537799 |
|
|
Aug 04 05:56:05 PM PDT 24 |
Aug 04 06:13:10 PM PDT 24 |
27749974908 ps |
| T908 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.166505002 |
|
|
Aug 04 05:47:03 PM PDT 24 |
Aug 04 05:52:47 PM PDT 24 |
93987790368 ps |
| T909 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3511130126 |
|
|
Aug 04 05:54:07 PM PDT 24 |
Aug 04 05:57:16 PM PDT 24 |
8157492372 ps |
| T910 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1877180200 |
|
|
Aug 04 05:46:29 PM PDT 24 |
Aug 04 06:29:59 PM PDT 24 |
100339193275 ps |
| T911 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.4249406831 |
|
|
Aug 04 05:54:18 PM PDT 24 |
Aug 04 05:56:55 PM PDT 24 |
32453571746 ps |
| T912 |
/workspace/coverage/default/14.sram_ctrl_bijection.3268541631 |
|
|
Aug 04 05:48:34 PM PDT 24 |
Aug 04 06:10:07 PM PDT 24 |
79191321918 ps |
| T913 |
/workspace/coverage/default/9.sram_ctrl_bijection.2345414145 |
|
|
Aug 04 05:47:35 PM PDT 24 |
Aug 04 06:01:58 PM PDT 24 |
48542630339 ps |
| T914 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3074948684 |
|
|
Aug 04 05:46:14 PM PDT 24 |
Aug 04 05:56:20 PM PDT 24 |
25588420311 ps |
| T915 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3692058201 |
|
|
Aug 04 05:51:35 PM PDT 24 |
Aug 04 05:51:36 PM PDT 24 |
12459318 ps |
| T916 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.4051406555 |
|
|
Aug 04 05:53:47 PM PDT 24 |
Aug 04 05:53:51 PM PDT 24 |
1983347801 ps |
| T917 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1241183561 |
|
|
Aug 04 05:49:46 PM PDT 24 |
Aug 04 05:49:59 PM PDT 24 |
877359266 ps |
| T918 |
/workspace/coverage/default/44.sram_ctrl_bijection.375682477 |
|
|
Aug 04 05:55:03 PM PDT 24 |
Aug 04 06:11:41 PM PDT 24 |
61257816358 ps |
| T919 |
/workspace/coverage/default/4.sram_ctrl_partial_access.341390673 |
|
|
Aug 04 05:46:50 PM PDT 24 |
Aug 04 05:47:02 PM PDT 24 |
959880104 ps |
| T920 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3123135070 |
|
|
Aug 04 05:50:21 PM PDT 24 |
Aug 04 06:00:10 PM PDT 24 |
83000561970 ps |
| T921 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2843362357 |
|
|
Aug 04 05:54:29 PM PDT 24 |
Aug 04 05:57:24 PM PDT 24 |
5810642731 ps |
| T922 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.2791184494 |
|
|
Aug 04 05:50:28 PM PDT 24 |
Aug 04 05:57:00 PM PDT 24 |
187988010408 ps |
| T923 |
/workspace/coverage/default/19.sram_ctrl_smoke.277009498 |
|
|
Aug 04 05:49:27 PM PDT 24 |
Aug 04 05:49:44 PM PDT 24 |
2144257638 ps |
| T924 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1217092655 |
|
|
Aug 04 05:52:04 PM PDT 24 |
Aug 04 05:55:02 PM PDT 24 |
4588557158 ps |
| T925 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.797259720 |
|
|
Aug 04 05:52:35 PM PDT 24 |
Aug 04 05:52:55 PM PDT 24 |
3898675769 ps |
| T926 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1114246672 |
|
|
Aug 04 05:53:30 PM PDT 24 |
Aug 04 05:54:49 PM PDT 24 |
12497339061 ps |
| T927 |
/workspace/coverage/default/43.sram_ctrl_regwen.2102664722 |
|
|
Aug 04 05:54:56 PM PDT 24 |
Aug 04 06:07:05 PM PDT 24 |
34277187845 ps |
| T928 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2047654043 |
|
|
Aug 04 05:49:46 PM PDT 24 |
Aug 04 05:50:07 PM PDT 24 |
3697125254 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.431550091 |
|
|
Aug 04 05:54:03 PM PDT 24 |
Aug 04 05:57:01 PM PDT 24 |
1632245473 ps |
| T930 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.490770494 |
|
|
Aug 04 05:47:11 PM PDT 24 |
Aug 04 05:55:30 PM PDT 24 |
25274205732 ps |
| T931 |
/workspace/coverage/default/34.sram_ctrl_regwen.3275974384 |
|
|
Aug 04 05:52:49 PM PDT 24 |
Aug 04 05:55:24 PM PDT 24 |
909406893 ps |
| T932 |
/workspace/coverage/default/6.sram_ctrl_partial_access.2125929811 |
|
|
Aug 04 05:47:09 PM PDT 24 |
Aug 04 05:47:27 PM PDT 24 |
3786848071 ps |
| T933 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1370493686 |
|
|
Aug 04 05:52:56 PM PDT 24 |
Aug 04 05:57:14 PM PDT 24 |
17918514886 ps |
| T934 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3109248572 |
|
|
Aug 04 05:48:47 PM PDT 24 |
Aug 04 05:49:04 PM PDT 24 |
1992968615 ps |
| T935 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1478251645 |
|
|
Aug 04 05:55:35 PM PDT 24 |
Aug 04 06:05:01 PM PDT 24 |
29592087539 ps |
| T936 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.905202372 |
|
|
Aug 04 05:52:40 PM PDT 24 |
Aug 04 06:06:54 PM PDT 24 |
199109465337 ps |
| T937 |
/workspace/coverage/default/8.sram_ctrl_alert_test.578237246 |
|
|
Aug 04 05:47:30 PM PDT 24 |
Aug 04 05:47:31 PM PDT 24 |
22916842 ps |
| T938 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.887612772 |
|
|
Aug 04 05:48:27 PM PDT 24 |
Aug 04 06:06:24 PM PDT 24 |
87004617658 ps |
| T939 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.78475471 |
|
|
Aug 04 05:53:30 PM PDT 24 |
Aug 04 05:59:06 PM PDT 24 |
18682385964 ps |
| T940 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3771265275 |
|
|
Aug 04 05:49:19 PM PDT 24 |
Aug 04 05:55:54 PM PDT 24 |
16409845850 ps |
| T941 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3470259288 |
|
|
Aug 04 05:54:32 PM PDT 24 |
Aug 04 05:54:33 PM PDT 24 |
42439275 ps |
| T942 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3066442598 |
|
|
Aug 04 05:46:58 PM PDT 24 |
Aug 04 05:47:28 PM PDT 24 |
18216798088 ps |
| T943 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1742748326 |
|
|
Aug 04 05:50:37 PM PDT 24 |
Aug 04 05:51:57 PM PDT 24 |
25968384380 ps |
| T944 |
/workspace/coverage/default/36.sram_ctrl_executable.195140106 |
|
|
Aug 04 05:53:24 PM PDT 24 |
Aug 04 05:54:25 PM PDT 24 |
861435284 ps |
| T945 |
/workspace/coverage/default/49.sram_ctrl_bijection.3534793457 |
|
|
Aug 04 05:56:09 PM PDT 24 |
Aug 04 06:25:22 PM PDT 24 |
78358253644 ps |
| T946 |
/workspace/coverage/default/37.sram_ctrl_regwen.1536515504 |
|
|
Aug 04 05:53:28 PM PDT 24 |
Aug 04 06:09:58 PM PDT 24 |
11235190120 ps |
| T947 |
/workspace/coverage/default/48.sram_ctrl_partial_access.3369075539 |
|
|
Aug 04 05:55:59 PM PDT 24 |
Aug 04 05:56:16 PM PDT 24 |
16788646657 ps |
| T948 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1803881571 |
|
|
Aug 04 05:50:16 PM PDT 24 |
Aug 04 05:52:29 PM PDT 24 |
7903861285 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1925160670 |
|
|
Aug 04 04:30:06 PM PDT 24 |
Aug 04 04:30:08 PM PDT 24 |
27018894 ps |
| T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.772532594 |
|
|
Aug 04 04:29:57 PM PDT 24 |
Aug 04 04:29:57 PM PDT 24 |
40163212 ps |
| T950 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2325886704 |
|
|
Aug 04 04:30:09 PM PDT 24 |
Aug 04 04:30:11 PM PDT 24 |
169336776 ps |
| T79 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3040735772 |
|
|
Aug 04 04:29:54 PM PDT 24 |
Aug 04 04:29:55 PM PDT 24 |
13458579 ps |
| T951 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2158365012 |
|
|
Aug 04 04:29:50 PM PDT 24 |
Aug 04 04:29:53 PM PDT 24 |
43299466 ps |
| T71 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1878177282 |
|
|
Aug 04 04:29:43 PM PDT 24 |
Aug 04 04:29:45 PM PDT 24 |
96714917 ps |
| T121 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4293754035 |
|
|
Aug 04 04:29:56 PM PDT 24 |
Aug 04 04:29:57 PM PDT 24 |
87699953 ps |
| T122 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3761587045 |
|
|
Aug 04 04:30:15 PM PDT 24 |
Aug 04 04:30:16 PM PDT 24 |
57451760 ps |
| T123 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4549898 |
|
|
Aug 04 04:30:11 PM PDT 24 |
Aug 04 04:30:12 PM PDT 24 |
57231121 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1818627880 |
|
|
Aug 04 04:30:18 PM PDT 24 |
Aug 04 04:30:22 PM PDT 24 |
1438565827 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.796303086 |
|
|
Aug 04 04:30:10 PM PDT 24 |
Aug 04 04:30:13 PM PDT 24 |
259670533 ps |
| T86 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2642218435 |
|
|
Aug 04 04:29:53 PM PDT 24 |
Aug 04 04:29:54 PM PDT 24 |
73278855 ps |
| T953 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3693021811 |
|
|
Aug 04 04:30:10 PM PDT 24 |
Aug 04 04:30:15 PM PDT 24 |
367180745 ps |
| T954 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2244594219 |
|
|
Aug 04 04:30:13 PM PDT 24 |
Aug 04 04:30:15 PM PDT 24 |
60091237 ps |
| T87 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3661114847 |
|
|
Aug 04 04:29:58 PM PDT 24 |
Aug 04 04:30:31 PM PDT 24 |
14791293410 ps |
| T88 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3130604913 |
|
|
Aug 04 04:30:31 PM PDT 24 |
Aug 04 04:31:24 PM PDT 24 |
7344305958 ps |
| T124 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2090232550 |
|
|
Aug 04 04:31:25 PM PDT 24 |
Aug 04 04:31:26 PM PDT 24 |
61249322 ps |
| T89 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2206771556 |
|
|
Aug 04 04:29:50 PM PDT 24 |
Aug 04 04:29:51 PM PDT 24 |
16109648 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1049662915 |
|
|
Aug 04 04:29:57 PM PDT 24 |
Aug 04 04:30:02 PM PDT 24 |
257136969 ps |
| T73 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3828323501 |
|
|
Aug 04 04:30:04 PM PDT 24 |
Aug 04 04:30:06 PM PDT 24 |
165133571 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3341225747 |
|
|
Aug 04 04:29:50 PM PDT 24 |
Aug 04 04:29:54 PM PDT 24 |
32168332 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.708167144 |
|
|
Aug 04 04:30:21 PM PDT 24 |
Aug 04 04:30:22 PM PDT 24 |
267542106 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1760328074 |
|
|
Aug 04 04:30:02 PM PDT 24 |
Aug 04 04:30:06 PM PDT 24 |
369740148 ps |
| T959 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3957318680 |
|
|
Aug 04 04:30:02 PM PDT 24 |
Aug 04 04:30:05 PM PDT 24 |
346496129 ps |
| T90 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1992298738 |
|
|
Aug 04 04:30:14 PM PDT 24 |
Aug 04 04:30:15 PM PDT 24 |
100718250 ps |
| T960 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1014132412 |
|
|
Aug 04 04:30:13 PM PDT 24 |
Aug 04 04:30:17 PM PDT 24 |
115468199 ps |
| T961 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1901764329 |
|
|
Aug 04 04:30:05 PM PDT 24 |
Aug 04 04:30:10 PM PDT 24 |
137887620 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2006331341 |
|
|
Aug 04 04:29:58 PM PDT 24 |
Aug 04 04:29:59 PM PDT 24 |
64550749 ps |
| T962 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3718541001 |
|
|
Aug 04 04:30:03 PM PDT 24 |
Aug 04 04:30:04 PM PDT 24 |
11809520 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2586677834 |
|
|
Aug 04 04:29:49 PM PDT 24 |
Aug 04 04:29:50 PM PDT 24 |
51525257 ps |
| T963 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3435975109 |
|
|
Aug 04 04:30:22 PM PDT 24 |
Aug 04 04:30:25 PM PDT 24 |
351620073 ps |
| T93 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3049551442 |
|
|
Aug 04 04:30:07 PM PDT 24 |
Aug 04 04:30:35 PM PDT 24 |
17602760013 ps |
| T137 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2596188400 |
|
|
Aug 04 04:30:06 PM PDT 24 |
Aug 04 04:30:09 PM PDT 24 |
350526415 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1498534669 |
|
|
Aug 04 04:30:01 PM PDT 24 |
Aug 04 04:30:48 PM PDT 24 |
7343223078 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3004492460 |
|
|
Aug 04 04:30:19 PM PDT 24 |
Aug 04 04:30:20 PM PDT 24 |
45773773 ps |
| T144 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4103592728 |
|
|
Aug 04 04:30:10 PM PDT 24 |
Aug 04 04:30:12 PM PDT 24 |
295628465 ps |
| T965 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.638946245 |
|
|
Aug 04 04:30:00 PM PDT 24 |
Aug 04 04:30:03 PM PDT 24 |
78960464 ps |
| T143 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2707170826 |
|
|
Aug 04 04:30:06 PM PDT 24 |
Aug 04 04:30:07 PM PDT 24 |
203041084 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3805391527 |
|
|
Aug 04 04:30:02 PM PDT 24 |
Aug 04 04:30:05 PM PDT 24 |
951380759 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3067668714 |
|
|
Aug 04 04:29:52 PM PDT 24 |
Aug 04 04:29:54 PM PDT 24 |
65957504 ps |
| T95 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1455541749 |
|
|
Aug 04 04:30:59 PM PDT 24 |
Aug 04 04:31:00 PM PDT 24 |
15775704 ps |
| T968 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3219899981 |
|
|
Aug 04 04:30:18 PM PDT 24 |
Aug 04 04:30:19 PM PDT 24 |
27529823 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4206523363 |
|
|
Aug 04 04:29:51 PM PDT 24 |
Aug 04 04:29:51 PM PDT 24 |
71942916 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.143364902 |
|
|
Aug 04 04:29:50 PM PDT 24 |
Aug 04 04:29:55 PM PDT 24 |
1472458803 ps |
| T96 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.455363359 |
|
|
Aug 04 04:30:12 PM PDT 24 |
Aug 04 04:30:13 PM PDT 24 |
20248378 ps |
| T97 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.560601361 |
|
|
Aug 04 04:30:25 PM PDT 24 |
Aug 04 04:31:11 PM PDT 24 |
61516035331 ps |
| T971 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4245488320 |
|
|
Aug 04 04:31:05 PM PDT 24 |
Aug 04 04:31:07 PM PDT 24 |
177482185 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2047625244 |
|
|
Aug 04 04:30:27 PM PDT 24 |
Aug 04 04:30:28 PM PDT 24 |
39782171 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1020813894 |
|
|
Aug 04 04:29:43 PM PDT 24 |
Aug 04 04:29:44 PM PDT 24 |
38317500 ps |
| T98 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2181402816 |
|
|
Aug 04 04:29:58 PM PDT 24 |
Aug 04 04:30:31 PM PDT 24 |
16759925895 ps |
| T974 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1966297777 |
|
|
Aug 04 04:30:33 PM PDT 24 |
Aug 04 04:30:37 PM PDT 24 |
366817894 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1333867437 |
|
|
Aug 04 04:30:10 PM PDT 24 |
Aug 04 04:30:12 PM PDT 24 |
354148262 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3663067525 |
|
|
Aug 04 04:30:27 PM PDT 24 |
Aug 04 04:30:28 PM PDT 24 |
72458487 ps |
| T977 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3370394160 |
|
|
Aug 04 04:30:12 PM PDT 24 |
Aug 04 04:30:16 PM PDT 24 |
32810563 ps |
| T978 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2119889077 |
|
|
Aug 04 04:30:31 PM PDT 24 |
Aug 04 04:31:00 PM PDT 24 |
5281223565 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3468269322 |
|
|
Aug 04 04:29:55 PM PDT 24 |
Aug 04 04:29:58 PM PDT 24 |
442548993 ps |
| T980 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2857929462 |
|
|
Aug 04 04:30:14 PM PDT 24 |
Aug 04 04:30:43 PM PDT 24 |
8798729052 ps |
| T981 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2156402643 |
|
|
Aug 04 04:30:00 PM PDT 24 |
Aug 04 04:30:28 PM PDT 24 |
7776752925 ps |
| T982 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.335066249 |
|
|
Aug 04 04:29:48 PM PDT 24 |
Aug 04 04:29:53 PM PDT 24 |
1617176743 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3441300610 |
|
|
Aug 04 04:29:58 PM PDT 24 |
Aug 04 04:30:29 PM PDT 24 |
7710180707 ps |
| T983 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1762632117 |
|
|
Aug 04 04:30:15 PM PDT 24 |
Aug 04 04:30:16 PM PDT 24 |
40667675 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1739942023 |
|
|
Aug 04 04:30:18 PM PDT 24 |
Aug 04 04:30:21 PM PDT 24 |
345966249 ps |
| T135 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.597734793 |
|
|
Aug 04 04:30:33 PM PDT 24 |
Aug 04 04:30:34 PM PDT 24 |
159375029 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3476072579 |
|
|
Aug 04 04:29:47 PM PDT 24 |
Aug 04 04:29:51 PM PDT 24 |
1723602708 ps |
| T986 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3263356414 |
|
|
Aug 04 04:30:19 PM PDT 24 |
Aug 04 04:30:20 PM PDT 24 |
59716789 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1963053430 |
|
|
Aug 04 04:29:44 PM PDT 24 |
Aug 04 04:29:44 PM PDT 24 |
39416995 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4211215813 |
|
|
Aug 04 04:29:57 PM PDT 24 |
Aug 04 04:29:58 PM PDT 24 |
14246052 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3500222813 |
|
|
Aug 04 04:30:03 PM PDT 24 |
Aug 04 04:30:04 PM PDT 24 |
16132585 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3888299374 |
|
|
Aug 04 04:31:20 PM PDT 24 |
Aug 04 04:31:27 PM PDT 24 |
583115673 ps |
| T990 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1908163784 |
|
|
Aug 04 04:29:49 PM PDT 24 |
Aug 04 04:29:53 PM PDT 24 |
372918509 ps |
| T101 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3995257637 |
|
|
Aug 04 04:30:28 PM PDT 24 |
Aug 04 04:30:54 PM PDT 24 |
3797757849 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3915179630 |
|
|
Aug 04 04:29:52 PM PDT 24 |
Aug 04 04:29:53 PM PDT 24 |
18503470 ps |
| T136 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2265855224 |
|
|
Aug 04 04:30:08 PM PDT 24 |
Aug 04 04:30:10 PM PDT 24 |
75465779 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.506807716 |
|
|
Aug 04 04:31:02 PM PDT 24 |
Aug 04 04:31:09 PM PDT 24 |
22008394 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.264879515 |
|
|
Aug 04 04:30:18 PM PDT 24 |
Aug 04 04:30:21 PM PDT 24 |
349568493 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1051070457 |
|
|
Aug 04 04:29:55 PM PDT 24 |
Aug 04 04:29:56 PM PDT 24 |
29797826 ps |
| T109 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.768005721 |
|
|
Aug 04 04:30:24 PM PDT 24 |
Aug 04 04:30:25 PM PDT 24 |
34742949 ps |
| T995 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.587623088 |
|
|
Aug 04 04:31:02 PM PDT 24 |
Aug 04 04:31:06 PM PDT 24 |
1735694099 ps |
| T107 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.953574999 |
|
|
Aug 04 04:30:28 PM PDT 24 |
Aug 04 04:30:56 PM PDT 24 |
15464963812 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3755381889 |
|
|
Aug 04 04:30:59 PM PDT 24 |
Aug 04 04:31:03 PM PDT 24 |
1415951578 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.807109648 |
|
|
Aug 04 04:30:05 PM PDT 24 |
Aug 04 04:30:06 PM PDT 24 |
14045521 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1011588112 |
|
|
Aug 04 04:29:53 PM PDT 24 |
Aug 04 04:29:54 PM PDT 24 |
20185557 ps |
| T108 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3161534778 |
|
|
Aug 04 04:30:14 PM PDT 24 |
Aug 04 04:30:15 PM PDT 24 |
13362449 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2963053273 |
|
|
Aug 04 04:30:29 PM PDT 24 |
Aug 04 04:30:33 PM PDT 24 |
504705827 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.902653728 |
|
|
Aug 04 04:29:52 PM PDT 24 |
Aug 04 04:30:53 PM PDT 24 |
29333900660 ps |
| T1001 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4102414313 |
|
|
Aug 04 04:29:45 PM PDT 24 |
Aug 04 04:29:45 PM PDT 24 |
37814292 ps |
| T1002 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.337144699 |
|
|
Aug 04 04:29:59 PM PDT 24 |
Aug 04 04:30:04 PM PDT 24 |
1837272368 ps |
| T1003 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2719433277 |
|
|
Aug 04 04:30:33 PM PDT 24 |
Aug 04 04:30:37 PM PDT 24 |
117998367 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3702972865 |
|
|
Aug 04 04:30:21 PM PDT 24 |
Aug 04 04:30:22 PM PDT 24 |
45844482 ps |
| T1005 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.958289336 |
|
|
Aug 04 04:30:08 PM PDT 24 |
Aug 04 04:30:08 PM PDT 24 |
14976886 ps |
| T1006 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2814864039 |
|
|
Aug 04 04:29:56 PM PDT 24 |
Aug 04 04:29:57 PM PDT 24 |
100859923 ps |
| T118 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2563064822 |
|
|
Aug 04 04:30:12 PM PDT 24 |
Aug 04 04:31:03 PM PDT 24 |
7452198464 ps |
| T138 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1113227034 |
|
|
Aug 04 04:30:02 PM PDT 24 |
Aug 04 04:30:05 PM PDT 24 |
318887891 ps |
| T1007 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.671518770 |
|
|
Aug 04 04:30:12 PM PDT 24 |
Aug 04 04:30:16 PM PDT 24 |
368768674 ps |
| T139 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3834492014 |
|
|
Aug 04 04:30:17 PM PDT 24 |
Aug 04 04:30:18 PM PDT 24 |
102418313 ps |
| T1008 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3733966422 |
|
|
Aug 04 04:30:16 PM PDT 24 |
Aug 04 04:30:18 PM PDT 24 |
163400577 ps |
| T1009 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3957751150 |
|
|
Aug 04 04:30:24 PM PDT 24 |
Aug 04 04:30:25 PM PDT 24 |
89558022 ps |