Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	347747692	1			T1	60818		T2	11694		T3	13374
instr_valid_dis	313003478	1			T1	60818		T2	11694		T3	13374
instr_en	25112914	1			T11	146898		T23	323644		T28	40734

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12916606	1			T11	70576		T23	94290		T28	178340
sram_ifetch_valid_disable	308707965	1			T1	60818		T2	11694		T3	13374
sram_ifetch_enable	26123121	1			T11	62978		T23	195242		T28	78774

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	347747692	1			T1	60818		T2	11694		T3	13374
hw_debug_en_valid_off	306579916	1			T1	60818		T2	11694		T3	13374
hw_debug_en_on	28191598	1			T11	76834		T23	44888		T28	118806

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	308707965	1			T1	60818		T2	11694		T3	13374
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	294339859	1			T1	60818		T2	11694		T3	13374
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9515270	1			T11	68910		T23	34112		T84	41358
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4381580	1			T11	18372		T23	94236		T28	112454
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2170946	1			T28	112454		T84	20676		T71	89856
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1667138	1			T23	94236		T84	6518		T156	27532
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4339398	1			T11	14216		T23	54		T28	65886
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2221874	1			T24	38514		T25	43574		T71	62552
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1581554	1			T23	54		T151	37656		T156	15866
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11223754	1			T11	42618		T23	5974		T28	20070
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4164666	1			T11	19502		T28	20070		T24	170384
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3942798	1			T11	23116		T23	5974		T84	34702

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	11626038	1			T11	40000		T23	195242		T28	40734
lc_exec_en	12628446	1			T11	20000		T23	38860		T28	32850
valid_exec_dis	304500510	1			T1	60818		T2	11694		T3	13374
invalid_exec_dis	39039727	1			T11	133554		T23	289532		T28	257114