Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	144390606	1			T1	1537		T2	1055		T3	6060
triple_byte_access	2733187	1			T1	3470		T2	946		T3	114
halfword_access	4194155	1			T1	6268		T2	1436		T3	197
byte_access	5865986	1			T1	12070		T2	1918		T3	241
zero_access	1783198	1			T1	7064		T2	492		T3	75

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79435089

1

T1

14954

T2

2895

T3

3379

auto[1]

79532043

1

T1

15455

T2

2952

T3

3308

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	72002800	1			T1	131		T2	531		T3	3041
auto[0]	triple_byte_access	1303978	1			T1	645		T2	456		T3	57
auto[0]	halfword_access	2051685	1			T1	2133		T2	717		T3	103
auto[0]	byte_access	3009024	1			T1	6437		T2	952		T3	144
auto[0]	zero_access	1067602	1			T1	5608		T2	239		T3	34
auto[1]	word_access	72387806	1			T1	1406		T2	524		T3	3019
auto[1]	triple_byte_access	1429209	1			T1	2825		T2	490		T3	57
auto[1]	halfword_access	2142470	1			T1	4135		T2	719		T3	94
auto[1]	byte_access	2856962	1			T1	5633		T2	966		T3	97
auto[1]	zero_access	715596	1			T1	1456		T2	253		T3	41